Practical case: Series and parallel of capacitors

Materials

• 1 DC power supply, 5–9 V, current-limited (≤100 mA)
• 1 Breadboard and jumper wires
• 4 Electrolytic capacitors, 100 µF, ≥16 V (C1, C2, C3, C4)
• 2 Resistors, 1 kΩ, 0.25 W (R1, R2)
• 1 Digital multimeter (DMM) with voltage and capacitance modes
• 1 Insulated screwdriver (for controlled shorting to discharge, if needed)
• Optional: 1 Oscilloscope or stopwatch app (for RC time-constant checks)

Wiring guide

Abbreviations used in the schematic and measurements:
– V_A: Node between R1 and C1 (top of the series stack). Reference to GND for series‑branch voltage and timing.
– REF: Middle node between C1 and C2 (reference node to measure V across C1; also the top of C2).
– V_P: Node between R2 and the parallel capacitors C3/C4 (top of the parallel branch).

Steps:
– Turn the power supply off. Set it to 5–9 V.
– Series branch (left):
– From +V to R1, then from R1 to C1 (+ lead of C1).
– Connect C1 (−) to the REF node (middle).
– Connect C2 (+) to REF, and C2 (−) to GND.
– This orients C1 and C2 correctly for DC: C1 “+” toward +V; C2 “+” toward the middle node.
– Place a black dot on the R1–C1 node and label it V_A; place another black dot on the C1–C2 node and label it REF.
– Parallel branch (right):
– From +V to R2, then from R2 to a top node that splits into two legs.
– Connect C3 (+) from the top node to its bottom node; connect its bottom node to GND.
– Connect C4 (+) from the same top node to its bottom node; connect its bottom node to GND.
– Orient C3 and C4 with “+” on the top node side (toward +V) and “−” toward GND.
– Place a black dot on the R2 output/top of the parallel node and label it V_P.
– Double‑check that:
– All component leads go somewhere (no floating wires).
– All grounds share the same GND rail.
– Electrolytic polarities match the directions described.

Schematic

Configuración A: Capacitores en paralelo (C_eq = C1 + C2)

      Generador de señales
  (seno, 1 Vpp, 0 V offset)
Vin ────────────────┬───────────────● VIN
                    │
                   ┌┴┐  
                   │ │  R_S = 10 kΩ (serie)
                   │ │
                   └┬┘
                    │
                    ├───────────────● VOUT──────────────┬───────────
                    │                                   │
                   ┌┴┐                                 ┌┴┐
                   │ │                                 │ │
                   │ │                                 │ │
                   └┬┘                                 └┬┘
                    │                                   │
                    │  C1 = 100 nF (paralelo)           │  C2 = 100 nF (paralelo)
                    │                                   │
                    └───────────────┬───────────────────┘
                                    │
Tierra del generador ───────────────┴───────────────────● GND
                                                        │
                                                       GND


Configuración B: Capacitores en serie (C_eq = (C1·C2)/(C1+C2))

      Generador de señales
  (seno, 1 Vpp, 0 V offset)
Vin ────────────────┬───────────────● VIN
                    │
                   ┌┴┐  
                   │ │  R_S = 10 kΩ (serie)
                   │ │
                   └┬┘
                    │
                    ├───────────────● VOUT
                    │
                   ┌┴┐
                   │ │
                   │ │
                   └┬┘
                    │   C1 = 100 nF (serie)
                    ├────● VX
                    │
                   ┌┴┐
                   │ │
                   │ │
                   └┬┘
                    │   C2 = 100 nF (serie)
                    │
Tierra del generador ───────────────────────────────────● GND
                                                        │
                                                       GND

Measurements and tests

• Safety and prep:
  • Ensure capacitors are discharged before moving probes. To discharge, power off and wait 30–60 s; if needed, briefly bridge the node to GND through a 1 kΩ resistor (never short large caps directly with a wire).
• Power-on check:
  • Turn the supply on (5–9 V). Verify no components are warm or leaking.
• Series branch — voltage sharing:
  • With DMM in DC volts, black probe to GND, red probe to ● V_A:
    • • V_A should rise toward the supply voltage (+V).
  • Measure C2 voltage: black probe to GND, red probe to ● REF:
    • • This is V_C2; expect approximately +V/2 if C1 = C2.
  • Measure C1 voltage: black probe to ● REF, red probe to ● V_A:
    • • This is V_C1; expect approximately +V/2 if C1 = C2.
  • Observe V_C1 + V_C2 ≈ V_A ≈ +V.
• Parallel branch — same voltage across each capacitor:
  • With DMM in DC volts, black probe to GND, red probe to ● V_P:
    • • V_P ≈ +V (both C3 and C4 see the same voltage).
• Equivalent capacitance by capacitance meter (power off first):
  • Turn power off and discharge capacitors.
  • For series pair: disconnect the series branch from +V (lift the +V jumper to R1), then measure capacitance between ● V_A and GND:
    • • Expect C_eq(series) ≈ (C1·C2)/(C1 + C2) ≈ 50 µF if both are 100 µF.
  • For parallel pair: disconnect the parallel branch from +V (lift the +V jumper to R2), then measure capacitance between ● V_P and GND:
    • • Expect C_eq(parallel) ≈ C3 + C4 ≈ 200 µF.
• Optional RC time‑constant (tau) using voltage rise:
  • Power on, measure V_A versus time from 0 V after reconnecting the series branch.
    • • Time to reach 63% of final voltage ≈ τ_series = R1 · C_eq(series).
  • Similarly, measure V_P rise; 63% time ≈ τ_parallel = R2 · C_eq(parallel).
  • Compare measured τ to calculated values.

Common mistakes and safety

• Polarity reversed on electrolytics: C1 “+” must be toward V_A; C2 “+” toward REF; C3/C4 “+” toward V_P. Reverse connection can damage the capacitors.
• Measuring in current mode by mistake will short nodes—always check the DMM mode before probing.
• Not sharing a common ground between branches can produce confusing readings; ensure one GND rail is used.
• Handling charged capacitors: always discharge safely through a resistor before rewiring.

Improvements and explorations

• Add large-value “balancing” resistors (e.g., 470 kΩ) in parallel with C1 and C2 to ensure predictable voltage sharing and safe discharge.
• Try unequal values (e.g., 100 µF and 47 µF in series) to observe how voltage divides inversely with capacitance.
• Repeat tests at different supply voltages and note that series C_eq decreases while parallel C_eq increases as expected.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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