Level: Medium | Objective: Analyze and assemble a voltage doubler circuit to increase the peak voltage of an AC signal.

Objective and use case

In this practical case, you will build a half-wave voltage doubler (a basic Villard/Greinacher cascade) using two diodes and two capacitors. This circuit rectifies an AC input while simultaneously stepping up the voltage, yielding a DC output roughly twice the peak voltage of the AC source.

Why this circuit is useful in the real world:
* Generating high-voltage bias supplies for components like vacuum tubes, cathode ray tubes, or photomultipliers.
* Providing higher voltage rails for specific operational amplifier stages without requiring a custom, bulky step-up transformer.
* Powering low-current electrostatic devices, ionizers, or Geiger-Müller tubes.

Expected outcome:
* The input signal (V_in_AC) operates as a standard sinusoidal wave.
* The output voltage (V_out_DC) measures approximately 2 × Vpeak of the input signal, minus the forward voltage drops of the two diodes.
* Ripple voltage will be present on the DC output and will noticeably increase when a heavier load (lower resistance) is connected.

Target audience: Intermediate electronics students learning AC-to-DC conversion and fundamental multiplier topologies.

Materials

• V1: 12 Vrms (approx 17 Vpeak) AC source, 50/60 Hz, function: main AC input signal
• D1: 1N4007 rectifier diode, function: first clamping stage
• D2: 1N4007 rectifier diode, function: second peak rectifier stage
• C1: 100 µF / 50 V electrolytic capacitor, function: AC coupling and intermediate charge storage
• C2: 100 µF / 50 V electrolytic capacitor, function: output smoothing and final charge storage
• R1: 10 kΩ resistor, function: light output load to safely discharge capacitors after power off

Wiring guide

• V1: connects between node NODE_AC and node 0 (GND).
• C1: connects between node NODE_AC (negative terminal) and node NODE_MID (positive terminal).
• D1: connects between node 0 (anode) and node NODE_MID (cathode).
• D2: connects between node NODE_MID (anode) and node VOUT (cathode).
• C2: connects between node VOUT (positive terminal) and node 0 (negative terminal).
• R1: connects between node VOUT and node 0.

Conceptual block diagram

Schematic

GND
                                                        |
                                                  [ D1: 1N4007 ]
                                                        |
                                                        v
GND --> [ V1: 12Vrms AC ] --(NODE_AC)--> [ C1: 100µF ] --(NODE_MID)--> [ D2: 1N4007 ] --(VOUT)--> [ R1: 10 kΩ ] --> GND
                                                                                            |
                                                                                            +---> [ C2: 100µF ] --> GND

Electrical diagram

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Measurements and tests

1. Measure the AC Input Peak: Connect an oscilloscope or a multimeter (in AC mode) across node NODE_AC and node 0. A 12 Vrms input should read roughly 17 V peak.
2. Measure the Intermediate DC Voltage: Place a multimeter (in DC mode) across C1. You should read approximately Vpeak – 0.7 V (around 16.3 VDC).
3. Measure the Doubled Output (V_out_DC): Probe between VOUT and 0 in DC mode. The voltage should be approximately 2 × Vpeak – 1.4 V (around 32.6 VDC).
4. Observe Output Ripple: Switch the oscilloscope to AC coupling and probe VOUT. You will observe a ripple wave matching the frequency of the input source (half-wave rectification).
5. Test Load Dependency: Swap R1 for a 1 kΩ resistor. Notice how the output DC voltage sags and the ripple amplitude increases significantly, proving this topology is best suited for low-current applications.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Half-wave voltage doubler
.width out=256

* Main AC Input Signal (12 Vrms -> ~16.97 Vpeak, 50 Hz)
V1 NODE_AC 0 SIN(0 16.97056 50)

* AC coupling and intermediate charge storage
* Connected with NODE_MID as positive and NODE_AC as negative terminal
C1 NODE_MID NODE_AC 100u

* First clamping stage rectifier diode
D1 0 NODE_MID 1N4007

* Second peak rectifier stage diode
D2 NODE_MID VOUT 1N4007

* Output smoothing and final charge storage
C2 VOUT 0 100u

* Light output load to safely discharge capacitors
* ... (truncated in public view) ...

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* Practical case: Half-wave voltage doubler
.width out=256

* Main AC Input Signal (12 Vrms -> ~16.97 Vpeak, 50 Hz)
V1 NODE_AC 0 SIN(0 16.97056 50)

* AC coupling and intermediate charge storage
* Connected with NODE_MID as positive and NODE_AC as negative terminal
C1 NODE_MID NODE_AC 100u

* First clamping stage rectifier diode
D1 0 NODE_MID 1N4007

* Second peak rectifier stage diode
D2 NODE_MID VOUT 1N4007

* Output smoothing and final charge storage
C2 VOUT 0 100u

* Light output load to safely discharge capacitors
R1 VOUT 0 10k

* Diode Model for 1N4007
.model 1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1e-11 VJ=0.7 M=0.5 FC=0.5 TT=1e-07)

* Simulation Directives
.print tran V(NODE_AC) V(VOUT) V(NODE_MID)
.tran 100u 500m
.op
.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation shows the input AC voltage swinging between approximately -17V and +17V. The intermediate node (NODE_MID) is clamped and shifted, reaching a peak of about 32.6V. The output voltage (VOUT) successfully charges up to approximately 32V, which is nearly double the peak input voltage, confirming the voltage doubler operation.
* overall_comment: The SPICE netlist perfectly matches the BOM and wiring guide. The simulation results clearly demonstrate the expected behavior of a half-wave voltage doubler, with the output voltage reaching approximately twice the peak input voltage. This is an excellent didactic example.
* --------------------------------------

Simulation Results (Transient Analysis)

Analysis: The simulation shows the input AC voltage swinging between approximately -17V and +17V. The intermediate node (NODE_MID) is clamped and shifted, reaching a peak of about 32.6V. The output voltage (VOUT) successfully charges up to approximately 32V, which is nearly double the peak input voltage, confirming the voltage doubler operation.

Show raw data table (5027 rows)

Index   time            v(node_ac)      v(vout)         v(node_mid)
0	0.000000e+00	0.000000e+00	2.565925e-21	-1.89144e-18
1	1.000000e-06	5.331459e-03	5.419582e-10	5.331457e-03
2	2.000000e-06	1.066292e-02	1.097125e-09	1.066291e-02
3	4.000000e-06	2.132583e-02	2.236679e-09	2.132582e-02
4	8.000000e-06	4.265162e-02	4.716739e-09	4.265162e-02
5	1.600000e-05	8.530298e-02	1.109752e-08	8.530296e-02
6	2.994581e-05	1.596525e-01	3.640348e-08	1.596524e-01
7	4.360349e-05	2.324629e-01	1.285942e-07	2.324628e-01
8	5.923389e-05	3.157848e-01	6.926674e-07	3.157841e-01
9	7.569182e-05	4.035098e-01	4.463881e-06	4.035053e-01
10	9.313209e-05	4.964590e-01	3.310357e-05	4.964259e-01
11	1.114841e-04	5.942514e-01	2.714571e-04	5.939798e-01
12	1.306697e-04	6.964642e-01	2.279240e-03	6.941849e-01
13	1.507869e-04	8.036134e-01	1.447578e-02	7.891374e-01
14	1.727320e-04	9.204617e-01	5.134539e-02	8.691153e-01
15	1.929217e-04	1.027924e+00	1.015818e-01	9.263400e-01
16	2.144482e-04	1.142457e+00	1.586780e-01	9.837739e-01
17	2.454175e-04	1.307137e+00	2.410344e-01	1.066092e+00
18	2.845422e-04	1.515006e+00	3.449894e-01	1.169993e+00
19	3.627917e-04	1.930024e+00	5.525467e-01	1.377419e+00
20	4.627917e-04	2.458671e+00	8.169450e-01	1.641599e+00
21	5.627917e-04	2.984892e+00	1.080147e+00	1.904524e+00
22	6.627917e-04	3.508167e+00	1.341889e+00	2.165935e+00
23	7.627917e-04	4.027980e+00	1.601917e+00	2.425574e+00
... (5003 more rows) ...

Common mistakes and how to avoid them

• Reversing diode polarity: Installing D1 or D2 backward will either clamp the voltage to a negative potential instead of positive, or block the charge from reaching the output entirely. Always check the silver band indicating the cathode.
• Incorrect capacitor polarity: Electrolytic capacitors will fail or vent if reverse-biased. Ensure C1‘s positive terminal faces the diode junction (NODE_MID) and C2‘s positive terminal faces VOUT.
• Using capacitors with low voltage ratings: C2 must handle the fully doubled voltage (2 × Vpeak). Using a 25 V capacitor for a 34 V output will cause immediate failure. Always select capacitors rated for at least 2.5 × Vpeak of the AC source.

Troubleshooting

• Symptom: Output voltage is only equal to Vpeak (not doubled).
  • Cause: C1 is shorted, or D1 is open/damaged.
  • Fix: Verify D1‘s continuity using a multimeter diode test and check C1 for internal shorts.
• Symptom: Output voltage (VOUT) is zero or close to zero.
  • Cause: D2 is installed backwards (blocking the DC flow), or the load resistor R1 is completely shorted/too small, collapsing the multiplier’s charge.
  • Fix: Verify D2 orientation and ensure R1 is at least 10 kΩ for testing.
• Symptom: Loud pop or bulging capacitor upon power-up.
  • Cause: C2 voltage rating was exceeded or it was connected with reversed polarity.
  • Fix: Immediately disconnect power. Replace the damaged capacitor, double-checking correct polarity and a safe voltage rating (e.g., ≥ 50 V).

Possible improvements and extensions

• Add multiplier stages: Cascade additional diodes and capacitors to turn this circuit into a Cockcroft-Walton voltage tripler or quadrupler for even higher DC potentials.
• Build a full-wave voltage doubler: Reconfigure the circuit into a full-wave doubler topology to double the ripple frequency, which reduces the required size of the filter capacitors to maintain a stable output under load.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Who we are

Level: Medium. Design an astable NE555 oscillator where an LDR modulates the output frequency based on ambient light.

Objective and use case

In this project, you will build an astable oscillator using the 555 timer IC, where a Light Dependent Resistor (LDR) replaces one of the standard timing resistors. This substitution dynamically changes the pitch of a piezoelectric speaker depending on the amount of light hitting the sensor.

This circuit is highly useful in the real world:
* It serves as an auditory sensor for light warnings, such as an alarm for a refrigerator door left open.
* It acts as a fundamental building block for simple electronic musical instruments, like a basic optical theremin.
* It provides accessibility indicators, giving distinct audio feedback for visually impaired users to know if lights are turned on or off in a room.
* It demonstrates how to convert a varying analog physical property (luminosity) into a frequency-modulated electrical signal.

Expected outcome:
* The piezoelectric speaker will output a continuous, audible tone.
* The frequency (pitch) of the tone will increase significantly when the LDR is exposed to bright light.
* The frequency of the tone will drop to a lower pitch when the LDR is covered or in a dark environment.
* The primary timing capacitor will continuously charge and discharge between 1/3 and 2/3 of the supply voltage.

Target audience and level: Intermediate electronics students looking to combine analog sensors with standard timing ICs.

Materials

• V1: 9 V DC supply
• U1: NE555 timer IC, function: astable oscillator
• R1: 1 kΩ resistor, function: fixed timing resistor limiting discharge current
• R2: Photoresistor (LDR), function: variable timing resistor modulated by light
• C1: 100 nF ceramic capacitor, function: primary timing oscillator capacitor
• C2: 10 nF ceramic capacitor, function: control voltage stabilization for U1
• C3: 10 µF electrolytic capacitor, function: AC coupling for the speaker
• LS1: Piezoelectric speaker, function: audio output

Wiring guide

• V1: connects between node VCC and node 0 (GND).
• U1 Pin 1 (GND): connects to node 0.
• U1 Pin 8 (VCC): connects to node VCC.
• U1 Pin 4 (RESET): connects to node VCC.
• U1 Pin 7 (DISCHARGE): connects to node DISCH.
• U1 Pin 2 (TRIGGER): connects to node TRIG_THR.
• U1 Pin 6 (THRESHOLD): connects to node TRIG_THR.
• U1 Pin 5 (CONTROL): connects to node CTRL.
• U1 Pin 3 (OUTPUT): connects to node OUT.
• R1: connects between node VCC and node DISCH.
• R2: connects between node DISCH and node TRIG_THR.
• C1: connects between node TRIG_THR and node 0.
• C2: connects between node CTRL and node 0.
• C3: connects between node OUT (positive terminal) and node SPK_IN (negative terminal).
• LS1: connects between node SPK_IN and node 0.

Conceptual block diagram

Schematic

Inputs / Timing Network                                        Processing                      Output / Load
=======================                                        ==========                      =============

[ VCC --> R1: 1 kΩ ] -----------------------(DISCH: Pin 7)----> [ U1: NE555 Timer ]
                                                               [                 ]
[ Node DISCH --> R2: LDR (Light Mod.) ] ---(TRIG_THR: Pins 2,6)[                 ]
                                                               [  (Oscillator)   ] --(OUT: Pin 3)--> [ C3: 10µF ] --(SPK_IN)--> [ LS1: Speaker ] --> GND
[ Node TRIG_THR --> C1: 100nF --> GND ] ---(Timing Ref)------> [                 ]
                                                               [                 ]
[ Node CTRL --> C2: 10nF --> GND ] --------(CTRL: Pin 5)-----> [                 ]

Electrical diagram

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Measurements and tests

1. LDR resistance: Before inserting the LDR into the circuit, measure its resistance with a digital multimeter. Record the value in absolute darkness (it should be very high, e.g., > 50 kΩ) and under direct flashlight illumination (it should drop significantly, e.g., < 1 kΩ).
2. Capacitor voltage: Power the assembled circuit. Use an oscilloscope to probe the node TRIG_THR with respect to ground (node 0). You should observe a continuous charge-discharge waveform (resembling a shark fin or triangle) oscillating exactly between 3 V and 6 V (which correspond to 1/3 and 2/3 of the 9 V supply).
3. Output frequency: Connect an oscilloscope or a frequency counter to node OUT with respect to ground. Shine a flashlight directly onto the LDR and observe the frequency rise rapidly. Cover the sensor with your hand to simulate darkness and watch the frequency fall.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Light-controlled oscillator (NE555 astable)
.width out=256

.op
.tran 10u 5m uic
.print tran V(TRIG_THR) V(OUT) V(VCC) V(SPK_IN)

* Power Supply
V1 VCC 0 DC 9

* 555 Timer IC Subcircuit Definition
.subckt NE555 1 2 3 4 5 6 7 8
* Pins: 1:GND 2:TRIG 3:OUT 4:RESET 5:CTRL 6:THR 7:DISCH 8:VCC
* Internal voltage divider
R1 8 5 5k
R2 5 N_TRIG_REF 5k
R3 N_TRIG_REF 1 5k

* Comparators using continuous tanh functions for robust convergence
B_S N_S 1 V=0.5 + 0.5*tanh(100 * (V(N_TRIG_REF) - V(2)))
* ... (truncated in public view) ...

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* Light-controlled oscillator (NE555 astable)
.width out=256

.op
.tran 10u 5m uic
.print tran V(TRIG_THR) V(OUT) V(VCC) V(SPK_IN)

* Power Supply
V1 VCC 0 DC 9

* 555 Timer IC Subcircuit Definition
.subckt NE555 1 2 3 4 5 6 7 8
* Pins: 1:GND 2:TRIG 3:OUT 4:RESET 5:CTRL 6:THR 7:DISCH 8:VCC
* Internal voltage divider
R1 8 5 5k
R2 5 N_TRIG_REF 5k
R3 N_TRIG_REF 1 5k

* Comparators using continuous tanh functions for robust convergence
B_S N_S 1 V=0.5 + 0.5*tanh(100 * (V(N_TRIG_REF) - V(2)))
B_R N_R 1 V=0.5 + 0.5*tanh(100 * (V(6) - V(5)))
B_RESET N_RESET 1 V=0.5 + 0.5*tanh(100 * (0.7 - (V(4) - V(1))))

* SR Latch (Behavioral RC model ensuring smooth transitions)
B_INT N_INT 1 V=(V(N_RESET)<=0.5) * ( (V(N_S)>=0.5) + (V(N_S)<0.5) * (V(N_R)<=0.5) * V(N_INT_CAP) )
R_INT N_INT N_INT_CAP 100
C_INT N_INT_CAP 1 1n

* Output stage (Push-pull behavior)
B_OUT N_OUT 1 V=(V(N_INT_CAP)>0.5) * V(8)
R_OUT N_OUT 3 10

* Discharge stage (Open collector behavior)
B_DISCH 7 1 I=V(7) * ( (V(N_INT_CAP)<0.5)*0.1 + (V(N_INT_CAP)>=0.5)*1e-9 )
.ends

* Main Circuit
XU1 0 TRIG_THR OUT VCC CTRL TRIG_THR DISCH VCC NE555
R1 VCC DISCH 1k
R2 DISCH TRIG_THR 10k
C1 TRIG_THR 0 100n
C2 CTRL 0 10n
C3 OUT SPK_IN 10u
RLS1 SPK_IN 0 1k

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The transient simulation shows the trigger/threshold voltage oscillating between approximately 3V (1/3 VCC) and 6V (2/3 VCC), and the output toggling between near 0V and near 9V. The AC-coupled speaker input (SPK_IN) correctly centers around 0V during operation.
* bom_vs_spice equivalences ignored:
*   - Photoresistor (LDR) R2 modeled as a fixed 10k resistor.
*   - Piezoelectric speaker LS1 modeled as a 1k resistor RLS1.
* overall_comment: The SPICE netlist accurately represents the light-controlled oscillator described in the BOM and wiring guide. The NE555 subcircuit functions correctly as an astable multivibrator, and the simulation results confirm the expected oscillation. The circuit is perfectly suitable as a didactic example.
* --------------------------------------

Simulation Results (Transient Analysis)

Analysis: The transient simulation shows the trigger/threshold voltage oscillating between approximately 3V (1/3 VCC) and 6V (2/3 VCC), and the output toggling between near 0V and near 9V. The AC-coupled speaker input (SPK_IN) correctly centers around 0V during operation.

Show raw data table (631 rows)

Index   time            v(trig_thr)     v(out)          v(vcc)          v(spk_in)
0	1.000000e-07	8.901188e-06	0.000000e+00	9.000000e+00	0.000000e+00
1	1.014392e-07	2.067642e-05	8.910891e+00	9.000000e+00	8.910890e+00
2	1.043176e-07	4.422687e-05	8.910891e+00	9.000000e+00	8.910887e+00
3	1.100744e-07	9.132756e-05	8.910891e+00	9.000000e+00	8.910882e+00
4	1.215880e-07	1.855282e-04	8.910891e+00	9.000000e+00	8.910872e+00
5	1.446152e-07	3.739266e-04	8.910891e+00	9.000000e+00	8.910852e+00
6	1.906696e-07	7.507115e-04	8.910892e+00	9.000000e+00	8.910811e+00
7	2.827784e-07	1.504234e-03	8.910893e+00	9.000000e+00	8.910730e+00
8	4.361485e-07	2.758782e-03	8.910894e+00	9.000000e+00	8.910595e+00
9	6.136134e-07	4.210203e-03	8.910896e+00	9.000000e+00	8.910438e+00
10	8.824756e-07	6.408686e-03	8.910898e+00	9.000000e+00	8.910201e+00
11	1.315870e-06	9.951414e-03	8.910902e+00	9.000000e+00	8.909818e+00
12	2.182659e-06	1.703268e-02	8.910909e+00	9.000000e+00	8.909054e+00
13	3.916236e-06	3.117850e-02	8.910925e+00	9.000000e+00	8.907525e+00
14	7.383392e-06	5.940335e-02	8.910955e+00	9.000000e+00	8.904468e+00
15	1.000000e-05	8.064538e-02	8.910978e+00	9.000000e+00	8.902161e+00
16	1.069343e-05	8.626452e-02	8.910985e+00	9.000000e+00	8.901550e+00
17	1.208029e-05	9.749572e-02	8.910997e+00	9.000000e+00	8.900328e+00
18	1.485402e-05	1.199157e-01	8.911021e+00	9.000000e+00	8.897884e+00
19	2.040147e-05	1.645865e-01	8.911070e+00	9.000000e+00	8.892998e+00
20	3.040147e-05	2.445449e-01	8.911158e+00	9.000000e+00	8.884197e+00
21	4.040147e-05	3.237797e-01	8.911246e+00	9.000000e+00	8.875405e+00
22	5.040147e-05	4.022975e-01	8.911334e+00	9.000000e+00	8.866622e+00
23	6.040147e-05	4.801047e-01	8.911422e+00	9.000000e+00	8.857848e+00
... (607 more rows) ...

Common mistakes and how to avoid them

• Swapping the positions of R1 and the LDR: If the LDR is placed between VCC and pin 7 (DISCHARGE), intense light will drop its resistance to almost zero. When the NE555 attempts to discharge the capacitor by grounding pin 7, it will create a near short-circuit from VCC to ground, potentially destroying the IC. Always keep a fixed safety resistor (R1) in the upper position.
• Choosing the wrong value for C1: If C1 is too large (like a 10 µF electrolytic capacitor), the oscillator will run at a sub-audio frequency, producing a series of clicks rather than a tone. Stick to the 10 nF to 100 nF range for audible results.
• Omitting the AC coupling capacitor (C3): Connecting the piezo speaker directly from the output pin to ground forces a constant DC offset through the speaker, which draws unnecessary power and can degrade the component over time. Always use an AC coupling capacitor to block the DC component.

Troubleshooting

• Symptom: The speaker emits a continuous clicking or ticking sound instead of a musical tone.
  • Cause: The oscillation frequency is too low, likely below 20 Hz.
  • Fix: Check the value of C1. Ensure it is a 100 nF ceramic capacitor (often marked 104) and not a much larger electrolytic capacitor. Also, ensure the LDR is not in total darkness.
• Symptom: No sound is produced, and the NE555 chip feels hot to the touch.
  • Cause: A short circuit during the discharge cycle.
  • Fix: Disconnect power immediately. Verify that R1 is a fixed 1 kΩ resistor and that the LDR is strictly placed between pins 7 and 6, NOT between VCC and pin 7.
• Symptom: A tone is heard, but the pitch barely changes when waving a hand over the sensor.
  • Cause: The resistance swing of the LDR in current lighting conditions is too small, or ambient room light is too uniform.
  • Fix: Test the circuit by shining a highly focused light source (like a smartphone flashlight) directly onto the LDR, then completely covering it with a dark cup. If the tone still doesn’t change much, verify that R2 is indeed an LDR and not a standard fixed resistor by mistake.

Possible improvements and extensions

• Manual tuning potentiometer: Add a 10 kΩ potentiometer in series with the LDR. This allows you to manually offset the total resistance, providing a way to tune the «base pitch» of the oscillator for different room lighting conditions.
• Inverse light response: Modify the configuration so that pitch decreases as light increases. This can be achieved by rewiring the timing section (keeping safety resistors in mind) or by using a secondary transistor to invert the LDR’s behavior over the control voltage (Pin 5) of the NE555 instead of the standard timing network.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium – Use a very low-value resistor to indirectly measure a DC load’s current via voltage drop.

Objective and use case

You will build a direct current (DC) circuit featuring a primary dummy load and a low-value series resistor, known as a shunt. By measuring the tiny voltage drop across this shunt, you will indirectly calculate the total current flowing through the circuit using Ohm’s Law.

Why this is useful:
* Safe high-current measurement: Avoids running massive currents directly through your multimeter’s internal, potentially fragile, circuitry.
* Continuous monitoring: Allows microcontrollers or analog panels to constantly track power consumption without breaking the circuit.
* Overcurrent protection: Provides a proportional voltage signal that can trigger a shutdown mechanism if the current exceeds safe limits.
* Lowering burden voltage: Customizing the shunt size minimizes the interference the measurement instrument imposes on the operating circuit.

Expected outcome:
* You will generate a measurable millivolt-range voltage drop across the low-side shunt resistor.
* You will correctly calculate the load current ($I = V/R$) from the observed voltage.
* You will verify the power dissipation (P = I^2 × R) of the shunt to ensure it operates within safe thermal limits.

Target audience and level: Intermediate electronics students learning indirect measurement techniques and power calculations.

Materials

• V1: 12 V DC supply, function: main power source
• R_LOAD: 24 Ω resistor (10 W), function: primary DC load
• R_SHUNT: 1 Ω resistor (1 W), function: current sensing shunt
• VM1: Digital Multimeter, function: measure voltage drop across shunt

Wiring guide

• V1: connects positive terminal to node VCC and negative terminal to node 0 (GND).
• R_LOAD: connects between node VCC and node SENSE.
• R_SHUNT: connects between node SENSE and node 0 (GND).
• VM1: connects positive probe to node SENSE and negative probe to node 0 (GND) to measure the voltage drop across the shunt.

Conceptual block diagram

Schematic

[ V1: 12 V VCC ] --> [ R_LOAD: 24 Ω ] --(Node SENSE)--> [ R_SHUNT: 1 Ω ] --> GND
                                           |
                                           +--(+ probe)--> [ VM1: Multimeter ] --(- probe)--> GND

Electrical diagram

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Measurements and tests

1. Verify the power supply: Turn on V1 and measure the voltage at node VCC relative to node 0. It should read exactly 12 V.
2. Measure the shunt voltage (Vshunt): Set your multimeter to the DC millivolts or volts range. Measure the voltage at node SENSE relative to node 0. With a 24 Ω load and a 1 Ω shunt (25 Ω total), you should measure approximately 480 mV (0.48 V).
3. Calculate the current: Use Ohm’s law (I = Vshunt / Rshunt). Divide the 0.48 V measurement by 1 Ω. The total current flowing through the circuit is 480 mA (0.48 A).
4. Calculate power dissipation: Calculate the power dissipated by the shunt using P = Vshunt × I. In this case, 0.48 V × 0.48 A = 0.23 W. Because we selected a 1 W resistor, it is operating safely within its limits.
5. Measure load voltage drop: Measure the voltage between node VCC and node SENSE. It should be approximately 11.52 V, confirming that the shunt «steals» very little voltage from the primary load.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice)

* Practical case: Current measurement with shunt
.width out=256

* Main power source
V1 VCC 0 DC 12

* Primary DC load
R_LOAD VCC SENSE 24

* Current sensing shunt
R_SHUNT SENSE 0 1

* Simulation commands
.op
.tran 1u 100u

* Print the input voltage and the voltage drop across the shunt (VM1)
.print tran V(VCC) V(SENSE)

.end

Copy this content into a .cir file and run with ngspice.

Simulation Results (Transient Analysis)

Analysis: The simulation shows a constant 12V supply at VCC and a constant 0.48V at the SENSE node. This perfectly matches the theoretical voltage divider calculation (12V * 1Ω / 25Ω = 0.48V), indicating a current of 0.48A.

Show raw data table (108 rows)

Index   time            v(vcc)          v(sense)
0	0.000000e+00	1.200000e+01	4.800000e-01
1	1.000000e-08	1.200000e+01	4.800000e-01
2	2.000000e-08	1.200000e+01	4.800000e-01
3	4.000000e-08	1.200000e+01	4.800000e-01
4	8.000000e-08	1.200000e+01	4.800000e-01
5	1.600000e-07	1.200000e+01	4.800000e-01
6	3.200000e-07	1.200000e+01	4.800000e-01
7	6.400000e-07	1.200000e+01	4.800000e-01
8	1.280000e-06	1.200000e+01	4.800000e-01
9	2.280000e-06	1.200000e+01	4.800000e-01
10	3.280000e-06	1.200000e+01	4.800000e-01
11	4.280000e-06	1.200000e+01	4.800000e-01
12	5.280000e-06	1.200000e+01	4.800000e-01
13	6.280000e-06	1.200000e+01	4.800000e-01
14	7.280000e-06	1.200000e+01	4.800000e-01
15	8.280000e-06	1.200000e+01	4.800000e-01
16	9.280000e-06	1.200000e+01	4.800000e-01
17	1.028000e-05	1.200000e+01	4.800000e-01
18	1.128000e-05	1.200000e+01	4.800000e-01
19	1.228000e-05	1.200000e+01	4.800000e-01
20	1.328000e-05	1.200000e+01	4.800000e-01
21	1.428000e-05	1.200000e+01	4.800000e-01
22	1.528000e-05	1.200000e+01	4.800000e-01
23	1.628000e-05	1.200000e+01	4.800000e-01
... (84 more rows) ...

Common mistakes and how to avoid them

• Using a shunt with too much resistance: If the shunt value is too high (e.g., 100 Ω), it creates a massive «burden voltage,» starving the actual load of power and altering the circuit’s behavior. Always use low values (typically 1 Ω, 0.1 Ω, or even milliohms).
• Ignoring the power rating of the shunt: A resistor dropping even a fraction of a volt can dissipate substantial heat if the current is high. Always calculate P = I^2 × R and select a resistor with double the calculated wattage rating.
• Measuring current directly across the shunt: Setting the multimeter to «Amps» mode and putting it in parallel with the shunt will short out the shunt, potentially blowing the multimeter’s internal fuse. Always use the «Voltage» mode to measure the voltage drop across the shunt.

Troubleshooting

• Symptom: Multimeter reads 0 V across the shunt.
  • Cause: The circuit is open; power isn’t reaching the load, or R_SHUNT is shorted out.
  • Fix: Check all wire continuity, ensure the power supply is turned on, and confirm the load is properly connected.
• Symptom: The shunt resistor is smoking or gets dangerously hot.
  • Cause: The current exceeds the wattage rating of the shunt, or R_LOAD has been bypassed (creating a short circuit directly through the shunt).
  • Fix: Immediately turn off the power. Verify R_LOAD is not bypassed and replace the shunt with one of a higher wattage rating if necessary.
• Symptom: The calculated current seems far lower than the expected load consumption.
  • Cause: The resistance of the connecting wires or breadboard contacts is acting as an unmeasured secondary shunt, adding to the total circuit resistance.
  • Fix: Ensure short, thick wires are used for power connections. Consider switching to a 4-wire (Kelvin) measurement setup for extreme precision.

Possible improvements and extensions

• Add a current-sense amplifier: Connect an Operational Amplifier (Op-Amp) across R_SHUNT in a non-inverting configuration to amplify the small millivolt signal into a robust 0-5 V signal easily readable by a microcontroller’s ADC.
• Implement high-side sensing: Move R_SHUNT to the «high side» (between VCC and R_LOAD). Use a dedicated high-side current sensing IC (such as the INA219) to measure the differential voltage, proving that current can be measured before it reaches the load while keeping the load strictly grounded.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium — Build a stable shadow detector with visual indication and low false triggering.

Objective and use case

You will build a photoresistor-based circuit that detects a sudden drop in light caused by a shadow and turns on an LED in a stable way. The design uses an LDR voltage divider, an RC filter, and a comparator with hysteresis to reduce false activations.

Why it is useful:

• Detect when a hand or object passes in front of a lighted opening.
• Create a simple visual warning for access points, boxes, or cabinets.
• Monitor brief shadow events in classroom experiments on light sensing.
• Add a reliable light-change trigger to small automation prototypes.

Expected outcome:

• Sensor voltage at VA changes with light level, typically from about 0.8 V to 4.2 V depending on illumination.
• Filtered voltage at VB changes more slowly than VA, reducing short spikes and flicker.
• Comparator output at VOUT switches cleanly between low and high states.
• LED D1 turns on when light drops below the adjusted threshold and remains stable near the switching point.
• Hysteresis of about 0.2 V to 0.5 V avoids repeated on/off oscillation.

Target audience and level: Students with basic knowledge of resistors, capacitors, and voltage measurement.

Materials

• V1: 5 V DC supply
• R1: LDR photoresistor, function: light-dependent upper arm of sensor divider
• R2: 10 kΩ potentiometer, function: adjustable lower arm of sensor divider and threshold tuning aid
• R3: 22 kΩ resistor, function: series resistor from sensor node to RC filter
• C1: 10 µF capacitor, function: low-pass filter for shadow event stabilization
• U1: LM393 comparator, function: compare filtered sensor voltage against adjustable reference
• R4: 10 kΩ potentiometer, function: reference voltage adjustment for comparator
• R5: 220 kΩ resistor, function: positive feedback to add hysteresis
• R6: 10 kΩ resistor, function: pull-up for LM393 open-collector output
• D1: red LED, function: visual alert output
• R7: 330 Ω resistor, function: LED current limiting

Wiring guide

• V1 connects between nodes VCC and 0.
• R1 connects between nodes VCC and VA.
• R2 connects between nodes VA and 0; use the potentiometer as a variable resistor to adjust the divider sensitivity.
• R3 connects between nodes VA and VB.
• C1 connects between nodes VB and 0.
• R4 connects between nodes VCC and 0; connect the wiper of R4 to node VREF.
• U1 LM393 power pins connect as follows: supply pin to VCC, ground pin to 0.
• U1 comparator non-inverting input connects to node VREF.
• U1 comparator inverting input connects to node VB.
• R5 connects between nodes VOUT and VREF.
• R6 connects between nodes VCC and VOUT.
• R7 connects between nodes VCC and VLED.
• D1 connects between nodes VLED and VOUT; orient the LED so it turns on when VOUT is pulled low by U1.

Conceptual block diagram

Schematic

Practical case: Shadow detector for visual alert

Light / Shadow
      --> [ R1: LDR ]
      --> (VA: sensor divider node)
      --> [ R3: 22 kΩ ]
      --> (VB: filtered sensor signal)
      --> [ U1: LM393 Comparator (-) ]

VCC --> [ R2: 10 kΩ Pot, sensitivity adjust ] --> GND
                  \
                   --> (VA)

VCC --> [ R4: 10 kΩ Pot, reference adjust ] --> GND
                  \
                   --> (VREF)
                   --> [ U1: LM393 Comparator (+) ]

[ U1: LM393 Comparator Output VOUT ]
      --> [ R5: 220 kΩ Positive Feedback ] --> (VREF)
      --> [ D1: Red LED ] --> [ R7: 330 Ω ] --> VCC
      --> [ Alert Output: LED ON when VOUT goes LOW ]

VCC --> [ R6: 10 kΩ Pull-up ] --> (VOUT)

(VB) --> [ C1: 10 µF Low-Pass Filter ] --> GND

V1: 5 V DC --> VCC
V1: 0 V    --> GND
U1 power: VCC, GND

Electrical diagram

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Measurements and tests

1. Power-off inspection
2. Check that VCC and 0 are not shorted.
3. Confirm LED polarity.

4. Verify that the LM393 output has a pull-up resistor R6.

5. Supply check

6. Power the circuit with V1 = 5 V.

7. Measure between VCC and 0; expected value: 4.9 V to 5.1 V.

8. Sensor voltage measurement

9. Measure VA in bright light and then under a shadow.
10. Expected result: VA should change clearly, often by more than 1 V.

11. If the change is too small, adjust R2 or change the light angle on the LDR.

12. Filtered response measurement

13. Measure VB while suddenly covering the LDR.
14. VB should not jump instantly; it should move with a short delay set by R3 × C1.

15. With R3 = 22 kΩ and C1 = 10 µF, the time constant is about 0.22 s.

16. Threshold adjustment

17. Adjust R4 until D1 is off in normal light and turns on when a clear shadow is applied.

18. Measure VREF; typical useful range is 1 V to 4 V.

19. Hysteresis verification

20. Slowly move a hand to create a partial shadow and then slowly remove it.
21. Measure the switching voltage at VB when the LED turns on and when it turns off.

22. The two values should differ slightly because of R5; a difference of 0.2 V to 0.5 V is a good target.

23. Response time test

24. Repeatedly create a sudden shadow and observe LED behavior.
25. The LED should react within a fraction of a second, without flickering from very brief light variations.
26. If the response is too slow, reduce C1 to 4.7 µF.

27. If false triggering remains, increase C1 to 22 µF or increase R5 slightly for more hysteresis.

28. False activation test

29. Illuminate the LDR with room light and introduce small disturbances such as hand motion nearby but not fully covering it.
30. The LED should remain stable unless the light drop is large enough to cross the threshold.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Shadow detector for visual alert
.width out=256

.param R2VAL=5k
.param R4POS=0.5
.param R4TOP={10000*(1-R4POS)+1m}
.param R4BOT={10000*(R4POS)+1m}
.param RLIGHT=2k
.param RDARK=50k

V1 VCC 0 DC 5

* Dynamic light/shadow stimulus: 0 = light, 1 = shadow
VLUX LUX 0 PULSE(0 1 50m 1m 1m 200m 400m)

* R1 LDR photoresistor: upper arm of divider
R1 VCC VA r='{RLIGHT + (RDARK-RLIGHT)*V(LUX)}'

* R2 10k potentiometer used as variable resistor
R2 VA 0 {R2VAL}
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Shadow detector for visual alert
.width out=256

.param R2VAL=5k
.param R4POS=0.5
.param R4TOP={10000*(1-R4POS)+1m}
.param R4BOT={10000*(R4POS)+1m}
.param RLIGHT=2k
.param RDARK=50k

V1 VCC 0 DC 5

* Dynamic light/shadow stimulus: 0 = light, 1 = shadow
VLUX LUX 0 PULSE(0 1 50m 1m 1m 200m 400m)

* R1 LDR photoresistor: upper arm of divider
R1 VCC VA r='{RLIGHT + (RDARK-RLIGHT)*V(LUX)}'

* R2 10k potentiometer used as variable resistor
R2 VA 0 {R2VAL}

R3 VA VB 22k
C1 VB 0 10u

* R4 10k potentiometer with wiper at VREF
R4A VCC VREF {R4TOP}
R4B VREF 0 {R4BOT}

* U1 LM393 approximation
* Non-inverting input: VREF
* Inverting input: VB
* Open-collector output: VOUT
B_U1DRV NBASE 0 V='0.95*(1+tanh(80*(V(VREF)-V(VB))))/2'
R_U1B NBASE 0 100k
Q_U1 VOUT NBASE 0 QLM393OC

R5 VOUT VREF 220k
R6 VCC VOUT 10k

R7 VCC VLED 330
D1 VLED VOUT DRED

* Probe aliases so .print can include V(IN) and V(OUT) first
V_INMON IN VB DC 0
V_OUTMON OUT VOUT DC 0

.model QLM393OC NPN(IS=1e-14 BF=100 VAF=100 CJE=5p CJC=3p TF=1n TR=10n)
.model DRED D(IS=1e-18 N=2.0 RS=10 CJO=5p VJ=0.75 M=0.33 TT=50n BV=5 IBV=10u)

.print tran V(IN) V(OUT) V(VB) V(VOUT) V(VREF) V(VA) V(VLED) V(LUX)
.op
.tran 100u 500m
.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation is consistent with a shadow detector. In bright condition, VA and VB are high, VB is above VREF, the LM393 output transistor is off, and VOUT stays high at about 4.89 V so the LED is off. After the light-to-shadow transition, VA drops, VB falls slowly because of the R3-C1 filter, and when VB crosses below VREF at about 0.168 s, VOUT is pulled low to about 18 mV and the LED turns on. When light returns, VB rises slowly again, so the alert remains on for a while before resetting, consistent with RC filtering and hysteresis.
* bom/wiring vs SPICE issues (modelo):
*   - The LM393 is not a specific manufacturer macro-model; it is only an approximation of open-collector comparator behavior. This is acceptable for logic/function teaching, but not for accurate device-level output saturation or input common-mode behavior.
* bom_vs_spice equivalences ignored:
*   - R2 is described in the wiring guide as a 10 kΩ potentiometer used as a variable resistor, but the netlist fixes it with .param R2VAL=5k. This is acceptable for one simulation run, but the adjustable setting is not exposed unless the parameter is changed manually.
*   - The 10 kΩ potentiometer R4 is validly modeled as two resistors R4A and R4B with the wiper at node VREF.
*   - The LDR R1 is validly modeled as a resistor whose value changes with a control stimulus (behavioral resistance driven by VLUX).
*   - The LED D1 is validly modeled as a diode, with R7 providing the series current limit.
*   - The LM393 comparator is validly modeled with behavioral circuitry plus an NPN open-collector output stage.
*   - The changing light/shadow condition is validly modeled by the PULSE source VLUX.
* overall_comment: This SPICE netlist is broadly faithful to the BOM and wiring and is usable as a didactic example of a shadow-triggered visual alarm. The divider, RC filter, adjustable reference, hysteresis, open-collector pull-up, and active-low LED wiring all match the intended circuit. The main caveat is pedagogical: the LM393 is only behaviorally approximated, and R2 is represented by a fixed chosen value rather than an interactively adjustable potentiometer position. Before classroom use, I would explain the active-low output, the delayed switching caused by R3-C1, and the role of positive feedback R5 in shifting VREF slightly between output states.
* --------------------------------------

Simulation Results (Transient Analysis)

Analysis: The simulation is consistent with a shadow detector. In bright condition, VA and VB are high, VB is above VREF, the LM393 output transistor is off, and VOUT stays high at about 4.89 V so the LED is off. After the light-to-shadow transition, VA drops, VB falls slowly because of the R3-C1 filter, and when VB crosses below VREF at about 0.168 s, VOUT is pulled low to about 18 mV and the LED turns on. When light returns, VB rises slowly again, so the alert remains on for a while before resetting, consistent with RC filtering and hysteresis.

Show raw data table (5027 rows)

Index   time            v(in)           v(out)          v(vb)           v(vout)         v(vref)         v(va)           v(vled)         v(lux)
0	0.000000e+00	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
1	1.000000e-06	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
2	2.000000e-06	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
3	4.000000e-06	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
4	8.000000e-06	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
5	1.600000e-05	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
6	3.200000e-05	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
7	6.400000e-05	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
8	1.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
9	2.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
10	3.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
11	4.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
12	5.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
13	6.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
14	7.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
15	8.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
16	9.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
17	1.028000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
18	1.128000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
19	1.228000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
20	1.328000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
21	1.428000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
22	1.528000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
23	1.628000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
... (5003 more rows) ...

Common mistakes and how to avoid them

1. Connecting the LED directly to the comparator output without a resistor

2. Always use R7 in series with D1 to limit current.

3. Forgetting that the LM393 output is open collector

4. Add R6 from VCC to VOUT, or the output will not produce a valid high level.

5. Using no hysteresis near the threshold

6. Keep R5 installed so the LED does not chatter when the light level is close to the switching point.

Troubleshooting

• Symptom: LED never turns on
• Cause: VREF is set too low or the LDR divider range is too small.

• Fix: Adjust R4, then verify that VA and VB really change under a shadow.

• Symptom: LED is always on

• Cause: VREF is too high, or the LDR is wired incorrectly.

• Fix: Lower VREF with R4 and confirm R1 is between VCC and VA.

• Symptom: LED flickers near the switching point

• Cause: insufficient filtering or hysteresis.

• Fix: Increase C1 or reduce R5 moderately to strengthen hysteresis.

• Symptom: Output voltage at VOUT never rises

• Cause: missing or incorrect pull-up resistor R6.

• Fix: Confirm R6 is connected between VCC and VOUT.

• Symptom: Response is too slow

• Cause: RC filter too large.
• Fix: Reduce C1 or R3 to shorten the response time.

Possible improvements and extensions

1. Add a buzzer output

2. Connect a transistor driver to VOUT so the same shadow event activates both an LED and a buzzer for stronger alerting.

3. Use a dual-threshold window

4. Add a second comparator to detect both excessive darkness and excessive brightness, useful for light-condition monitoring rather than only shadow detection.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium — Calculate and verify a base resistor to switch an NPN transistor safely from a logic output.

Objective and use case

You will build a simple transistor switch where a 5 V logic output drives an NPN transistor through a base resistor. The goal is to choose the resistor so the transistor turns the load on reliably without exceeding the allowed logic output current.

Why it is useful:
– To drive a relay module, buzzer, or small lamp from a microcontroller pin.
– To control loads that require more current than a logic output can supply directly.
– To protect a logic output from excessive base current.
– To learn how to verify transistor saturation with real voltage and current measurements.

Expected outcome:
– When the logic output is LOW, the transistor remains OFF and the load is de-energized.
– When the logic output is HIGH, the transistor turns ON and the load current is about 20 mA.
– Base current stays below the logic output limit, target about 4.3 mA.
– Measured base-emitter voltage is about 0.7 V when ON.
– Measured collector-emitter voltage is low in saturation, typically below 0.2 V.

Target audience and level: Students with basic DC circuit and transistor knowledge.

Materials

• V1: 5 V DC supply
• VSIG: 0 V / 5 V logic source, function: control signal for transistor base
• R1: 1 kΩ resistor, function: base current limiting
• R2: 150 Ω resistor, function: load current limiting for LED branch
• D1: red LED, function: visible collector load indicator
• Q1: 2N2222 NPN transistor, function: low-side switch
• M1: digital multimeter, function: voltage and current measurements
• M2: optional second multimeter, function: simultaneous current check

Wiring guide

Use these node names: VCC, 0, VIN, VB, VC.

• V1 connects between VCC and 0.
• VSIG connects between VIN and 0.
• R1 connects between VIN and VB.
• Q1 collector connects to VC.
• Q1 base connects to VB.
• Q1 emitter connects to 0.
• R2 connects between VCC and the anode node of D1.
• D1 anode connects to R2; D1 cathode connects to VC.

Practical design values:
– Load current target: about Ic = (5 V - 2.0 V - 0.2 V) / 150 Ω ≈ 18.7 mA
– Forced gain for saturation: use β_forced ≈ 10
– Required base current: Ib ≈ Ic / 10 ≈ 1.9 mA
– Base resistor estimate: R1 ≈ (5 V - 0.7 V) / 1.9 mA ≈ 2.26 kΩ

To make switching more robust, choose a lower standard value:
– Selected R1 = 1 kΩ
– Expected base current: Ib ≈ (5 V - 0.7 V) / 1 kΩ ≈ 4.3 mA

This value is suitable only if the logic output can safely source at least 4.3 mA.

Conceptual block diagram

Schematic

Practical case: Base Biasing with Resistor

Power / load path:
[ V1: 5 V DC Supply ] --(VCC)--> [ R2: 150 ohm ] --(LED current limit)--> [ D1: Red LED ] --(cathode at VC)--> [ Q1:C 2N2222 ]
[ Q1:C 2N2222 ] --(collector-emitter path)--> [ Q1:E 2N2222 ] --(0 / GND)--> [ V1: 0 V ]

Control / base path:
[ VSIG: 0/5 V Logic Source ] --(VIN)--> [ R1: 1 kohm ] --(VB)--> [ Q1:B 2N2222 ]
[ Q1:B 2N2222 ] --(base-emitter junction)--> [ Q1:E 2N2222 ] --(0 / GND)--> [ VSIG: 0 V ]

Node labels:
[ VIN ] --> [ R1 ] --> [ VB ] --> [ Q1:B ]
[ VCC ] --> [ R2 ] --> [ D1 Anode ]
[ D1 Cathode ] --> [ VC ] --> [ Q1:C ]
[ Q1:E ] --> [ 0 / GND ]

Optional measurements:
[ M1 DMM ] --(measure V_B or V_C vs 0)--> [ VB / VC ] --> [ 0 / GND ]
[ M2 DMM ] --(current mode, inserted in series where needed)--> [ Base path or Load path ]

Electrical diagram

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

1. Power-off check
2. Verify all connections before applying power.
3. Confirm Q1 emitter goes to 0.

4. Confirm R1 is in series between VIN and VB.

5. OFF-state test

6. Set VSIG = 0 V.
7. Measure Vb from VB to 0: expected near 0 V.
8. Measure Vce from VC to 0: expected near 5 V.
9. Observe D1: it should be OFF.
10. Measure Ib: expected approximately 0 mA.

11. Measure Ic: expected approximately 0 mA.

12. ON-state test

13. Set VSIG = 5 V.
14. Measure Vb: expected about 0.7 V.
15. Measure Vbe: expected about 0.65 V to 0.8 V.
16. Measure Ib by placing the meter in series with R1: expected about 4.3 mA.
17. Measure Vc: expected low, typically below 0.2 V to 0.3 V.
18. Measure Vce: expected below 0.2 V if saturation is achieved.
19. Measure Ic in series with the collector path: expected about 18 mA to 20 mA.

20. Observe D1: it should be clearly ON.

21. Logic output safety check

22. Compare the measured Ib with the maximum source current allowed by the logic output.

23. If the logic output rating is less than the measured base current, increase R1.

24. Verification calculation

25. Compute measured gain in switching mode: Ic / Ib.
26. Example with measured values: 19 mA / 4.3 mA ≈ 4.4

27. This is consistent with saturated switching, where the transistor is intentionally overdriven.

28. Pass criteria

29. Ib does not exceed the logic output limit.
30. D1 turns fully ON at logic HIGH and fully OFF at logic LOW.
31. Vce in ON state is low enough to confirm saturation.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Base Biasing with Resistor
.width out=256

V1 VCC 0 DC 5
VSIG VIN 0 PULSE(0 5 10m 1u 1u 245m 1s)

R1 VIN VB 1k
R2 VCC VLED 150
D1 VLED VC DRED
Q1 VC VB 0 Q2N2222

* Optional multimeter loading approximations (high impedance voltmeters)
RM1 VC 0 10Meg
RM2 VB 0 10Meg

* Alias nodes for guaranteed logging
VALIASIN IN VIN 0
VALIASOUT OUT VC 0

.model DRED D(IS=1e-18 N=2.0 RS=10 CJO=20p VJ=0.75 M=0.5 TT=50n BV=5 IBV=10u)
* ... (truncated in public view) ...

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* Practical case: Base Biasing with Resistor
.width out=256

V1 VCC 0 DC 5
VSIG VIN 0 PULSE(0 5 10m 1u 1u 245m 1s)

R1 VIN VB 1k
R2 VCC VLED 150
D1 VLED VC DRED
Q1 VC VB 0 Q2N2222

* Optional multimeter loading approximations (high impedance voltmeters)
RM1 VC 0 10Meg
RM2 VB 0 10Meg

* Alias nodes for guaranteed logging
VALIASIN IN VIN 0
VALIASOUT OUT VC 0

.model DRED D(IS=1e-18 N=2.0 RS=10 CJO=20p VJ=0.75 M=0.5 TT=50n BV=5 IBV=10u)
.model Q2N2222 NPN(IS=1e-14 BF=200 VAF=100 IKF=0.1 ISE=1e-13 NE=1.5 BR=5 NR=1.0 VAR=25 IKR=0.05
+ RC=0.5 RE=0.2 RB=10 CJE=25p VJE=0.75 MJE=0.33 TF=0.4n XTF=2 CJC=8p VJC=0.55 MJC=0.33 TR=50n)

.save V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.op
.print op V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.tran 0.1m 250m
.print tran V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.end

Simulation Results (Transient Analysis)

Show raw data table (2528 rows)

Index   time            v(in)           v(out)          v(vin)          v(vc)           v(vb)           v(vled)         v1#branch       vsig#branch
0	0.000000e+00	0.000000e+00	3.623103e+00	0.000000e+00	3.623103e+00	3.624741e-09	4.999946e+00	-3.62318e-07	3.624741e-12
1	1.000000e-06	0.000000e+00	3.623104e+00	0.000000e+00	3.623104e+00	6.699379e-09	4.999946e+00	-3.62321e-07	6.699379e-12
2	2.000000e-06	0.000000e+00	3.623105e+00	0.000000e+00	3.623105e+00	6.506970e-09	4.999946e+00	-3.62321e-07	6.506970e-12
3	4.000000e-06	0.000000e+00	3.623106e+00	0.000000e+00	3.623106e+00	5.984372e-09	4.999946e+00	-3.62320e-07	5.984372e-12
4	8.000000e-06	0.000000e+00	3.623108e+00	0.000000e+00	3.623108e+00	5.188535e-09	4.999946e+00	-3.62320e-07	5.188535e-12
5	1.600000e-05	0.000000e+00	3.623110e+00	0.000000e+00	3.623110e+00	4.293865e-09	4.999946e+00	-3.62319e-07	4.293865e-12
6	3.200000e-05	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.693772e-09	4.999946e+00	-3.62318e-07	3.693772e-12
7	6.400000e-05	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.610539e-09	4.999946e+00	-3.62318e-07	3.610539e-12
8	1.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.631021e-09	4.999946e+00	-3.62318e-07	3.631021e-12
9	2.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.621414e-09	4.999946e+00	-3.62318e-07	3.621414e-12
10	3.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.626121e-09	4.999946e+00	-3.62318e-07	3.626121e-12
11	4.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.624676e-09	4.999946e+00	-3.62318e-07	3.624676e-12
12	5.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.623957e-09	4.999946e+00	-3.62318e-07	3.623957e-12
13	6.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.626113e-09	4.999946e+00	-3.62318e-07	3.626113e-12
14	7.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.623011e-09	4.999946e+00	-3.62318e-07	3.623011e-12
15	8.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.626745e-09	4.999946e+00	-3.62318e-07	3.626745e-12
16	9.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.622584e-09	4.999946e+00	-3.62318e-07	3.622584e-12
17	1.028000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.627045e-09	4.999946e+00	-3.62318e-07	3.627045e-12
18	1.128000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.622367e-09	4.999946e+00	-3.62318e-07	3.622367e-12
19	1.228000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.627168e-09	4.999946e+00	-3.62318e-07	3.627168e-12
20	1.328000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.622305e-09	4.999946e+00	-3.62318e-07	3.622305e-12
21	1.428000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.627229e-09	4.999946e+00	-3.62318e-07	3.627229e-12
22	1.528000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.622257e-09	4.999946e+00	-3.62318e-07	3.622257e-12
23	1.628000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.627228e-09	4.999946e+00	-3.62318e-07	3.627228e-12
... (2504 more rows) ...

Common mistakes and how to avoid them

1. Using no base resistor
2. Error: connecting the logic output directly to the transistor base.
3. Result: excessive base current and possible damage to the logic output.

4. Fix: always place R1 between VIN and VB.

5. Choosing a base resistor that is too large

6. Error: using R1 = 10 kΩ without checking current.
7. Result: base current may be too low, so the transistor may not saturate.

8. Fix: calculate Ib from the load current and use a forced gain of about 10 for switching.

9. Reversing transistor terminals

10. Error: swapping collector and emitter.
11. Result: abnormal voltages, weak load current, or no switching.
12. Fix: confirm the 2N2222 pinout from its datasheet before wiring.

Troubleshooting

• Symptom: LED never turns ON
• Cause: VSIG is not reaching 5 V, or Q1 base is not connected through R1.

• Fix: measure VIN and VB; verify R1 continuity and transistor pinout.

• Symptom: LED is dim

• Cause: transistor is not saturated because R1 is too large.

• Fix: reduce R1 after checking the logic output current limit.

• Symptom: Logic output voltage drops when ON

• Cause: base current demand is too high for the logic source.

• Fix: increase R1 or use a transistor driver stage.

• Symptom: LED stays ON all the time

• Cause: wrong wiring at the collector node or unintended base bias.

• Fix: check that Q1 emitter is at 0 and that VIN actually goes to 0 V in the LOW state.

• Symptom: Measured Vce is high when ON

• Cause: insufficient base current or incorrect collector load wiring.
• Fix: verify Ib, recalculate R1, and check R2 and D1 orientation.

Possible improvements and extensions

• Add a 10 kΩ pull-down resistor from VB to 0 so the transistor stays OFF if the logic source becomes disconnected or high-impedance.
• Replace the LED load with a relay coil and add a flyback diode across the coil to study transistor switching with inductive loads.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic – Control a high-power load using a low-voltage signal via galvanic isolation.

Objective and use case

You will build a driver circuit that uses a small 5 V signal to activate an electromechanical relay, which in turn switches a separate 12 V high-power circuit powering a bulb.

• Why it is useful:

  • Automotive Systems: Allows a low-current ECU signal to switch high-current headlights.
  • Safety: Keeps high voltage/current (the load side) physically separated from the sensitive control logic (the user side).
  • Interface: Enables microcontrollers (like Arduino/ESP32) to control industrial equipment or AC appliances (simulated here with 12 V).

• Expected outcome:

  • The 12 V bulb turns ON only when the 5 V control switch is closed.
  • An audible «click» is heard from the relay component when switching states.
  • Measurements: 0 V on the load when the control signal is 0 V; ~12 V on the load when the control signal is 5 V.

• Target audience: Students dealing with electromechanical interfaces and circuit protection.

Materials

• V1: 5 V DC voltage source, function: Control Logic Supply
• V2: 12 V DC voltage source, function: High Power Load Supply
• S1: SPST Toggle Switch, function: Control trigger
• R1: 1 kΩ resistor, function: Base current limiter for Q1
• Q1: 2N2222 NPN BJT Transistor, function: Relay coil driver
• D1: 1N4007 Diode, function: Flyback protection (snubber)
• K1: 5 V SPST Relay (coil resistance ~70 Ω), function: Galvanic isolation switch
• L1: 12 V / 10 W Incandescent Bulb, function: High power load

Wiring guide

This guide uses specific node names to ensure correct connections in simulation and assembly. The circuit has two isolated sides: the Control Side (Nodes: V_CTRL, 0) and the Load Side (Nodes: V_HV, GND_LOAD).

Control Side (Low Power):
* V1 (+): Connects to Node V_CTRL.
* V1 (-): Connects to Node 0 (Common Ground).
* S1: Connects between V_CTRL and Node V_TRIG.
* R1: Connects between V_TRIG and Node V_BASE.
* Q1 (Base): Connects to Node V_BASE.
* Q1 (Emitter): Connects to Node 0.
* Q1 (Collector): Connects to Node COIL_LOW.
* K1 (Coil pin 1): Connects to Node V_CTRL.
* K1 (Coil pin 2): Connects to Node COIL_LOW.
* D1 (Anode): Connects to Node COIL_LOW.
* D1 (Cathode): Connects to Node V_CTRL (Reverse biased across coil).

Load Side (High Power):
* V2 (+): Connects to Node V_HV.
* V2 (-): Connects to Node GND_LOAD (Isolated from Node 0).
* K1 (Common Contact): Connects to Node V_HV.
* K1 (Normally Open Contact): Connects to Node BULB_IN.
* L1: Connects between Node BULB_IN and Node GND_LOAD.

Conceptual block diagram

Schematic

+-------------------------------------------------------------------------+
|               PRACTICAL CASE: HIGH POWER CIRCUIT ISOLATION              |
+-------------------------------------------------------------------------+

===========================================================================
  PART 1: CONTROL SIDE (5 V Logic)
  Nodes: V_CTRL, V_TRIG, V_BASE, COIL_LOW, 0 (GND)
===========================================================================

  (Trigger Signal Path)
  [ V1: 5 V (+) ] --> [ S1: Switch ] --> [ R1: 1k Ohm ] --> [ Q1: Base ]
                                                               |
                                                               | (Controls)
                                                               v
  (Coil Power Path)                                    [ Q1: Collector ]
  [ V1: 5 V (+) ] ---------> [ K1: Relay Coil ] --------------> |
                            [ || D1 Diode    ]                 |
                            [ (Rev Biased)   ]                 | (Conducts to)
                                                               |
                                                               v
                                                       [ Q1: Emitter ]
                                                               |
                                                               v
                                                       [ Node 0 (GND) ]


             ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
             ~      MAGNETIC LINK (GALVANIC ISOLATION)   ~
             ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~


===========================================================================
  PART 2: LOAD SIDE (12 V High Power)
  Nodes: V_HV, BULB_IN, GND_LOAD
===========================================================================

  (High Current Path)

  [ V2: 12 V (+) ] --> [ K1: Relay Switch ] --> [ L1: 12 V Bulb ] --> [ GND_LOAD ]
                      [   (COM -> NO)    ]

Measurements and tests

Follow these steps to validate the isolation and switching capability:

1. Coil Voltage Test:

   • Close switch S1.
   • Measure voltage between V_CTRL and COIL_LOW.
   • Result: It should read approximately 5 V (indicating the transistor is sinking current).

2. Load Activation:

   • Keep S1 closed.
   • Observe L1 (Bulb).
   • Result: The bulb illuminates. Measure voltage across L1; it should be ~12 V.

3. Switch Latency (Oscilloscope required):

   • Connect Channel 1 to V_TRIG and Channel 2 to BULB_IN.
   • Toggle S1 from OFF to ON.
   • Result: You will observe a delay (typically 5–15 ms) between the signal rising on Ch1 and power appearing on Ch2. This is the mechanical switching time of the relay armature.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* High power circuit isolation
*
* This netlist simulates a relay driver circuit with a high-power load.
* It includes a low-voltage control side (5V) and an isolated high-voltage load side (12V).
*

* --- Analysis Setup ---
.tran 10u 10m
.print tran V(V_TRIG) V(BULB_IN) V(COIL_LOW) I(L_K1_COIL)

* --- Control Side (Low Power) ---

* Supply V1: 5V DC
V1 V_CTRL 0 DC 5

* Switch S1: Modeled as a Pulse Voltage Source to simulate user actuation
* Connects to V_TRIG to drive the base resistor.
* Timing: Off for 1ms, On for 4ms, then Off.
V_S1 V_TRIG 0 PULSE(0 5 1m 10u 10u 4m 10m)

* ... (truncated in public view) ...

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* High power circuit isolation
*
* This netlist simulates a relay driver circuit with a high-power load.
* It includes a low-voltage control side (5V) and an isolated high-voltage load side (12V).
*

* --- Analysis Setup ---
.tran 10u 10m
.print tran V(V_TRIG) V(BULB_IN) V(COIL_LOW) I(L_K1_COIL)

* --- Control Side (Low Power) ---

* Supply V1: 5V DC
V1 V_CTRL 0 DC 5

* Switch S1: Modeled as a Pulse Voltage Source to simulate user actuation
* Connects to V_TRIG to drive the base resistor.
* Timing: Off for 1ms, On for 4ms, then Off.
V_S1 V_TRIG 0 PULSE(0 5 1m 10u 10u 4m 10m)

* Resistor R1: 1k Base Current Limiter
R1 V_TRIG V_BASE 1k

* Transistor Q1: 2N2222 NPN Relay Driver
* Connections: Collector=COIL_LOW, Base=V_BASE, Emitter=0
Q1 COIL_LOW V_BASE 0 2N2222MOD

* Relay Coil K1 (Coil Side)
* Modeled as Inductance + Resistance in series between V_CTRL and COIL_LOW
R_K1_COIL V_CTRL INT_COIL 70
L_K1_COIL INT_COIL COIL_LOW 50m

* Diode D1: Flyback protection (Snubber)
* Anode=COIL_LOW, Cathode=V_CTRL
D1 COIL_LOW V_CTRL 1N4007MOD

* --- Load Side (High Power) ---

* Ground Isolation: High resistance path to global ground 0 to prevent singular matrix
R_ISO GND_LOAD 0 100Meg

* Supply V2: 12V DC
V2 V_HV GND_LOAD DC 12

* Relay Contact K1 (Switch Side)
* Modeled as a Voltage Controlled Switch
* Controlled by the voltage across the coil: V(V_CTRL) - V(COIL_LOW)
* Connects V_HV to BULB_IN when coil is energized
S_K1 V_HV BULB_IN V_CTRL COIL_LOW RELAY_SW_MOD

* Load L1: 12V / 10W Bulb
* Resistance ~ 14.4 Ohms (R = V^2 / P = 144 / 10)
R_L1 BULB_IN GND_LOAD 14.4

* --- Component Models ---

* NPN Transistor Model
.model 2N2222MOD NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=0.3 RE=0.2)

* Diode Model
.model 1N4007MOD D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3 BV=1000 IBV=5u CJO=10p VJ=0.7 M=0.5 FC=0.5 TT=100n)

* Relay Switch Model
* Threshold Vt=2.5V (Coil is 5V), Hysteresis Vh=0.5V
.model RELAY_SW_MOD SW(Vt=2.5 Vh=0.5 Ron=0.1 Roff=100Meg)

.op
.end

Simulation Results (Transient Analysis)

Analysis: The simulation shows the trigger signal (V_TRIG) going high (5V) between 1ms and 5ms. During this window, the coil current (I(L_K1_COIL)) rises, causing the relay switch to close and V(BULB_IN) to switch to ~12V. After 5ms, the trigger drops, coil current decays (snubber active), and the load voltage returns to near zero.

Show raw data table (4100 rows)

Index   time            v(v_trig)       v(bulb_in)      v(coil_low)     l_k1_coil#branc
0	0.000000e+00	0.000000e+00	1.722670e-06	5.000000e+00	1.002664e-11
1	1.000000e-07	0.000000e+00	1.722670e-06	5.000000e+00	1.002626e-11
2	2.000000e-07	0.000000e+00	1.722670e-06	5.000000e+00	1.002547e-11
3	4.000000e-07	0.000000e+00	1.722670e-06	5.000000e+00	1.002342e-11
4	8.000000e-07	0.000000e+00	1.722670e-06	5.000000e+00	1.001814e-11
5	1.600000e-06	0.000000e+00	1.722670e-06	5.000000e+00	1.000316e-11
6	3.200000e-06	0.000000e+00	1.722670e-06	5.000000e+00	9.969744e-12
7	6.400000e-06	0.000000e+00	1.722670e-06	5.000000e+00	1.000801e-11
8	1.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	1.002921e-11
9	2.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	9.970357e-12
10	3.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	1.004993e-11
11	4.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	9.955463e-12
12	5.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	1.004077e-11
13	6.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	9.984500e-12
14	7.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	1.001134e-11
15	8.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	1.001578e-11
16	9.280000e-05	0.000000e+00	1.722670e-06	5.000000e+00	1.000519e-11
17	1.028000e-04	0.000000e+00	1.722670e-06	5.000000e+00	1.003686e-11
18	1.128000e-04	0.000000e+00	1.722670e-06	5.000000e+00	9.961732e-12
19	1.228000e-04	0.000000e+00	1.722670e-06	5.000000e+00	1.005266e-11
20	1.328000e-04	0.000000e+00	1.722670e-06	5.000000e+00	9.963169e-12
21	1.428000e-04	0.000000e+00	1.722670e-06	5.000000e+00	1.003205e-11
22	1.528000e-04	0.000000e+00	1.722670e-06	5.000000e+00	9.984436e-12
23	1.628000e-04	0.000000e+00	1.722670e-06	5.000000e+00	1.001919e-11
... (4076 more rows) ...

Common mistakes and how to avoid them

1. Omitting the flyback diode (D1):

   • Error: The transistor Q1 fails permanently after a few switches.
   • Solution: Always place a diode in reverse bias parallel to the relay coil to absorb the high-voltage spike generated when the magnetic field collapses.

2. Sharing Grounds unintentionally:

   • Error: Connecting GND_LOAD to Node 0 on the breadboard.
   • Solution: While the circuit will work, you lose galvanic isolation. Keep the high-power return path physically separate from the logic ground.

3. Insufficient Base Current:

   • Error: Using a resistor R1 that is too high (e.g., 100 kΩ). The relay does not click or clicks weakly.
   • Solution: Ensure the transistor is in saturation. For a 2N2222 driving a standard relay, 1 kΩ is usually sufficient.

Troubleshooting

• Symptom: Relay clicks, but the bulb does not light up.

  • Cause: Issue on the Load Side (Secondary circuit).
  • Fix: Check V2 supply, verify the bulb L1 is not burnt, and ensure connections to the Relay COM/NO pins are tight.

• Symptom: No sound from relay, Bulb OFF.

  • Cause: The coil is not energizing.
  • Fix: Check voltage at Node V_BASE. If 0 V, check S1. If ~0.7 V, check if Q1 is installed correctly (E-B-C pinout).

• Symptom: Transistor gets extremely hot.

  • Cause: Coil current is too high for the selected transistor.
  • Fix: Verify the relay coil resistance. If it draws >600 mA, the 2N2222 might be underpowered; use a power transistor (e.g., TIP31) or a MOSFET.

Possible improvements and extensions

1. Status Indicator: Add a small LED and a 330 Ω resistor in parallel with the Relay Coil to visually indicate when the control signal is active.
2. Solid State Upgrade: Replace the mechanical relay (K1) and transistor driver with an Optocoupler and a MOSFET (or Triac for AC) to eliminate mechanical wear and reduce switching latency.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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