/* spi_master.v */
module spi_master (
    input wire clk,          // System clock
    input wire rst,          // Active high reset
    input wire start,        // Pulse high to start transmission
    input wire [7:0] data_in,// Data to transmit
    output reg mosi,         // Master Out Slave In
    output reg sck,          // Serial Clock
    output reg latch,        // Register Latch (RCLK)
    output reg busy          // High while transmitting
);

    reg [3:0] bit_cnt;
    reg [7:0] shift_reg;
    reg [2:0] state;

    localparam IDLE  = 3'd0;
    localparam LOAD  = 3'd1;
    localparam LOW   = 3'd2;
    localparam HIGH  = 3'd3;
    localparam LATCH = 3'd4;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            mosi <= 1'b0;
            sck <= 1'b0;
            latch <= 1'b0;
            busy <= 1'b0;
            bit_cnt <= 4'd0;
            shift_reg <= 8'd0;
            state <= IDLE;
        end else begin
            case (state)
                IDLE: begin
                    latch <= 1'b0;
                    sck <= 1'b0;
                    if (start) begin
                        shift_reg <= data_in;
                        busy <= 1'b1;
                        bit_cnt <= 4'd8;
                        state <= LOAD;
                    end else begin
                        busy <= 1'b0;
                    end
                end

                LOAD: begin
                    mosi <= shift_reg[7];
                    shift_reg <= {shift_reg[6:0], 1'b0};
                    sck <= 1'b0;
                    state <= HIGH;
                end

                HIGH: begin
                    sck <= 1'b1;
                    bit_cnt <= bit_cnt - 4'd1;
                    state <= LOW;
                end

                LOW: begin
                    sck <= 1'b0;
                    if (bit_cnt == 4'd0) begin
                        state <= LATCH;
                    end else begin
                        state <= LOAD;
                    end
                end

                LATCH: begin
                    latch <= 1'b1;
                    state <= IDLE;
                end

                default: state <= IDLE;
            endcase
        end
    end
endmodule

/* tester_top.v */
module tester_top #(
    parameter TIMER_BITS = 24 // Can be reduced for simulation speed
)(
    input wire clk_25mhz,
    input wire [2:1] btn,
    output wire spi_mosi,
    output wire spi_sck,
    output wire spi_latch
);

    wire rst = btn[1];
    wire mode_btn = btn[2];

    // Clock dividers
    reg [TIMER_BITS-1:0] timer;
    reg [3:0] spi_clk_div;
    wire spi_clk = spi_clk_div[3];

    always @(posedge clk_25mhz) begin
        timer <= timer + 1;
        spi_clk_div <= spi_clk_div + 4'd1;
    end

    wire update_tick = (timer == 0);

    // Button Debouncer
    reg [15:0] debounce_shift;
    reg mode_btn_clean;
    reg mode_btn_last;
    wire mode_pulse;

    always @(posedge clk_25mhz) begin
        debounce_shift <= {debounce_shift[14:0], mode_btn};
        if (debounce_shift == 16'hFFFF) mode_btn_clean <= 1'b1;
        else if (debounce_shift == 16'h0000) mode_btn_clean <= 1'b0;

        mode_btn_last <= mode_btn_clean;
    end

    assign mode_pulse = mode_btn_clean & ~mode_btn_last;

    // Pattern Generator State Machine
    reg [1:0] mode;
    reg [7:0] current_pattern;
    reg [2:0] walk_idx;

    always @(posedge clk_25mhz or posedge rst) begin
        if (rst) begin
            mode <= 2'd0;
            walk_idx <= 3'd0;
            current_pattern <= 8'h01;
        end else begin
            if (mode_pulse) begin
                mode <= mode + 2'd1;
                walk_idx <= 3'd0;
            end

            if (update_tick) begin
                case (mode)
                    2'd0: begin // Mode 0: Walking One
                        current_pattern <= (8'h01 << walk_idx);
                        walk_idx <= walk_idx + 3'd1;
                    end
                    2'd1: begin // Mode 1: Alternating
                        current_pattern <= (walk_idx[0]) ? 8'hAA : 8'h55;
                        walk_idx <= walk_idx + 3'd1;
                    end
                    2'd2: begin // Mode 2: All On
                        current_pattern <= 8'hFF;
                    end
                    2'd3: begin // Mode 3: All Off
                        current_pattern <= 8'h00;
                    end
                endcase
            end
        end
    end

    // SPI Master Instantiation
    wire spi_busy;
    reg spi_start;
    reg spi_start_d;

    // Generate a single-cycle start pulse in the spi_clk domain
    always @(posedge spi_clk) begin
        spi_start_d <= update_tick;
        spi_start <= update_tick & ~spi_start_d;
    end

    spi_master u_spi (
        .clk(spi_clk),
        .rst(rst),
        .start(spi_start),
        .data_in(current_pattern),
        .mosi(spi_mosi),
        .sck(spi_sck),
        .latch(spi_latch),
        .busy(spi_busy)
    );

endmodule

/* top.v */
module top #(
    parameter CLK_FREQ = 25000000,
    parameter DEBOUNCE_CYCLES = 50000
) (
    input  wire clk_25mhz,
    input  wire enc_a,
    input  wire enc_b,
    output wire [7:0] led
);

    // Synchronization registers to prevent metastability
    reg [2:0] sync_a;
    always @(posedge clk_25mhz) begin
        sync_a <= {sync_a[1:0], enc_a};
    end

    // Debounce logic for Channel A
    reg clean_a;
    reg [15:0] debounce_cnt_a;

    initial begin
        clean_a = 1'b1;
        debounce_cnt_a = 16'd0;
    end

    always @(posedge clk_25mhz) begin
        if (sync_a[2] == clean_a) begin
            debounce_cnt_a <= 16'd0;
        end else begin
            debounce_cnt_a <= debounce_cnt_a + 16'd1;
            if (debounce_cnt_a == DEBOUNCE_CYCLES) begin
                clean_a <= sync_a[2];
                debounce_cnt_a <= 16'd0;
            end
        end
    end

    // Edge detection on debounced Channel A
    reg clean_a_prev;
    initial clean_a_prev = 1'b1;

    always @(posedge clk_25mhz) begin
        clean_a_prev <= clean_a;
    end

    wire step_pulse = (clean_a == 1'b1 && clean_a_prev == 1'b0);

    // 1-Second Timer and Pulse Counter
    reg [24:0] timer;
    reg [15:0] pulse_count;
    reg [15:0] saved_pulses;

    initial begin
        timer = 25'd0;
        pulse_count = 16'd0;
        saved_pulses = 16'd0;
    end

    always @(posedge clk_25mhz) begin
        if (timer == CLK_FREQ - 1) begin
            timer <= 25'd0;
            saved_pulses <= pulse_count;
            pulse_count <= 16'd0;
        end else begin
            timer <= timer + 25'd1;
            if (step_pulse) begin
                pulse_count <= pulse_count + 16'd1;
            end
        end
    end

    // Calculate RPM: (Pulses per second * 60) / 20 pulses per revolution = Pulses * 3
    wire [15:0] rpm = saved_pulses * 16'd3;

    // LED Bar Graph Display (Thermometer Code)
    reg [7:0] led_reg;
    always @(*) begin
        led_reg = 8'b00000000;
        if (rpm >= 16'd15)  led_reg[0] = 1'b1;
        if (rpm >= 16'd30)  led_reg[1] = 1'b1;
        if (rpm >= 16'd45)  led_reg[2] = 1'b1;
        if (rpm >= 16'd60)  led_reg[3] = 1'b1;
        if (rpm >= 16'd75)  led_reg[4] = 1'b1;
        if (rpm >= 16'd90)  led_reg[5] = 1'b1;
        if (rpm >= 16'd105) led_reg[6] = 1'b1;
        if (rpm >= 16'd120) led_reg[7] = 1'b1;
    end

    assign led = led_reg;

endmodule

/*
 * Module: reaction_trainer
 * Description: A hardware reaction time measurement tool for the Radiona ULX3S.
 */
module reaction_trainer #(
    parameter MS_TICKS = 25000,      // 25MHz clock: 25,000 ticks = 1ms
    parameter DEBOUNCE_TICKS = 250000 // 10ms debounce
)(
    input  wire clk_25mhz,
    input  wire btn_start,
    input  wire btn_react,
    output reg  [7:0] led
);

    // --- State Machine Definitions ---
    localparam S_IDLE   = 3'd0;
    localparam S_WAIT   = 3'd1;
    localparam S_TEST   = 3'd2;
    localparam S_RESULT = 3'd3;
    localparam S_FAULT  = 3'd4;

    reg [2:0] state = S_IDLE;

    // --- Button Debouncing ---
    reg [17:0] debounce_counter_start = 0;
    reg [17:0] debounce_counter_react = 0;
    reg start_clean = 0;
    reg react_clean = 0;
    reg start_sync_1 = 0, start_sync_2 = 0;
    reg react_sync_1 = 0, react_sync_2 = 0;

    always @(posedge clk_25mhz) begin
        // Double-flop synchronizers
        start_sync_1 <= btn_start; start_sync_2 <= start_sync_1;
        react_sync_1 <= btn_react; react_sync_2 <= react_sync_1;

        // Debounce btn_start
        if (start_sync_2 == start_clean) begin
            debounce_counter_start <= 0;
        end else begin
            debounce_counter_start <= debounce_counter_start + 1;
            if (debounce_counter_start >= DEBOUNCE_TICKS) begin
                start_clean <= start_sync_2;
                debounce_counter_start <= 0;
            end
        end

        // Debounce btn_react
        if (react_sync_2 == react_clean) begin
            debounce_counter_react <= 0;
        end else begin
            debounce_counter_react <= debounce_counter_react + 1;
            if (debounce_counter_react >= DEBOUNCE_TICKS) begin
                react_clean <= react_sync_2;
                debounce_counter_react <= 0;
            end
        end
    end

    // Edge detection for debounced buttons
    reg start_clean_last = 0;
    reg react_clean_last = 0;
    wire start_pressed = (start_clean && !start_clean_last);
    wire react_pressed = (react_clean && !react_clean_last);

    always @(posedge clk_25mhz) begin
        start_clean_last <= start_clean;
        react_clean_last <= react_clean;
    end

    // --- Timers and LFSR ---
    reg [15:0] ms_counter = 0;
    reg [15:0] timer_ms = 0;
    reg [15:0] random_wait_ms = 0;

    // 16-bit LFSR for pseudo-randomness
    reg [15:0] lfsr = 16'hACE1;

    always @(posedge clk_25mhz) begin
        // Continuously run LFSR to ensure entropy based on human timing
        lfsr <= {lfsr[14:0], lfsr[15] ^ lfsr[13] ^ lfsr[12] ^ lfsr[10]};
    end

    // --- Main FSM ---
    reg [24:0] blink_counter = 0; // For visual effects in IDLE/FAULT

    always @(posedge clk_25mhz) begin
        blink_counter <= blink_counter + 1;

        // Millisecond tick generator
        if (ms_counter >= MS_TICKS - 1) begin
            ms_counter <= 0;
            if (state == S_WAIT || state == S_TEST) begin
                timer_ms <= timer_ms + 1;
            end
        end else begin
            ms_counter <= ms_counter + 1;
        end

        case (state)
            S_IDLE: begin
                // Alternating outer LEDs to show IDLE
                led <= blink_counter[23] ? 8'b10000001 : 8'b01000010;
                if (start_pressed) begin
                    // Calculate wait time: 1000 ms + random (0 to 2047 ms)
                    random_wait_ms <= 1000 + (lfsr & 16'h07FF);
                    timer_ms <= 0;
                    ms_counter <= 0;
                    state <= S_WAIT;
                end
            end

            S_WAIT: begin
                led <= 8'b00000000; // All LEDs off during wait
                if (react_pressed) begin
                    // False start!
                    state <= S_FAULT;
                end else if (timer_ms >= random_wait_ms) begin
                    timer_ms <= 0;
                    state <= S_TEST;
                end
            end

            S_TEST: begin
                led <= 8'b11111111; // GO signal!
                if (react_pressed) begin
                    state <= S_RESULT;
                end else if (timer_ms > 5000) begin
                    // Timeout after 5 seconds
                    state <= S_IDLE;
                end
            end

            S_RESULT: begin
                // Display bar graph based on reaction time (timer_ms)
                // <150ms: 1 LED, 150-199: 2 LEDs, 200-249: 3 LEDs... >450ms: 8 LEDs
                if (timer_ms < 150)       led <= 8'b00000001;
                else if (timer_ms < 200)  led <= 8'b00000011;
                else if (timer_ms < 250)  led <= 8'b00000111;
                else if (timer_ms < 300)  led <= 8'b00001111;
                else if (timer_ms < 350)  led <= 8'b00011111;
                else if (timer_ms < 400)  led <= 8'b00111111;
                else if (timer_ms < 450)  led <= 8'b01111111;
                else                      led <= 8'b11111111;

                if (start_pressed) begin
                    state <= S_IDLE;
                end
            end

            S_FAULT: begin
                // Fast blink all LEDs to indicate false start
                led <= blink_counter[22] ? 8'b11111111 : 8'b00000000;
                if (start_pressed) begin
                    state <= S_IDLE;
                end
            end

            default: state <= S_IDLE;
        endcase
    end

endmodule

`timescale 1ns/1ps

module reaction_trainer_tb;

    reg clk;
    reg btn_start;
    reg btn_react;
    wire [7:0] led;

    // Instantiate the Device Under Test (DUT)
    // Override parameters to speed up simulation drastically
    reaction_trainer #(
        .MS_TICKS(2),      // 2 ticks = 1 "ms" for simulation
        .DEBOUNCE_TICKS(5) // 5 ticks for debounce
    ) dut (
        .clk_25mhz(clk),
        .btn_start(btn_start),
        .btn_react(btn_react),
        .led(led)
    );

    // Generate simulated clock
    initial begin
        clk = 0;
        forever #20 clk = ~clk; // 40ns period -> 25MHz
    end

    initial begin
        $dumpfile("reaction_trainer.vcd");
        $dumpvars(0, reaction_trainer_tb);

        // Initialize inputs
        btn_start = 0;
        btn_react = 0;

        // Wait a few cycles in IDLE
        #1000;

        // Press START button
        $display("[%0t] Pressing START button...", $time);
        btn_start = 1;
        #500;
        btn_start = 0;

        // Wait for LED to turn on (TEST state)
        $display("[%0t] Waiting for GO signal...", $time);
        wait(led == 8'b11111111);
        $display("[%0t] LED is ON! Reacting...", $time);

        // Simulate a fast reaction time (e.g., 180ms)
        // In this TB, 1ms = 2 ticks = 80ns. So 180ms = 14400ns.
        #14400;
        btn_react = 1;
        #500;
        btn_react = 0;

        // Wait for RESULT state to settle
        #5000;
        $display("[%0t] Simulation complete. LED output: %b", $time, led);
        $finish;
    end

endmodule

/*
 * Module: watchdog
 * Description: Missing-pulse watchdog alarm. Triggers an LED and a 2 kHz 
 * piezo buzzer tone if a rising edge is not detected within the timeout period.
 */
module watchdog #(
    // Defaults for 25 MHz clock
    parameter TIMEOUT_CYCLES = 25000000, // 1 second timeout
    parameter TONE_CYCLES    = 12500     // 2 kHz tone period (25M / 2k)
)(
    input  wire clk_25mhz,
    input  wire pulse_in,
    output wire buzzer_out,
    output wire led_out
);

    // --------------------------------------------------------
    // 1. Metastability Synchronizer
    // --------------------------------------------------------
    // The input pulse comes from the outside world and is asynchronous.
    // We use a 2-stage shift register to synchronize it to the 25MHz clock.
    reg [1:0] sync_reg = 2'b00;

    always @(posedge clk_25mhz) begin
        sync_reg <= {sync_reg[0], pulse_in};
    end

    // --------------------------------------------------------
    // 2. Edge Detector
    // --------------------------------------------------------
    // Compare the current synchronized state with the previous state
    // to generate a single-cycle pulse on the rising edge.
    reg pulse_prev = 1'b0;
    wire pulse_edge;

    always @(posedge clk_25mhz) begin
        pulse_prev <= sync_reg[1];
    end

    assign pulse_edge = (sync_reg[1] && !pulse_prev);

    // --------------------------------------------------------
    // 3. Watchdog Timer
    // --------------------------------------------------------
    reg [24:0] timer_cnt = 25'd0;
    reg alarm_state = 1'b0;

    always @(posedge clk_25mhz) begin
        if (pulse_edge) begin
            // Valid pulse received: reset timer and clear alarm
            timer_cnt <= 25'd0;
            alarm_state <= 1'b0;
        end else if (timer_cnt < TIMEOUT_CYCLES) begin
            // No pulse, but timeout not yet reached: increment timer
            timer_cnt <= timer_cnt + 1'b1;
        end else begin
            // Timeout reached: trigger alarm
            alarm_state <= 1'b1;
        end
    end

    // --------------------------------------------------------
    // 4. Tone Generator (2 kHz Square Wave)
    // --------------------------------------------------------
    reg [13:0] tone_cnt = 14'd0;
    reg tone_out = 1'b0;

    always @(posedge clk_25mhz) begin
        if (alarm_state) begin
            // Toggle the buzzer state every half-period
            if (tone_cnt >= (TONE_CYCLES / 2) - 1) begin
                tone_cnt <= 14'd0;
                tone_out <= ~tone_out;
            end else begin
                tone_cnt <= tone_cnt + 1'b1;
            end
        end else begin
            // Ensure buzzer is silent when alarm is inactive
            tone_cnt <= 14'd0;
            tone_out <= 1'b0;
        end
    end

    // --------------------------------------------------------
    // 5. Output Assignments
    // --------------------------------------------------------
    assign buzzer_out = tone_out;
    assign led_out    = alarm_state;

endmodule

/*
 * Module: watchdog_tb
 * Description: Simulation testbench for the missing-pulse watchdog.
 */
`timescale 1ns/1ps

module watchdog_tb;

    reg clk;
    reg pulse_in;
    wire buzzer_out;
    wire led_out;

    // Instantiate the Device Under Test (DUT)
    // Override parameters for faster simulation:
    // Timeout = 100 cycles, Tone period = 10 cycles
    watchdog #(
        .TIMEOUT_CYCLES(100),
        .TONE_CYCLES(10)
    ) dut (
        .clk_25mhz(clk),
        .pulse_in(pulse_in),
        .buzzer_out(buzzer_out),
        .led_out(led_out)
    );

    // Clock generation (25 MHz = 40ns period)
    initial clk = 0;
    always #20 clk = ~clk;

    initial begin
        $dumpfile("watchdog_tb.vcd");
        $dumpvars(0, watchdog_tb);

        // Initialize inputs
        pulse_in = 0;

        // Wait for reset/initialization
        #100;

        // Apply a pulse
        pulse_in = 1;
        #40;
        pulse_in = 0;

        // Wait for timeout (100 cycles * 40ns = 4000ns)
        #5000;

        if (led_out !== 1'b1) begin
            $display("FAIL: Alarm did not trigger after timeout.");
        end else begin
            $display("PASS: Alarm triggered successfully.");
        end

        // Apply another pulse to reset alarm
        pulse_in = 1;
        #40;
        pulse_in = 0;

        #100;
        if (led_out !== 1'b0) begin
            $display("FAIL: Alarm did not clear after new pulse.");
        end else begin
            $display("PASS: Alarm cleared successfully.");
        end

        #1000;
        $finish;
    end

endmodule