Level: Medium — Build a decimal counter that advances from 0 to 9 and resets automatically using a TTL-compatible AND gate.

Objective and use case

You will build a decimal counter based on a 74LS93 ripple counter and a 74HCT08 AND gate. The circuit counts from 0000 to 1001 and automatically resets when 1010 appears.

This is useful for:
– Simple event counters with a decimal display interface
– Clock divider stages for timing experiments
– Learning how asynchronous reset works in ripple counters
– Testing TTL-to-CMOS/HCT logic compatibility in mixed logic designs

Expected outcome:
– QA, QB, QC, and QD show a binary count sequence from 0 to 9
– RESET_NODE goes HIGH only when QB = 1 and QD = 1
– The counter clears immediately when state 1010 is reached
– LEDs on the four outputs visibly repeat the decimal cycle
– Logic supply remains at +5 V, with TTL-compatible levels between the 74LS93 and 74HCT08

Target audience and level: Students and technicians with basic digital electronics experience.

Materials

• U1: 74LS93 4-bit ripple counter, function: binary count generation
• U2: 74HCT08 quad 2-input AND gate, function: TTL-compatible reset detection
• V1: 5 V DC supply, function: power for the logic circuit
• X1: clock source 0-5 V square wave, function: CLK_IN signal
• D1: red LED, function: QA indicator
• D2: red LED, function: QB indicator
• D3: red LED, function: QC indicator
• D4: red LED, function: QD indicator
• R1: 330 Ω resistor, function: current limiting for D1
• R2: 330 Ω resistor, function: current limiting for D2
• R3: 330 Ω resistor, function: current limiting for D3
• R4: 330 Ω resistor, function: current limiting for D4
• C1: 100 nF capacitor, function: local decoupling for U1
• C2: 100 nF capacitor, function: local decoupling for U2

Pin-out of the IC used

74LS93

74HCT08

Wiring guide

• V1 connects between VCC and 0.
• C1 connects between VCC and 0, placed close to U1.

• C2 connects between VCC and 0, placed close to U2.

• U1 pin 5 connects to VCC.

• U1 pin 10 connects to 0.
• U1 pin 14 connects to CLK_IN.
• U1 pin 1 connects to node QA.
• U1 pin 2 connects to RESET_NODE.
• U1 pin 3 connects to RESET_NODE.
• U1 pin 12 connects to node QA.
• U1 pin 9 connects to node QB.
• U1 pin 8 connects to node QC.

• U1 pin 11 connects to node QD.

• U2 pin 14 connects to VCC.

• U2 pin 7 connects to 0.
• U2 pin 1 connects to node QB.
• U2 pin 2 connects to node QD.

• U2 pin 3 connects to node RESET_NODE.

• R1 connects between QA and node LED1_A.

• D1 connects between LED1_A and 0.
• R2 connects between QB and node LED2_A.
• D2 connects between LED2_A and 0.
• R3 connects between QC and node LED3_A.
• D3 connects between LED3_A and 0.
• R4 connects between QD and node LED4_A.
• D4 connects between LED4_A and 0.

Use the 74HCT08, not the 74HC08, because the reset gate is driven by 74LS93 TTL outputs and must accept TTL-compatible HIGH levels reliably.

Conceptual block diagram

Schematic

Practical case: 0-9 counter with TTL-compatible reset (74LS93 + 74HCT08)

[ X1: CLK_IN 0-5 V square ] --> [ U1: 74LS93 4-bit Ripple Counter (CP0 pin14) ]
(Internal to U1: QA (pin12) --> CP1 (pin1) for divide-by-10 configuration)

U1 Q outputs to indicators (loads on the right):
[ U1: QA (pin12) ] --> [ R1: 330 Ω ] --> [ D1: Red LED ] --> GND
[ U1: QB (pin9)  ] --> [ R2: 330 Ω ] --> [ D2: Red LED ] --> GND
[ U1: QC (pin8)  ] --> [ R3: 330 Ω ] --> [ D3: Red LED ] --> GND
[ U1: QD (pin11) ] --> [ R4: 330 Ω ] --> [ D4: Red LED ] --> GND

Reset detection (separate branches; TTL-compatible gate):
[ Tap: U1.QB (pin9) ] -->
[ Tap: U1.QD (pin11) ] --> [ U2: 74HCT08 AND (pins 1,2→3) ] --(RESET_NODE)--> (to U1 Async Reset R0(1),R0(2) pins 2 & 3)

Power and decoupling (for completeness):
[ V1: +5 V ] --> [ U1: VCC pin5 ]          ; return GND --> (U1 GND pin10)
[ V1: +5 V ] --> [ U2: VCC pin14 ]         ; return GND --> (U2 GND pin7)
[ C1: 100 nF ] between U1 VCC and GND (place close to U1)
[ C2: 100 nF ] between U2 VCC and GND (place close to U2)

Electrical diagram

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Truth table

This table corresponds to the AND gate used for reset detection.

Measurements and tests

1. Power-off continuity check
2. Verify VCC is not shorted to 0.
3. Confirm U1 reset pins 2 and 3 are tied together at RESET_NODE.

4. Confirm U1 pin 1 is connected to QA.

5. Power-on static check

6. Apply +5 V.
7. Check that U1 and U2 both receive correct supply voltage.

8. With no clock applied, outputs may start in an unknown state; a brief manual reset to RESET_NODE = HIGH should force QA QB QC QD = 0000.

9. Clock verification

10. Measure CLK_IN with an oscilloscope.
11. Use a slow frequency such as 1 Hz to 10 Hz for visual LED observation.

12. Confirm the clock swings approximately from 0 V to 5 V.

13. Counter sequence check

14. Measure QA, QB, QC, and QD.
15. Verify the sequence:
    • 0000
    • 0001
    • 0010
    • 0011
    • 0100
    • 0101
    • 0110
    • 0111
    • 1000
    • 1001

16. The next attempted state is 1010, but it must reset immediately to 0000.

17. Reset-node validation

18. Measure RESET_NODE.
19. It should remain LOW for counts 0000 through 1001.

20. It should pulse HIGH when QB = 1 and QD = 1, which corresponds to detection of 1010.

21. LED observation

22. D1 must toggle at the highest visible rate.
23. D2 toggles at half the QA rate.
24. D3 and D4 toggle progressively slower.
25. The visible pattern must repeat every 10 clock pulses.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Decade counter 0-9 with reset (Corrected)
.width out=256
* Fixed Impedance and Timing issues for 74LS93 ripple counter
* Ngspice compliant netlist

* --- COMPONENT MODELS ---
* Generic Red LED Model
.model DLED D(IS=1e-14 N=1.7 RS=10 BV=5 IBV=10u CJO=10p)

* --- LOGIC GATE SUBCIRCUITS (Behavioral with Low Impedance Output) ---
* IMPORTANT: Output Impedance reduced to 50 ohms to drive LEDs and avoid loading effects.
* Delays (C1=10p) maintained for convergence and latch feedback.

* Inverter (Standard Delay ~500ps)
.subckt INV A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Decade counter 0-9 with reset (Corrected)
.width out=256
* Fixed Impedance and Timing issues for 74LS93 ripple counter
* Ngspice compliant netlist

* --- COMPONENT MODELS ---
* Generic Red LED Model
.model DLED D(IS=1e-14 N=1.7 RS=10 BV=5 IBV=10u CJO=10p)

* --- LOGIC GATE SUBCIRCUITS (Behavioral with Low Impedance Output) ---
* IMPORTANT: Output Impedance reduced to 50 ohms to drive LEDs and avoid loading effects.
* Delays (C1=10p) maintained for convergence and latch feedback.

* Inverter (Standard Delay ~500ps)
.subckt INV A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* Fast Inverter (Minimal Delay ~5ps) - Used for Clock Edge logic to prevent races
.subckt INV_FAST A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 0.1p
.ends

* 2-Input NAND
.subckt NAND2 A B Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) ))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* 3-Input NAND
.subckt NAND3 A B C Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) * (1/(1+exp(-20*(V(C)-2.5)))) ))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* 2-Input AND
.subckt AND2 A B Y VCC GND
B1 Y_int 0 V = V(VCC) * ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) )
R1 Y_int Y 50
C1 Y 0 10p
.ends

* --- FLIP-FLOP SUBCIRCUIT ---
* T-FlipFlop: Negative Edge Triggered with Active High Clear
* Uses INV_FAST for clock inversion to ensure Master-Slave non-overlap (Race Fix).
.subckt TFF_NEG_CLR CLK CLR Q QBAR VCC GND
* Invert Clear
XINV_CLR CLR CLR_BAR VCC GND INV

* Invert Clock FAST (Avoids race where both Master and Slave are transparent)
XINV_CLK CLK CLK_BAR VCC GND INV_FAST

* -- Master Latch (Tracks D=QBAR when CLK=1) --
XG1 QBAR CLK M_SET_BAR VCC GND NAND2
XG2 Q CLK CLR_BAR M_RST_BAR VCC GND NAND3
XL1 M_SET_BAR M_QBAR M_Q VCC GND NAND2
XL2 M_RST_BAR M_Q CLR_BAR M_QBAR VCC GND NAND3

* -- Slave Latch (Tracks Master when CLK=0 -> CLK_BAR=1) --
* Uses CLK_BAR which is delayed only slightly less than gates, ensuring clean handover.
XG3 M_Q CLK_BAR S_SET_BAR VCC GND NAND2
XG4 M_QBAR CLK_BAR S_RST_BAR VCC GND NAND2
XL3 S_SET_BAR QBAR Q VCC GND NAND2
XL4 S_RST_BAR Q CLR_BAR QBAR VCC GND NAND3
.ends

* --- IC SUBCIRCUITS ---

* U1: 74LS93 4-Bit Binary Counter
* Pinout mapping adjusted to match standard 14-pin DIP in netlist order:
* 1=IN_B, 2=R0(1), 3=R0(2), 5=VCC, 8=QC, 9=QB, 10=GND, 11=QD, 12=QA, 14=IN_A
.subckt 74LS93 IN_B R0_1 R0_2 VCC QC QB GND QD QA IN_A
* Internal Reset Logic: Reset if R0_1 AND R0_2 are High
XAND_RST R0_1 R0_2 RESET VCC GND AND2

* Section 1: 1-bit counter (Input A -> QA)
XFFA IN_A RESET QA QA_BAR VCC GND TFF_NEG_CLR

* Section 2: 3-bit ripple counter (Input B -> QB -> QC -> QD)
XFFB IN_B RESET QB QB_BAR VCC GND TFF_NEG_CLR
XFFC QB RESET QC QC_BAR VCC GND TFF_NEG_CLR
XFFD QC RESET QD QD_BAR VCC GND TFF_NEG_CLR
.ends

* U2: 74HCT08 Quad 2-Input AND Gate
* HCT input thresholds are TTL-compatible, so 74LS93 HIGH outputs
* reliably drive the reset-detect gate in a real classroom build.
* Pins: 1=1A, 2=1B, 3=1Y, 7=GND, 14=VCC
.subckt 74HCT08 1A 1B 1Y GND VCC
XG1 1A 1B 1Y VCC GND AND2
.ends

* --- MAIN CIRCUIT ---

* 1. Power Supply
V1 VCC 0 DC 5

* 2. Clock Signal (50kHz)
V2 CLK_IN 0 PULSE(0 5 1u 100n 100n 10u 20u)

* 3. U1: 74LS93 Counter
* Wiring Guide connections:
* Pin 1 (CKB) connects to QA_NODE (Cascade)
* Pin 12 (QA) connects to QA_NODE
* Pin 14 (CKA) connects to CLK_IN
* Pin 2, 3 connect to RESET_NODE
* Outputs to LEDs
XU1 QA_NODE RESET_NODE RESET_NODE VCC QC_NODE QB_NODE 0 QD_NODE QA_NODE CLK_IN 74LS93

* 4. U2: 74HCT08 Reset Logic
* Reset when Count=10 (Binary 1010 -> QD=1, QB=1)
* Inputs: QB_NODE, QD_NODE -> Output: RESET_NODE
XU2 QB_NODE QD_NODE RESET_NODE 0 VCC 74HCT08

* 5. LED Indicators (with Current Limiting Resistors)
* Bit 0 (QA)
R1 QA_NODE N_D1 330
D1 N_D1 0 DLED

* Bit 1 (QB)
R2 QB_NODE N_D2 330
D2 N_D2 0 DLED

* Bit 2 (QC)
R3 QC_NODE N_D3 330
D3 N_D3 0 DLED

* Bit 3 (QD)
R4 QD_NODE N_D4 330
D4 N_D4 0 DLED

* --- SIMULATION COMMANDS ---
.op
* Transient analysis: 500us to see counts 0-9 and reset
.tran 100n 500u

* Print essential nodes. CLK_IN first.
.print tran V(CLK_IN) V(QA_NODE) V(QB_NODE) V(QC_NODE) V(QD_NODE) V(RESET_NODE)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation successfully demonstrates a 4-bit counting sequence. The counter increments on the falling edge of the clock. The reset logic triggers correctly when the count reaches 10 (Binary 1010: QD=High, QB=High), forcing the outputs back to 0 immediately, effectively creating a 0-9 decade counter.
* bom_vs_spice equivalences ignored:
*   - Clock source V2 modeled as a PULSE voltage source.
*   - LEDs (D1-D4) modeled as generic diodes with specific parameters (DLED).
*   - U1 (74LS93) modeled as a behavioral subcircuit using flip-flops and logic gates.
*   - U2 (74HCT08) modeled as a behavioral subcircuit using AND gates.
* overall_comment: The circuit is well-designed and the SPICE netlist accurately reflects the intended decade counter logic. The behavioral models for the 74LS93 and 74HCT08 are robust, including necessary delays to prevent race conditions. The simulation logs confirm the modulo-10 reset operation works as expected. This is a solid didactic example.
* --------------------------------------

Simulation Results (Transient Analysis)

Analysis: The simulation successfully demonstrates a 4-bit counting sequence. The counter increments on the falling edge of the clock. The reset logic triggers correctly when the count reaches 10 (Binary 1010: QD=High, QB=High), forcing the outputs back to 0 immediately, effectively creating a 0-9 decade counter.

Show raw data table (6785 rows)

Index   time            v(clk_in)       v(qa_node)      v(qb_node)      v(qc_node)      v(qd_node)      v(reset_node)
0	0.000000e+00	0.000000e+00	-7.27413e-30	4.514570e+00	-7.27413e-30	-7.27411e-30	9.643749e-22
1	1.000000e-09	0.000000e+00	-6.24961e-30	4.514570e+00	-6.24960e-30	-6.24960e-30	9.643749e-22
2	2.000000e-09	0.000000e+00	-4.31599e-30	4.514570e+00	-4.31599e-30	-4.31599e-30	9.643749e-22
3	4.000000e-09	0.000000e+00	-8.63940e-32	4.514570e+00	-8.63867e-32	-8.63940e-32	9.643749e-22
4	8.000000e-09	0.000000e+00	6.051302e-30	4.514570e+00	6.051309e-30	6.051302e-30	9.643749e-22
5	1.600000e-08	0.000000e+00	8.619372e-30	4.514570e+00	8.619381e-30	8.619372e-30	9.643749e-22
6	3.200000e-08	0.000000e+00	4.420001e-30	4.514570e+00	4.420001e-30	4.419984e-30	9.643749e-22
7	6.400000e-08	0.000000e+00	-8.88725e-31	4.514570e+00	-8.88725e-31	-8.88708e-31	9.643749e-22
8	1.280000e-07	0.000000e+00	-1.16882e-30	4.514570e+00	-1.16881e-30	-1.16884e-30	9.643749e-22
9	2.280000e-07	0.000000e+00	-1.70113e-31	4.514570e+00	-1.70131e-31	-1.70113e-31	9.643749e-22
10	3.280000e-07	0.000000e+00	1.102262e-31	4.514570e+00	1.101893e-31	1.102078e-31	9.643749e-22
11	4.280000e-07	0.000000e+00	-2.09740e-32	4.514570e+00	-2.09440e-32	-2.09556e-32	9.643749e-22
12	5.280000e-07	0.000000e+00	3.730926e-32	4.514570e+00	3.729081e-32	3.729081e-32	9.643749e-22
13	6.280000e-07	0.000000e+00	-4.04764e-32	4.514570e+00	-4.04464e-32	-4.04395e-32	9.643749e-22
14	7.280000e-07	0.000000e+00	3.793658e-32	4.514570e+00	3.789968e-32	3.791813e-32	9.643749e-22
15	8.280000e-07	0.000000e+00	-3.71737e-32	4.514570e+00	-3.71437e-32	-3.71552e-32	9.643749e-22
16	9.280000e-07	0.000000e+00	3.658968e-32	4.514570e+00	3.657123e-32	3.658968e-32	9.643749e-22
17	1.000000e-06	0.000000e+00	-3.53679e-32	4.514570e+00	-3.53610e-32	-3.53496e-32	9.643749e-22
18	1.010000e-06	5.000000e-01	-2.79091e-33	4.514570e+00	-2.80820e-33	-2.79091e-33	9.643749e-22
19	1.030000e-06	1.500000e+00	1.602683e-33	4.514570e+00	1.585385e-33	1.602683e-33	9.643749e-22
20	1.048757e-06	2.437856e+00	4.312441e+00	4.514570e+00	-1.25584e-33	-1.27306e-33	9.643749e-22
21	1.062135e-06	3.106726e+00	4.691659e+00	4.514570e+00	1.096887e-33	1.103161e-33	9.643749e-22
22	1.071814e-06	3.590675e+00	4.366639e+00	4.514570e+00	-8.23695e-34	-8.33794e-34	9.643749e-22
23	1.080871e-06	4.043525e+00	4.636207e+00	4.514570e+00	6.872047e-34	7.032322e-34	9.643749e-22
... (6761 more rows) ...

Common mistakes and how to avoid them

1. Using 74HC08 instead of 74HCT08
2. Problem: the 74LS93 HIGH level may not meet standard HC input thresholds reliably.

3. Solution: use 74HCT08 for TTL-compatible input levels.

4. Forgetting the QA to CP1 connection

5. Problem: the 74LS93 will not count correctly through the intended 4-bit sequence.

6. Solution: connect U1 pin 12 (QA) directly to U1 pin 1 (CP1).

7. Reset inputs not tied together

8. Problem: the counter may not clear when 1010 occurs.
9. Solution: connect both R0(1) and R0(2) to the same RESET_NODE.

Troubleshooting

• Symptom: The count goes beyond 9.
• Cause: QB or QD is not correctly connected to the AND gate.

• Fix: verify U2 pin 1 = QB, U2 pin 2 = QD, and U2 pin 3 = RESET_NODE.

• Symptom: The circuit never counts.

• Cause: RESET_NODE is stuck HIGH.

• Fix: check for miswiring, shorts, or swapped AND gate pins.

• Symptom: LEDs behave randomly at power-up.

• Cause: ripple counters can power up in an undefined state.

• Fix: apply a short reset pulse at startup.

• Symptom: Reset is unreliable.

• Cause: wrong logic family used for the reset gate.

• Fix: replace any 74HC08 with 74HCT08.

• Symptom: Only the first stage toggles.

• Cause: missing cascade connection from QA to CP1.
• Fix: reconnect U1 pin 12 to U1 pin 1.

Possible improvements and extensions

• Add a BCD-to-7-segment decoder and display so the count is shown directly as digits 0 to 9.
• Replace the clock source with a debounced push-button for manual stepping and observation of each state.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Who we are

Level: Medium – Build an optical object counter with decimal outputs and an automatic batch reset.

Objective and use case

In this practical case, you will build a sequential optical counting circuit using a Light Dependent Resistor (LDR), a 74HC04 inverter for signal conditioning, and a CD4017BE decade counter. The circuit detects objects breaking a light beam, counts them sequentially using LED indicators, and automatically resets after a batch of 5 items.

This circuit is highly relevant in real-world scenarios:
– Packaging lines: Automatically grouping products into predetermined batch sizes (e.g., 5 items per box).
– Industrial automation: Tracking the movement of discrete parts along a conveyor belt.
– Safety interlocks: Monitoring limit switches or optical barriers to ensure an operation cycle is fully completed.

Expected outcome:
– The LDR voltage divider will swing from HIGH (illuminated) to LOW (beam blocked).
– The 74HC04 inverter will generate a clean, rising clock edge (VB) upon each detection.
– The CD4017BE counter will advance its active logic HIGH signal across outputs Q0 to Q4, lighting up LEDs in sequence.
– When the 6th object is detected (count of 5), output Q5 will trigger the reset pin, instantaneously clearing the count back to 0.

Target audience: Electronics students learning sequential logic, decimal counters, and basic sensor integration.

Materials

• V1: 5 V DC supply
• RLDR1: Light Dependent Resistor (LDR), function: optical sensing
• R1: 10 kΩ resistor, function: voltage divider pull-down for LDR
• U1: 74HC04, function: logic inverter and clock edge sharpener
• U2: CD4017BE, function: decade counter with decoded outputs
• D1: red LED, function: count 0 indicator
• D2: red LED, function: count 1 indicator
• D3: red LED, function: count 2 indicator
• D4: red LED, function: count 3 indicator
• D5: red LED, function: count 4 indicator
• R2: 330 Ω resistor, function: LED D1 current limiting
• R3: 330 Ω resistor, function: LED D2 current limiting
• R4: 330 Ω resistor, function: LED D3 current limiting
• R5: 330 Ω resistor, function: LED D4 current limiting
• R6: 330 Ω resistor, function: LED D5 current limiting
• C1: 100 nF capacitor, function: U1 decoupling
• C2: 100 nF capacitor, function: U2 decoupling

Pin-out of the IC used

74HC04 (Hex Inverter)

CD4017BE (Decade Counter / Divider)

Note: Pins 5, 6, 9, 11 and 12 are unused decoded outputs and carry-out pins; leave them floating in this case.

Wiring guide

• V1 connects between VCC and 0.
• RLDR1 connects between VCC and VA.
• R1 connects between VA and 0.
• U1 pin 14 connects to VCC.
• U1 pin 7 connects to 0.
• U1 pin 1 connects to VA.
• U1 pin 2 connects to VB.
• U2 pin 16 connects to VCC.
• U2 pin 8 connects to 0.
• U2 pin 13 connects to 0.
• U2 pin 14 connects to VB.
• U2 pin 1 connects to VC.
• U2 pin 15 connects to VC.
• U2 pin 3 connects to V_Q0.
• U2 pin 2 connects to V_Q1.
• U2 pin 4 connects to V_Q2.
• U2 pin 7 connects to V_Q3.
• U2 pin 10 connects to V_Q4.
• R2 connects between V_Q0 and V_D1.
• D1 connects between V_D1 and 0.
• R3 connects between V_Q1 and V_D2.
• D2 connects between V_D2 and 0.
• R4 connects between V_Q2 and V_D3.
• D3 connects between V_D3 and 0.
• R5 connects between V_Q3 and V_D4.
• D4 connects between V_D4 and 0.
• R6 connects between V_Q4 and V_D5.
• D5 connects between V_D5 and 0.
• C1 connects between VCC and 0.
• C2 connects between VCC and 0.

Conceptual block diagram

Schematic

[ U2: CD4017BE Decade Counter ]
                                                             |                             |
VCC --> [ RLDR1: LDR ] --(VA)--> [ U1: 74HC04 Inverter ] --(VB)--> CLK (Pin 14)            |
                           |                                 |                  Q0 (Pin 3)-|--(V_Q0)--> [ R2: 330 ] --> [ D1: Red LED ] --> GND
                           +---> [ R1: 10k ] --> GND         |                  Q1 (Pin 2)-|--(V_Q1)--> [ R3: 330 ] --> [ D2: Red LED ] --> GND
                                                             |                  Q2 (Pin 4)-|--(V_Q2)--> [ R4: 330 ] --> [ D3: Red LED ] --> GND
                                                 +--(VC)---------> RST (Pin 15) Q3 (Pin 7)-|--(V_Q3)--> [ R5: 330 ] --> [ D4: Red LED ] --> GND
                                                 |           |                  Q4 (Pin 10)|--(V_Q4)--> [ R6: 330 ] --> [ D5: Red LED ] --> GND
                                                 +---------------< Q5 (Pin 1)              |
                                                             |                             |
                                                 GND ------------> EN (Pin 13)             |
                                                             [-----------------------------]

* Power & Decoupling Notes:
  VCC --> [ C1: 100nF ] --> GND  (U1 Decoupling)
  VCC --> [ C2: 100nF ] --> GND  (U2 Decoupling)
  U1 Power: Pin 14 (VCC), Pin 7 (GND)
  U2 Power: Pin 16 (VCC), Pin 8 (GND)

Electrical diagram

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Measurements and tests

1. Sensor Calibration: Measure node VA with a multimeter. Ensure it rests at >4.0 V when the light source shines on the LDR, and drops to <1.0 V when an object blocks the beam. Adjust R1 if your LDR has different resistance characteristics.
2. Clock Edge Verification: Connect an oscilloscope to node VB. Pass an object through the beam and confirm a sharp, clean transition from 0 V to 5 V.
3. Sequential Counting Check: Monitor nodes V_Q0 through V_Q4. Verify that each output successively jumps to ~5 V upon each clock pulse, lighting up D1 through D5 one by one.
4. Auto-Reset Validation: Using an oscilloscope, monitor VC (Reset). When the 6th object passes, capture the brief microsecond high pulse on VC that clears the counter back to D1.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Conveyor belt object counter
.width out=256

* --- Digital Subcircuits ---

* Analog Behavioral D-Flip-Flop with Asynchronous Reset
.subckt DFF D CLK RST Q
B_M M_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(D)>2.5 ? 5 : 0))
R_M M_int M_state 100
C_M M_state 0 1n

B_S S_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(S_state)>2.5 ? 5 : 0))
R_S S_int S_state 100
C_S S_state 0 1n

B_Q Q_int 0 V = V(S_state)>2.5 ? 5 : 0
R_Q Q_int Q 100
C_Q Q 0 1n
.ends

* ... (truncated in public view) ...

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* Conveyor belt object counter
.width out=256

* --- Digital Subcircuits ---

* Analog Behavioral D-Flip-Flop with Asynchronous Reset
.subckt DFF D CLK RST Q
B_M M_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(D)>2.5 ? 5 : 0))
R_M M_int M_state 100
C_M M_state 0 1n

B_S S_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(S_state)>2.5 ? 5 : 0))
R_S S_int S_state 100
C_S S_state 0 1n

B_Q Q_int 0 V = V(S_state)>2.5 ? 5 : 0
R_Q Q_int Q 100
C_Q Q 0 1n
.ends

* CD4017BE Decade Counter (5-stage Johnson Counter with decoded outputs)
* Pins: 1:Q5(VC), 2:Q1, 3:Q0, 4:Q2, 7:Q3, 8:GND, 10:Q4, 13:EN, 14:CLK, 15:RST, 16:VCC
.subckt CD4017 1 2 3 4 7 8 10 13 14 15 16
B_CLK_INT CLK_INT 0 V = (V(14)>2.5) * (V(13)<2.5) * 5
R_CLK CLK_INT CLK_F 100
C_CLK CLK_F 0 1n

XF1 D1 CLK_F 15 F1 DFF
XF2 F1 CLK_F 15 F2 DFF
XF3 F2 CLK_F 15 F3 DFF
XF4 F3 CLK_F 15 F4 DFF
XF5 F4 CLK_F 15 F5 DFF

B_D1_int D1_int 0 V = V(F5)>2.5 ? 0 : 5
R_D1 D1_int D1 100
C_D1 D1 0 1n

B_Q0_int Q0_int 0 V = (V(F1)<2.5) * (V(F5)<2.5) * 5
R_Q0 Q0_int 3 100
C_Q0 3 0 1n

B_Q1_int Q1_int 0 V = (V(F1)>2.5) * (V(F2)<2.5) * 5
R_Q1 Q1_int 2 100
C_Q1 2 0 1n

B_Q2_int Q2_int 0 V = (V(F2)>2.5) * (V(F3)<2.5) * 5
R_Q2 Q2_int 4 100
C_Q2 4 0 1n

B_Q3_int Q3_int 0 V = (V(F3)>2.5) * (V(F4)<2.5) * 5
R_Q3 Q3_int 7 100
C_Q3 7 0 1n

B_Q4_int Q4_int 0 V = (V(F4)>2.5) * (V(F5)<2.5) * 5
R_Q4 Q4_int 10 100
C_Q4 10 0 1n

* Q5 output is used for the modulo-5 reset via VC, so it uses a slightly larger delay 
* to guarantee the reset pulse is wide enough to clear all DFFs.
B_Q5_int Q5_int 0 V = (V(F5)>2.5) * (V(F1)>2.5) * 5
R_Q5 Q5_int 1 100
C_Q5 1 0 10n

* Dummy loads to prevent warnings on power pins
R_GND 8 0 1
R_VCC 16 0 1Meg
.ends

* 74HC04 Hex Inverter (single gate modeled for pins 1, 2)
* Pins: 1:A, 2:Y, 7:GND, 14:VCC
.subckt 74HC04 1 2 7 14
B_Y_int Y_int 0 V = V(1)>2.5 ? 0 : 5
R_Y Y_int 2 100
C_Y 2 0 1n
R_GND 7 0 1
R_VCC 14 0 1Meg
.ends

* --- Main Circuit ---

* Power Supply
V1 VCC 0 DC 5

* Optical Sensing (LDR and pull-down divider)
* Conveyor beam is normally ON (light=1), LDR is 1k. 
* When object passes, light is blocked (light=0), LDR becomes 100k.
V_LIGHT N_LIGHT 0 PULSE(1 0 0.1 0.05 0.05 0.2 0.5)
R_LIGHT N_LIGHT 0 1Meg 
RLDR1 VCC VA R='V(N_LIGHT) > 0.5 ? 1k : 100k'
R1 VA 0 10k

* Edge sharpener and logic inverter
XU1 VA VB 0 VCC 74HC04

* Decade Counter
XU2 VC V_Q1 V_Q0 V_Q2 V_Q3 0 V_Q4 0 VB VC VCC CD4017

* LED Output Indicators
.model RED_LED D(IS=1e-18 N=1.8 RS=10)

R2 V_Q0 V_D1 330
D1 V_D1 0 RED_LED

R3 V_Q1 V_D2 330
D2 V_D2 0 RED_LED

R4 V_Q2 V_D3 330
D3 V_D3 0 RED_LED

R5 V_Q3 V_D4 330
D4 V_D4 0 RED_LED

R6 V_Q4 V_D5 330
D5 V_D5 0 RED_LED

* Decoupling Capacitors
C1 VCC 0 100n
C2 VCC 0 100n

* Dummy IN/OUT assignments for strict output requirements
R_IN VA IN 1
R_IN_GND IN 0 100Meg
R_OUT V_Q4 OUT 1
R_OUT_GND OUT 0 100Meg

* --- Simulation Commands ---
.op
.tran 1m 3.0
.print tran V(IN) V(OUT) V(VA) V(V_Q0) V(V_Q1) V(V_Q2) V(V_Q3) V(V_Q4)

Simulation Results (Transient Analysis)

Analysis: The simulation shows the input signal (VA) toggling between ~4.5V and ~0.45V, representing the LDR state changes. The outputs V_Q0 to V_Q4 sequentially pulse high to ~4.25V, confirming the decade counter is advancing correctly with each input pulse.

Show raw data table (3128 rows)

Index   time            v(in)           v(out)          v(va)           v(v_q0)         v(v_q1)         v(v_q2)         v(v_q3)         v(v_q4)
0	0.000000e+00	4.545413e+00	7.813983e-36	4.545413e+00	7.814080e-36	4.250409e+00	7.814080e-36	7.814080e-36	7.813983e-36
1	1.000000e-05	4.545413e+00	7.736609e-38	4.545413e+00	7.736713e-38	4.250409e+00	7.736713e-38	7.736713e-38	7.736609e-38
2	2.000000e-05	4.545413e+00	7.660001e-40	4.545413e+00	7.660112e-40	4.250409e+00	7.660112e-40	7.660112e-40	7.660001e-40
3	4.000000e-05	4.545413e+00	-7.50832e-40	4.545413e+00	-7.50843e-40	4.250409e+00	-7.50843e-40	-7.50843e-40	-7.50832e-40
4	8.000000e-05	4.545413e+00	7.433609e-40	4.545413e+00	7.433716e-40	4.250409e+00	7.433716e-40	7.433716e-40	7.433609e-40
5	1.600000e-04	4.545413e+00	-7.39653e-40	4.545413e+00	-7.39664e-40	4.250409e+00	-7.39664e-40	-7.39664e-40	-7.39653e-40
6	3.200000e-04	4.545413e+00	7.378065e-40	4.545413e+00	7.378171e-40	4.250409e+00	7.378171e-40	7.378171e-40	7.378065e-40
7	6.400000e-04	4.545413e+00	-7.36885e-40	4.545413e+00	-7.36895e-40	4.250409e+00	-7.36895e-40	-7.36895e-40	-7.36885e-40
8	1.280000e-03	4.545413e+00	7.364244e-40	4.545413e+00	7.364350e-40	4.250409e+00	7.364350e-40	7.364350e-40	7.364244e-40
9	2.280000e-03	4.545413e+00	-7.36130e-40	4.545413e+00	-7.36141e-40	4.250409e+00	-7.36141e-40	-7.36141e-40	-7.36130e-40
10	3.280000e-03	4.545413e+00	7.358355e-40	4.545413e+00	7.358461e-40	4.250409e+00	7.358461e-40	7.358461e-40	7.358355e-40
11	4.280000e-03	4.545413e+00	-7.35541e-40	4.545413e+00	-7.35552e-40	4.250409e+00	-7.35552e-40	-7.35552e-40	-7.35541e-40
12	5.280000e-03	4.545413e+00	7.352471e-40	4.545413e+00	7.352577e-40	4.250409e+00	7.352577e-40	7.352577e-40	7.352471e-40
13	6.280000e-03	4.545413e+00	-7.34953e-40	4.545413e+00	-7.34964e-40	4.250409e+00	-7.34964e-40	-7.34964e-40	-7.34953e-40
14	7.280000e-03	4.545413e+00	7.346591e-40	4.545413e+00	7.346697e-40	4.250409e+00	7.346697e-40	7.346697e-40	7.346591e-40
15	8.280000e-03	4.545413e+00	-7.34365e-40	4.545413e+00	-7.34376e-40	4.250409e+00	-7.34376e-40	-7.34376e-40	-7.34365e-40
16	9.280000e-03	4.545413e+00	7.340716e-40	4.545413e+00	7.340822e-40	4.250409e+00	7.340822e-40	7.340822e-40	7.340716e-40
17	1.028000e-02	4.545413e+00	-7.33778e-40	4.545413e+00	-7.33789e-40	4.250409e+00	-7.33789e-40	-7.33789e-40	-7.33778e-40
18	1.128000e-02	4.545413e+00	7.334846e-40	4.545413e+00	7.334952e-40	4.250409e+00	7.334952e-40	7.334952e-40	7.334846e-40
19	1.228000e-02	4.545413e+00	-7.33191e-40	4.545413e+00	-7.33202e-40	4.250409e+00	-7.33202e-40	-7.33202e-40	-7.33191e-40
20	1.328000e-02	4.545413e+00	7.328981e-40	4.545413e+00	7.329086e-40	4.250409e+00	7.329086e-40	7.329086e-40	7.328981e-40
21	1.428000e-02	4.545413e+00	-7.32605e-40	4.545413e+00	-7.32616e-40	4.250409e+00	-7.32616e-40	-7.32616e-40	-7.32605e-40
22	1.528000e-02	4.545413e+00	7.323120e-40	4.545413e+00	7.323225e-40	4.250409e+00	7.323225e-40	7.323225e-40	7.323120e-40
23	1.628000e-02	4.545413e+00	-7.32019e-40	4.545413e+00	-7.32030e-40	4.250409e+00	-7.32030e-40	-7.32030e-40	-7.32019e-40
... (3104 more rows) ...

Common mistakes and how to avoid them

1. Leaving Clock Enable floating: Pin 13 (CKE) on the CD4017BE is active low. If left unconnected, ambient electrical noise will disable the clock input irregularly. Always tie it directly to Ground (0).
2. Missing LED current limiters: Connecting LEDs directly to the CD4017BE outputs will draw too much current, potentially burning out the decoded output stages of the IC. Always use individual resistors (e.g., 330 Ω) for each LED.
3. Slow sensor transitions: The 74HC04 inverter buffers the signal, but slowly moving objects on a conveyor belt might still cause the logic threshold to linger, causing multiple rapid clock pulses (contact bounce equivalent). If objects move very slowly, replace the 74HC04 with a Schmitt trigger inverter (like the 74HC14) for severe hysteresis.

Troubleshooting

• Symptom: The counter skips numbers or counts randomly.
• Cause: Electrical noise on the LDR line or mechanical vibrations affecting the light source.
• Fix: Add a small 10 nF capacitor between VA and 0 to filter out high-frequency optical or electrical jitter.
• Symptom: Circuit stays permanently on LED D1 (Count 0) and never advances.
• Cause: The Reset pin (15) is stuck HIGH, or Clock Enable (13) is stuck HIGH.
• Fix: Verify the connection between Q5 and Reset. Ensure Pin 13 is firmly grounded.
• Symptom: LEDs are extremely dim.
• Cause: The current limiting resistors are too large, or the power supply cannot deliver enough current.
• Fix: Check that R2-R6 are exactly 330 Ω, not 330 kΩ. Confirm the VCC supply is maintaining a steady 5 V.

Possible improvements and extensions

1. Numerical Display: Replace the 10-LED output logic by substituting the CD4017BE with a CD4026BE, allowing you to directly drive a 7-segment numerical display for a true digit read-out.
2. Monostable Debouncing: Insert a 555 timer configured as a monostable multivibrator between the sensor inverter (VB) and the counter’s clock input. This guarantees a single, fixed-duration clock pulse per object, entirely eliminating false double-counts regardless of object shape or speed.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium | Construct a transistor-driven relay circuit to automatically control a water pump using a float switch.

Objective and use case

In this practical case, you will build an automatic reservoir pump controller. The circuit uses a mechanical float switch to trigger an NPN transistor, which energizes an electromechanical relay to drive a high-current DC pump (simulated here as a resistive load) and a status LED.

Why this is useful:
* Automates water level management in tanks, reservoirs, and sump basins.
* Safely isolates low-voltage control circuits from high-power loads.
* Demonstrates the practical interfacing of simple mechanical sensors with power electronics.
* Prevents overflow or dry-running conditions in industrial and agricultural settings.

Expected outcome:
* Closing the float switch applies a voltage to the transistor base, turning it on (saturation).
* The transistor sinks current for the relay coil, energizing it and closing its normally open (NO) contact.
* The simulated DC pump (load resistor) receives the full supply voltage.
* The status indicator LED illuminates when the pump is active.
* Releasing the switch de-energizes the relay, and the flyback diode safely dissipates the inductive voltage spike from the coil.

Target audience: Intermediate electronics students learning about transistor switching, electromechanical relays, and inductive load protection.

Materials

• V1: 12 V DC supply, function: main power for relay coil and pump
• V2: 5 V DC supply, function: control logic power for the float switch
• SW1: SPST switch, function: simulated float switch or high-level sensor
• R1: 1 kΩ resistor, function: transistor base current limiting
• R2: 10 kΩ resistor, function: pull-down for transistor base to ensure turn-off
• R3: 1 kΩ resistor, function: LED current limiting
• RLOAD: 50 Ω high-power resistor, function: simulated DC pump load
• Q1: 2N2222 NPN transistor, function: relay coil driver
• D1: 1N4007 diode, function: flyback protection for relay coil
• D2: Green LED, function: pump status indicator
• K1: 12 V SPDT Relay, function: electromechanical switch for the pump

Wiring guide

• V1 connects between node VCC12 and node 0.
• V2 connects between node VCC5 and node 0.
• SW1 connects between node VCC5 and node SENSE.
• R1 connects between node SENSE and node VB.
• R2 connects between node VB and node 0.
• Q1 base connects to node VB, emitter connects to node 0, and collector connects to node COIL_NEG.
• K1 coil connects between node VCC12 and node COIL_NEG.
• K1 COM (Common) contact connects to node VCC12.
• K1 NO (Normally Open) contact connects to node LOAD_SW.
• D1 cathode connects to node VCC12 and anode connects to node COIL_NEG (placed anti-parallel to the relay coil).
• RLOAD connects between node LOAD_SW and node 0.
• R3 connects between node LOAD_SW and the anode of D2.
• D2 cathode connects to node 0.

Conceptual block diagram

Schematic

VCC5 --> [ SW1 ] --(SENSE)--> [ R1 ] --(VB)--> [ Q1:B ]
                                              |          |
                                            [ R2 ]       |
                                              |          |
                                             GND         |
                                                         |
      VCC12 --> [ K1 Coil || D1(Rev) ] --(COIL_NEG)--> [ Q1:C ] --( )-- [ Q1:E ] --> GND
                       |
                (Magnetic Link)
                       v
      VCC12 --> [ K1 Switch (COM->NO) ] --(LOAD_SW)--> [ RLOAD (Pump) ] --> GND
                                              |
                                              +------> [ R3 ] --> [ D2 (LED) ] --> GND

Electrical diagram

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Measurements and tests

1. Control Logic Test: With SW1 open, measure the voltage at node SENSE. It should be 0 V. Close SW1 and verify the voltage rises to 5 V.
2. Base Drive Verification: Measure the voltage at node VB with SW1 closed. It should read approximately 0.7 V, confirming the base-emitter junction of Q1 is forward-biased.
3. Coil Switching Verification: Probe node COIL_NEG. When SW1 is open, it should measure 12 V. When SW1 is closed, it should drop to near 0 V (Vce_sat of the transistor), confirming the coil is energized.
4. Load Delivery Test: Measure the voltage at node LOAD_SW. Verify that it reads 0 V when the relay is off, and jumps to 12 V when the relay clicks on. Check that the RLOAD draws current and D2 illuminates.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Automatic Reservoir Pump Controller
.width out=256

* Power Supplies
V1 VCC12 0 DC 12
V2 VCC5 0 DC 5

* Simulated Float Switch (SW1)
* Using a voltage-controlled switch and a pulse source to simulate a user/sensor triggering the switch
V_SW_CTRL SW_CTRL 0 PULSE(0 5 50u 1u 1u 200u 500u)
S1 VCC5 SENSE SW_CTRL 0 myswitch

* Base driving circuit
R1 SENSE VB 1k
R2 VB 0 10k

* Relay Driver Transistor
Q1 COIL_NEG VB 0 2N2222MOD

* Relay Coil (K1)
* ... (truncated in public view) ...

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* Automatic Reservoir Pump Controller
.width out=256

* Power Supplies
V1 VCC12 0 DC 12
V2 VCC5 0 DC 5

* Simulated Float Switch (SW1)
* Using a voltage-controlled switch and a pulse source to simulate a user/sensor triggering the switch
V_SW_CTRL SW_CTRL 0 PULSE(0 5 50u 1u 1u 200u 500u)
S1 VCC5 SENSE SW_CTRL 0 myswitch

* Base driving circuit
R1 SENSE VB 1k
R2 VB 0 10k

* Relay Driver Transistor
Q1 COIL_NEG VB 0 2N2222MOD

* Relay Coil (K1)
* Modeled as a series resistor and inductor
R_K1 VCC12 K1_COIL_INT 400
L_K1 K1_COIL_INT COIL_NEG 10mH

* Flyback Diode
D1 COIL_NEG VCC12 1N4007MOD

* Relay Contacts (K1 NO)
* The switch closes when the voltage across the coil (VCC12 - COIL_NEG) exceeds 8V
S_RELAY VCC12 LOAD_SW VCC12 COIL_NEG relay_sw

* Simulated Pump Load
RLOAD LOAD_SW 0 50

* Status LED
R3 LOAD_SW D2_A 1k
D2 D2_A 0 DLED

* Models
.model myswitch SW(vt=2.5 vh=0.5 ron=0.1 roff=10MEG)
.model relay_sw SW(vt=8 vh=1 ron=0.05 roff=100MEG)
.model 2N2222MOD NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=100E-9 TF=400E-12 ITF=1 VTF=2 XTF=3 RB=10)
.model 1N4007MOD D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3.0 BV=1000 IBV=5e-08 CJO=1e-11 VJ=0.7 M=0.5 FC=0.5 TT=1e-07)
.model DLED D(IS=1e-20 N=2.2 RS=2.5 BV=5 IBV=10u CJO=50p)

* Analysis Commands
.op
.tran 1u 500u
.print tran V(SENSE) V(LOAD_SW) V(COIL_NEG) V(VB) I(L_K1)

.end

Simulation Results (Transient Analysis)

Analysis: The transient analysis spans 0 s to 500 us and captures the switching interval. The switching node and inductor current remain bounded, consistent with the flyback path protecting the switch. Main ranges: l_k1#branch -7.86 uA -> 29.9 mA; v(coil_neg) 9.89 mV -> 12.7 V; v(load_sw) 6 uV -> 12 V.

Show raw data table (961 rows)

Index   time            v(sense)        v(load_sw)      v(coil_neg)     v(vb)           l_k1#branch
0	0.000000e+00	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.403801e-11
1	1.000000e-08	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.403803e-11
2	2.000000e-08	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.403801e-11
3	4.000000e-08	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.403795e-11
4	8.000000e-08	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.403772e-11
5	1.600000e-07	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.403654e-11
6	3.200000e-07	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.403033e-11
7	6.400000e-07	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.400598e-11
8	1.280000e-06	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.398528e-11
9	2.280000e-06	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.403534e-11
10	3.280000e-06	5.494077e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.401174e-11
11	4.280000e-06	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.394780e-11
12	5.280000e-06	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.402136e-11
13	6.280000e-06	5.494077e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.408634e-11
14	7.280000e-06	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.401469e-11
15	8.280000e-06	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.399217e-11
16	9.280000e-06	5.494077e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.399919e-11
17	1.028000e-05	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.393646e-11
18	1.128000e-05	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.397704e-11
19	1.228000e-05	5.494077e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.408121e-11
20	1.328000e-05	5.494077e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.402567e-11
21	1.428000e-05	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.395460e-11
22	1.528000e-05	5.494076e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.400449e-11
23	1.628000e-05	5.494077e-03	5.999997e-06	1.200000e+01	4.994626e-03	2.399821e-11
... (937 more rows) ...

Common mistakes and how to avoid them

• Missing flyback diode (D1): When the relay turns off, the collapsing magnetic field in the coil generates a massive voltage spike. Without D1 to provide a safe discharge path, this spike will instantly destroy Q1. Always place D1 reverse-biased across the coil.
• Insufficient base drive current: If R1 is too large, Q1 will operate in its linear region instead of fully saturating. This will cause the transistor to overheat and the relay may fail to actuate reliably. Always ensure R1 provides enough base current (Ib) for the required collector current (Ic).
• Undersized relay contacts: Motors and pumps draw a massive «inrush» current when starting up. Using a relay rated exactly for the running current will cause the contacts to weld shut or burn. Always select a relay rated for at least 2-3 times the load’s continuous current.

Troubleshooting

• Symptom: The relay chatters or buzzes rapidly instead of latching cleanly.
• Cause: The 12 V power supply is too weak and drops voltage under the heavy load of the pump, causing the relay coil to lose holding power, disconnect the load, recover, and repeat.
• Fix: Use a bench power supply with a higher current capacity or test with a battery.
• Symptom: Transistor Q1 becomes extremely hot and fails.
• Cause: Missing flyback diode, or the relay coil’s current demand exceeds the maximum collector current of the 2N2222.
• Fix: Verify D1 is correctly installed. Check the relay coil resistance; ensure it draws less than 600 mA.
• Symptom: Circuit turns on randomly without float switch action.
• Cause: The base of Q1 is floating, picking up environmental electromagnetic interference.
• Fix: Ensure the pull-down resistor R2 is securely connected between node VB and ground.
• Symptom: The LED turns on, but the simulated pump (RLOAD) does not work.
• Cause: Broken connection at the relay NO contact or a blown load resistor.
• Fix: Check the wiring between the relay’s NO pin and LOAD_SW. Verify the resistance of RLOAD with a multimeter.

Possible improvements and extensions

• Low-Water Cutoff (Latching Logic): Add a second float switch and configure the relay as a latching circuit. This ensures the pump runs continuously until the tank is completely full, rather than short-cycling.
• Debounce Delay Network: Water ripples in a tank can cause the float switch to rapidly bounce on and off. Add an RC delay network (a capacitor and resistor) at the transistor base, or use a 555 timer, to introduce a turn-on/turn-off delay and protect the pump.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium – Disconnect a critical load using a normally closed relay contact when a voltage threshold is exceeded.

Objective and use case

In this practical case, you will build a hardware-based overvoltage protection circuit. It uses a Zener diode to set a voltage threshold and a bipolar junction transistor (BJT) to actuate an electromechanical relay, mechanically disconnecting power when the voltage spikes to dangerous levels.

This topology is highly useful in real-world scenarios:
– Safeguarding sensitive 5 V microcontrollers from accidental power supply surges.
– Protecting expensive sensors or instruments in automotive environments where alternator spikes occur.
– Ensuring battery-powered or USB-powered devices mechanically cut out during a charger regulator failure.

Expected outcome:
– When the input voltage (v-in) is in the safe range (e.g., 5.0 V), the BJT remains off, the relay is unpowered, and the normally closed (NC) contact feeds power to the load.
– When v-in exceeds the Zener threshold plus the BJT base-emitter drop (around 6.3 V), the Zener conducts.
– Base current flows, the BJT switch turns on, and the relay coil energizes.
– The relay’s NC contact opens, triggering a v-load-disconnect event that drops the load voltage to 0 V.
– Target audience and level: Intermediate electronics students exploring analog voltage thresholds and electromechanical switching.

Materials

• V1: Variable DC supply (0-9 V), function: provides system input voltage (v-in)
• D1: 5.6 V Zener diode (e.g., 1N4734 A), function: sets the overvoltage threshold reference
• R1: 1 kΩ resistor, function: base current limiting for the BJT
• R2: 10 kΩ resistor, function: base pull-down to ensure the BJT turns off cleanly
• Q1: 2N3904 NPN transistor, function: relay driver switch
• D2: 1N4148 or 1N4007 diode, function: flyback protection for the relay coil
• K1: 5 V SPDT Relay, function: disconnects the load using its normally closed (NC) contact
• R_LOAD: 100 Ω resistor, function: simulated critical load

Wiring guide

• V1: positive terminal connects to node V_IN, negative terminal connects to node 0 (GND).
• D1: cathode connects to node V_IN, anode connects to node V_ZENER.
• R1: connects between node V_ZENER and node BASE.
• R2: connects between node BASE and node 0.
• Q1: collector connects to node COLLECTOR, base connects to node BASE, emitter connects to node 0.
• K1_COIL: the relay coil connects between node V_IN and node COLLECTOR.
• D2: cathode connects to node V_IN, anode connects to node COLLECTOR (wired anti-parallel to the relay coil).
• K1_COM: the relay’s common contact connects to node V_IN.
• K1_NC: the relay’s normally closed contact connects to node LOAD_PWR.
• R_LOAD: connects between node LOAD_PWR and node 0.

Conceptual block diagram

Schematic

POWER SOURCE:
[ V1: 0-9 V DC ] --(V_IN)--> System Power
[ V1: Negative ] ---------> GND

1. OVERVOLTAGE SENSING & CONTROL PATH:
V_IN --> [ D1: 5.6 V Zener ] --(V_ZENER)--> [ R1: 1 kΩ ] --(BASE)--> [ Q1:Base ]
                                                             |
                                                        [ R2: 10 kΩ ]
                                                             |
                                                            GND

2. RELAY COIL & DRIVER PATH:
V_IN --> [ K1_COIL || D2: Flyback(Rev) ] --(COLLECTOR)--> [ Q1:Collector ]
                       |                                        |
                (Magnetic Link)                            [ Q1:Emitter ]
                       |                                        |
                       v                                       GND

3. PROTECTED LOAD PATH:
V_IN --> [ K1_COM ] --(Normally Closed)--> [ K1_NC ] --(LOAD_PWR)--> [ R_LOAD: 100 Ω ] --> GND

Electrical diagram

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Measurements and tests

1. Set the variable power supply V1 to exactly 5.0 V.
2. Measure v-in relative to ground. Verify it is 5.0 V.
3. Measure the voltage across the load (LOAD_PWR to 0). It should read 5.0 V, indicating the relay is deactivated and the NC contact is closed.
4. Slowly increase the voltage of V1. Monitor v-zener (the voltage at the anode of D1). It will remain near 0 V until v-in crosses the ~5.6 V breakdown threshold of the Zener diode.
5. Push V1 up to 6.5 V. Observe that v-zener rises, pushing current into the base of Q1.
6. Verify the v-load-disconnect event: listen for the relay click. Measure the voltage at LOAD_PWR; it should instantly drop to 0 V as the NC contact opens, successfully protecting the load.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Overvoltage protection
.width out=256

* Input Voltage Source (Sweeps from 0V to normal 5V, then overvoltage 9V, then back)
V1 V_IN 0 PWL(0 0 1m 5 4m 5 5m 9 6m 9 7m 5 9m 5 10m 0)

* Zener Diode for threshold detection
D1 V_IN V_ZENER DZENER

* Base resistors for Q1
R1 V_ZENER BASE 1k
R2 BASE 0 10k

* Relay Driver Transistor
Q1 COLLECTOR BASE 0 2N3904

* Relay Coil (Modeled as series inductor and resistor)
L_K1_COIL V_IN K1_COIL_INT 10m
R_K1_COIL K1_COIL_INT COLLECTOR 100

* ... (truncated in public view) ...

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* Practical case: Overvoltage protection
.width out=256

* Input Voltage Source (Sweeps from 0V to normal 5V, then overvoltage 9V, then back)
V1 V_IN 0 PWL(0 0 1m 5 4m 5 5m 9 6m 9 7m 5 9m 5 10m 0)

* Zener Diode for threshold detection
D1 V_IN V_ZENER DZENER

* Base resistors for Q1
R1 V_ZENER BASE 1k
R2 BASE 0 10k

* Relay Driver Transistor
Q1 COLLECTOR BASE 0 2N3904

* Relay Coil (Modeled as series inductor and resistor)
L_K1_COIL V_IN K1_COIL_INT 10m
R_K1_COIL K1_COIL_INT COLLECTOR 100

* Flyback Diode
D2 V_IN COLLECTOR D4148

* Relay Normally Closed (NC) Contact
* Modeled as a voltage-controlled switch controlled by the coil voltage (V_IN - COLLECTOR)
* When Q1 is OFF, coil voltage is 0V -> Switch is CLOSED (roff = 0.1)
* When Q1 is ON, coil voltage is > 6V -> Switch is OPEN (ron = 100meg)
S1 V_IN LOAD_PWR V_IN COLLECTOR RelayNC

* Critical Load
R_LOAD LOAD_PWR 0 100

* Models
.model DZENER D(IS=1e-15 RS=10 N=1 BV=5.6 IBV=5m)
.model D4148 D(IS=1e-14 RS=0.1 N=1)
.model 2N3904 NPN(IS=1E-14 VAF=100 BF=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1 TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3)
.model RelayNC SW(vt=3 vh=0.5 ron=100meg roff=0.1)

* Simulation Directives
.print tran V(V_IN) V(LOAD_PWR) V(BASE) V(COLLECTOR) V(V_ZENER) I(L_K1_COIL)
.tran 10u 10m
.op
.end

Simulation Results (Transient Analysis)

Analysis: The simulation sweeps the input voltage from 0V to 5V, then up to 9V (overvoltage), and back down. The ngspice results show that when V_IN reaches 9V, the Zener diode conducts, raising V(BASE) to ~1.07V, which turns on Q1. This energizes the relay coil (current reaches ~9mA), opening the NC contact and disconnecting the load (V(LOAD_PWR) drops or follows the switch logic).

Show raw data table (1788 rows)

Index   time            v(v_in)         v(load_pwr)     v(base)         v(collector)    v(v_zener)      l_k1_coil#branc
0	0.000000e+00	0.000000e+00	0.000000e+00	4.369907e-29	1.104363e-28	4.276684e-29	-1.10436e-30
1	1.000000e-07	5.000000e-04	4.995005e-04	2.124049e-05	1.169502e-04	2.124049e-05	3.826672e-09
2	1.128896e-07	5.644481e-04	5.638843e-04	2.436647e-05	1.341994e-04	2.436647e-05	4.380682e-09
3	1.386689e-07	6.933444e-04	6.926518e-04	3.144704e-05	1.734710e-04	3.144704e-05	5.604067e-09
4	1.902274e-07	9.511370e-04	9.501868e-04	5.084817e-05	2.848367e-04	5.084817e-05	8.658258e-09
5	2.933444e-07	1.466722e-03	1.465257e-03	1.084331e-04	6.633002e-04	1.084332e-04	1.622310e-08
6	4.910392e-07	2.455196e-03	2.452743e-03	2.404937e-04	1.923047e-03	2.404937e-04	2.937980e-08
7	6.875077e-07	3.437539e-03	3.434104e-03	3.216141e-04	3.548938e-03	3.216141e-04	3.345128e-08
8	9.631281e-07	4.815640e-03	4.810829e-03	2.723800e-04	5.450903e-03	2.723800e-04	2.308361e-08
9	1.154824e-06	5.774121e-03	5.768352e-03	1.710095e-04	6.210657e-03	1.710095e-04	1.277625e-08
10	1.305686e-06	6.528429e-03	6.521907e-03	1.116498e-04	6.566319e-03	1.116498e-04	9.181046e-09
11	1.495573e-06	7.477865e-03	7.470395e-03	1.085076e-04	7.080935e-03	1.085076e-04	1.256925e-08
12	1.736950e-06	8.684750e-03	8.676074e-03	1.904626e-04	8.232826e-03	1.904626e-04	2.277129e-08
13	2.001986e-06	1.000993e-02	9.999931e-03	2.728041e-04	1.002166e-02	2.728041e-04	2.853663e-08
14	2.256607e-06	1.128304e-02	1.127176e-02	2.568832e-04	1.166727e-02	2.568832e-04	2.342944e-08
15	2.500031e-06	1.250016e-02	1.248767e-02	1.808629e-04	1.277687e-02	1.808630e-04	1.533781e-08
16	2.702903e-06	1.351451e-02	1.350101e-02	1.375223e-04	1.345800e-02	1.375223e-04	1.307538e-08
17	2.944974e-06	1.472487e-02	1.471016e-02	1.562745e-04	1.440894e-02	1.562745e-04	1.754621e-08
18	3.189115e-06	1.594558e-02	1.592965e-02	2.174467e-04	1.574153e-02	2.174467e-04	2.384313e-08
19	3.483820e-06	1.741910e-02	1.740170e-02	2.492948e-04	1.756940e-02	2.492949e-04	2.456373e-08
20	3.789826e-06	1.894913e-02	1.893020e-02	2.050542e-04	1.918736e-02	2.050543e-04	1.855307e-08
21	4.028198e-06	2.014099e-02	2.012087e-02	1.627875e-04	2.016491e-02	1.627876e-04	1.538812e-08
22	4.364653e-06	2.182326e-02	2.180146e-02	1.717346e-04	2.161154e-02	1.717346e-04	1.849039e-08
23	4.749559e-06	2.374779e-02	2.372407e-02	2.249970e-04	2.370014e-02	2.249971e-04	2.340138e-08
... (1764 more rows) ...

Common mistakes and how to avoid them

• Omitting the flyback diode (D2): Failing to place a diode across the relay coil will result in a massive inductive voltage spike when the transistor turns off, permanently destroying the BJT. Always include the anti-parallel diode.
• Installing the Zener diode backward: If the Zener is installed forward-biased (anode to V_IN), it will act like a standard diode with a 0.7 V drop. The relay will trigger almost immediately. Ensure the cathode faces the positive input.
• Wiring the load to the NO contact: If you accidentally connect R_LOAD to the Normally Open (NO) terminal instead of the NC terminal, the load will only receive power during an overvoltage event, which defeats the purpose of the protection circuit.

Troubleshooting

• Symptom: The relay chatters rapidly or buzzes when the input voltage is right at the threshold (e.g., 6.2 V).
• Cause: The circuit lacks hysteresis. A slow-moving analog voltage at the exact threshold causes the BJT to partially turn on, putting the relay in an undefined mechanical state.
• Fix: In a practical setup, overvoltage events are usually fast spikes. For slow-rising voltages, a Schmitt trigger or a latching circuit is required to ensure a clean transition.
• Symptom: The load never powers on, even at 5.0 V.
• Cause: The relay might be stuck energized, the BJT is shorted, or the load was mistakenly wired to the NO contact.
• Fix: Check LOAD_PWR continuity to V_IN while the circuit is unpowered. Replace Q1 if it reads a dead short from collector to emitter.
• Symptom: The transistor gets exceptionally hot during an overvoltage event.
• Cause: The input voltage was raised far beyond the threshold (e.g., 12 V into a 5 V relay), causing excessive coil current through the BJT.
• Fix: Do not exceed the absolute maximum ratings of the relay coil and the 2N3904 transistor. If higher voltages are expected, use a beefier transistor (like a TIP120) or a pre-regulator.

Possible improvements and extensions

• Add a fault indicator: Connect a red LED with an appropriate current-limiting resistor to the Normally Open (NO) contact. When the overvoltage triggers, the load loses power, and the red LED instantly illuminates to warn the user.
• Implement a mechanical latch: Wire a secondary contact of the relay (if using a DPDT relay) or an SCR in the base circuit so that once an overvoltage event triggers the relay, it stays locked in the «disconnect» state until the user manually presses a reset button, preventing repeated power cycling.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium – Build basic logic gates by wiring the contacts of multiple relays in series and parallel.

Objective and use case

• What you will build: A circuit that utilizes two DPDT (Double Pole Double Throw) electro-mechanical relays to simultaneously demonstrate basic Boolean logic operations (AND and OR gates).
• Why it is useful:
  • Forms the historical foundation of industrial automation and ladder logic programming.
  • Demonstrates how to handle logic for high-voltage or high-current systems where standard silicon ICs are unsuitable.
  • Provides complete electrical isolation between the control inputs (coils) and the logic outputs (contacts).
  • Illustrates the fundamental fail-safe interlock principles used in heavy machinery and safety circuits.
• Expected outcome:
  • The AND output (Green LED) will only illuminate when both relay coils are energized (series contacts).
  • The OR output (Red LED) will illuminate when either relay coil is energized (parallel contacts).
  • Successful measurement of control voltages confirming the activation of specific logic paths.
• Target audience and level: Intermediate electronics students exploring automated control systems and electromechanical switching.

Materials

• V1: 5 V DC supply, function: power for coils and logic
• SW1: SPST switch, function: Input A control
• SW2: SPST switch, function: Input B control
• K1: 5 V DPDT relay, function: Logic gate element A
• K2: 5 V DPDT relay, function: Logic gate element B
• D1: Green LED, function: AND logic output indicator
• D2: Red LED, function: OR logic output indicator
• D3: 1N4148 diode, function: K1 flyback protection
• D4: 1N4148 diode, function: K2 flyback protection
• R1: 330 Ω resistor, function: D1 current limiting
• R2: 330 Ω resistor, function: D2 current limiting

Wiring guide

• V1 connects between VCC and 0.
• SW1 connects between VCC and node VA.
• SW2 connects between VCC and node VB.
• K1 coil connects between node VA and 0.
• K2 coil connects between node VB and 0.
• D3 cathode connects to node VA, anode connects to 0 (anti-parallel to K1 coil).
• D4 cathode connects to node VB, anode connects to 0 (anti-parallel to K2 coil).
• AND Logic (Series Wiring – Pole 1):
  • K1 Pole 1 Common contact connects to VCC.
  • K1 Pole 1 Normally Open (NO) contact connects to node AND_MID.
  • K2 Pole 1 Common contact connects to node AND_MID.
  • K2 Pole 1 Normally Open (NO) contact connects to node OUT_AND.
• OR Logic (Parallel Wiring – Pole 2):
  • K1 Pole 2 Common contact connects to VCC.
  • K1 Pole 2 Normally Open (NO) contact connects to node OUT_OR.
  • K2 Pole 2 Common contact connects to VCC.
  • K2 Pole 2 Normally Open (NO) contact connects to node OUT_OR.
• Outputs:
  • R1 connects between OUT_AND and node D1_ANODE.
  • D1 connects between D1_ANODE and 0 (cathode to ground).
  • R2 connects between OUT_OR and node D2_ANODE.
  • D2 connects between D2_ANODE and 0 (cathode to ground).

Conceptual block diagram

Schematic

[ CONTROL SECTION: RELAY COILS ]

VCC --> [ SW1 (Input A) ] --(VA)--> [ K1 Coil || D3(Rev) ] --> GND
                                          |
                                   (Magnetic Link)
                                          v
                                    (To K1 Poles)

VCC --> [ SW2 (Input B) ] --(VB)--> [ K2 Coil || D4(Rev) ] --> GND
                                          |
                                   (Magnetic Link)
                                          v
                                    (To K2 Poles)


[ AND LOGIC SECTION: SERIES WIRING (POLE 1) ]

VCC --> [ K1 Pole 1 (NO) ] --(AND_MID)--> [ K2 Pole 1 (NO) ] --(OUT_AND)--> [ R1 ] --(D1_ANODE)--> [ D1 (Green LED) ] --> GND


[ OR LOGIC SECTION: PARALLEL WIRING (POLE 2) ]

VCC --> [ K1 Pole 2 (NO) ] --(OUT_OR)--+
                                       |--> [ R2 ] --(D2_ANODE)--> [ D2 (Red LED) ] --> GND
VCC --> [ K2 Pole 2 (NO) ] --(OUT_OR)--+

Electrical diagram

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Truth table

Measurements and tests

1. Input Verification: Power on V1. Using a multimeter, measure the voltage at nodes VA and VB with respect to 0 (GND). Ensure it reads 0 V when the corresponding switch is open, and 5 V when closed.
2. Mechanical Operation: Toggle SW1 and SW2 individually. You should hear a distinct mechanical «click» from K1 and K2, confirming coil activation.
3. OR Gate Testing: Close SW1 only. Measure the voltage at OUT_OR (should be ~5 V) and ensure the Red LED lights up. Repeat this step for SW2 only.
4. AND Gate Testing: Ensure both SW1 and SW2 are closed. Measure the voltage at OUT_AND (should be ~5 V) and confirm the Green LED lights up. If either switch is opened, the Green LED must turn off.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: AND and OR logic using relays
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Input A Control (SW1)
* Modeled as a voltage-controlled switch toggled by a fast pulse source to simulate user input
S_SW1 VCC VA ctrl_A 0 switch_mod
V_ctrl_A ctrl_A 0 PULSE(0 5 0 1u 1u 100u 200u)

* Input B Control (SW2)
* Modeled as a voltage-controlled switch toggled by a fast pulse source
S_SW2 VCC VB ctrl_B 0 switch_mod
V_ctrl_B ctrl_B 0 PULSE(0 5 0 1u 1u 200u 400u)

* Relay K1 Coil and Flyback Diode
* Coil modeled as an RL series circuit
L_K1 VA K1_mid 1m
R_K1 K1_mid 0 100
* ... (truncated in public view) ...

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* Practical case: AND and OR logic using relays
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Input A Control (SW1)
* Modeled as a voltage-controlled switch toggled by a fast pulse source to simulate user input
S_SW1 VCC VA ctrl_A 0 switch_mod
V_ctrl_A ctrl_A 0 PULSE(0 5 0 1u 1u 100u 200u)

* Input B Control (SW2)
* Modeled as a voltage-controlled switch toggled by a fast pulse source
S_SW2 VCC VB ctrl_B 0 switch_mod
V_ctrl_B ctrl_B 0 PULSE(0 5 0 1u 1u 200u 400u)

* Relay K1 Coil and Flyback Diode
* Coil modeled as an RL series circuit
L_K1 VA K1_mid 1m
R_K1 K1_mid 0 100
D3 0 VA 1N4148

* Relay K2 Coil and Flyback Diode
L_K2 VB K2_mid 1m
R_K2 K2_mid 0 100
D4 0 VB 1N4148

* AND Logic (Series Wiring - Pole 1)
S_K1_P1 VCC AND_MID VA 0 relay_switch
S_K2_P1 AND_MID OUT_AND VB 0 relay_switch
* Anti-floating leak resistor for the midpoint of the series connection
R_leak AND_MID 0 1G 

* OR Logic (Parallel Wiring - Pole 2)
S_K1_P2 VCC OUT_OR VA 0 relay_switch
S_K2_P2 VCC OUT_OR VB 0 relay_switch

* Outputs
R1 OUT_AND D1_ANODE 330
D1 D1_ANODE 0 DLED_Green

R2 OUT_OR D2_ANODE 330
D2 D2_ANODE 0 DLED_Red

* Models
.model switch_mod SW(vt=2.5 vh=0.5 ron=0.1 roff=100MEG)
.model relay_switch SW(vt=2.5 vh=0.5 ron=0.1 roff=100MEG)
.model 1N4148 D(IS=2.682n N=1.836 RS=0.5623 BV=100 IBV=100p CJO=4p M=0.333 VJ=0.5 TT=11.54n)
.model DLED_Green D(IS=1e-20 N=2.2 RS=5)
.model DLED_Red D(IS=1e-15 N=2.0 RS=5)

* Analysis
.tran 1u 500u
.print tran V(VA) V(VB) V(OUT_AND) V(OUT_OR) V(AND_MID) I(L_K1)
.op
.end

Simulation Results (Transient Analysis)

Analysis: The simulation results match the expected truth table for AND and OR logic. When both inputs are 5V, both outputs are near 5V. When only one input is 5V, only the OR output goes to 5V. The OFF state voltages are non-zero (around 1.6V and 0.9V) due to the finite off-resistance of the switch models, but these are below the LED forward voltages.

Show raw data table (5166 rows)

Index   time            v(va)           v(vb)           v(out_and)      v(out_or)       v(and_mid)      l_k1#branch
0	0.000000e+00	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
1	1.000000e-08	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
2	2.000000e-08	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
3	4.000000e-08	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
4	8.000000e-08	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
5	1.600000e-07	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
6	3.200000e-07	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
7	3.750000e-07	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
8	4.712500e-07	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
9	4.978906e-07	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
10	5.445117e-07	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
11	5.574158e-07	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
12	5.799979e-07	4.999967e-06	4.999967e-06	1.597015e+00	9.421253e-01	3.141436e+00	4.999967e-08
13	6.019875e-07	4.999887e+00	4.999887e+00	4.998416e+00	4.999485e+00	4.999208e+00	5.496234e-05
14	6.174611e-07	5.000094e+00	5.000094e+00	4.998416e+00	4.999485e+00	4.999208e+00	1.321856e-04
15	6.317917e-07	4.999872e+00	4.999872e+00	4.998416e+00	4.999485e+00	4.999208e+00	2.035976e-04
16	6.498539e-07	5.000078e+00	5.000078e+00	4.998416e+00	4.999485e+00	4.999208e+00	2.934595e-04
17	6.859784e-07	4.999845e+00	4.999845e+00	4.998416e+00	4.999485e+00	4.999208e+00	4.726966e-04
18	7.582273e-07	5.000025e+00	5.000025e+00	4.998416e+00	4.999485e+00	4.999208e+00	8.292335e-04
19	9.027252e-07	4.999739e+00	4.999739e+00	4.998416e+00	4.999485e+00	4.999208e+00	1.534627e-03
20	1.000000e-06	4.999907e+00	4.999907e+00	4.998416e+00	4.999485e+00	4.999208e+00	2.003774e-03
21	1.028900e-06	4.999786e+00	4.999786e+00	4.998416e+00	4.999485e+00	4.999208e+00	2.142075e-03
22	1.086699e-06	4.999758e+00	4.999758e+00	4.998416e+00	4.999485e+00	4.999208e+00	2.417880e-03
23	1.202297e-06	4.999704e+00	4.999704e+00	4.998416e+00	4.999485e+00	4.999208e+00	2.964729e-03
... (5142 more rows) ...

Common mistakes and how to avoid them

• Omitting flyback diodes: Failing to include D3 and D4 can cause high voltage spikes when the switches are opened, which can damage the switches or surrounding sensitive electronics. Always wire them in reverse-bias across the coils.
• Confusing NO and NC contacts: Accidentally wiring to the Normally Closed (NC) pin instead of the Normally Open (NO) pin will invert the logic, effectively creating NAND/NOR conditions instead of AND/OR. Double-check your relay’s datasheet or pinout.
• Insufficient power supply current: Relays consume significantly more current than digital ICs (often 50–100 mA per coil). Ensure your 5 V supply can comfortably deliver at least 300 mA to prevent voltage dips when both relays are energized.

Troubleshooting

• Symptom: Neither LED lights up under any switch combination, and no «clicks» are heard.
  • Cause: Power supply V1 is disconnected, dead, or current-limited.
  • Fix: Verify VCC and 0 connections to the main supply and check the supply limits.
• Symptom: Relays click when switches are pressed, but LEDs never turn on.
  • Cause: The control side (coils) is working, but the logic side (contacts) is unpowered.
  • Fix: Verify that VCC is properly routed to the Common pins of both poles on K1 and K2.
• Symptom: Power supply resets or dips severely when a switch is pressed.
  • Cause: A flyback diode (D3 or D4) is installed backward, creating a direct short circuit to ground when the switch closes.
  • Fix: Check diode orientation; the cathode (striped side) must face the positive incoming voltage (VA or VB).
• Symptom: The AND logic acts like an OR logic.
  • Cause: The contacts for the AND gate were wired in parallel instead of series.
  • Fix: Inspect the node AND_MID. VCC should strictly flow through K1 into K2, not directly to both.

Possible improvements and extensions

• Implement a NOT Gate (Inverter): Add a third relay or utilize an unused pole. Route VCC through its Normally Closed (NC) contact so that the output turns OFF when the relay is energized.
• Build an XOR (Exclusive OR) Circuit: Using both poles of two SPDT/DPDT relays, wire the NO contact of K1 to the NC contact of K2, and the NC contact of K1 to the NO contact of K2. This implements a 2-way lighting circuit logic using relays.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Who we are

Level: Medium – Implement an SPDT relay to automatically alternate between a main power supply and a backup battery.

Objective and use case

In this practical case, you will build a power management circuit using a Single Pole Double Throw (SPDT) relay. The circuit will automatically switch a connected load to a backup battery whenever the main power supply fails.

This automated switching topology is highly useful in several real-world applications:
* Uninterruptible Power Supplies (UPS) for routers and critical network equipment.
* Alarm and security systems that require continuous operation during grid power outages.
* Medical monitoring devices that must remain functional during patient transport.
* Solar power systems that automatically switch to battery power after sunset.

Expected outcome:
* When the main supply (V_MAIN) is active, the relay coil energizes, and the load connects to the Normally Open (NO) contact powered by the main supply.
* When the main supply fails (drops to 0 V), the relay de-energizes, seamlessly transferring the load to the Normally Closed (NC) contact powered by the backup battery.
* The load voltage (V_LOAD_OUT) remains continuous, save for a minor mechanical switching delay.
* A visual LED indicator successfully reports the presence of the main power supply.

Target audience: Hobbyists and intermediate electronics students learning about electromechanical relays and power redundancy.

Materials

• V1: 12 V DC supply, function: main power source
• V2: 9 V DC supply, function: backup battery source
• K1: 12 V SPDT relay, function: automatic power switch
• D1: 1N4007 diode, function: flyback diode to protect against relay coil voltage spikes
• D2: Red LED, function: main power indicator
• R1: 1 kΩ resistor, function: LED current limiting
• R2: 100 Ω resistor, function: simulated system load

Wiring guide

• V1: Connect positive terminal to V_MAIN and negative terminal to 0 (GND).
• V2: Connect positive terminal to V_BACKUP and negative terminal to 0 (GND).
• K1 (Coil): Connect one side to V_MAIN and the other side to 0 (GND).
• D1: Connect parallel to the K1 coil. Connect the cathode to V_MAIN and the anode to 0 (GND).
• K1 (NO Contact): Connect the Normally Open terminal to V_MAIN.
• K1 (NC Contact): Connect the Normally Closed terminal to V_BACKUP.
• K1 (COM Contact): Connect the Common terminal to V_LOAD_OUT.
• R2: Connect between V_LOAD_OUT and 0 (GND).
• R1: Connect between V_MAIN and NODE_LED.
• D2: Connect the anode to NODE_LED and the cathode to 0 (GND).

Conceptual block diagram

Schematic

[ V1: 12 V Main ] --(V_MAIN)--> [ K1 Coil || D1 (Rev) ] --> GND
                                       |
                                 (Magnetic Link)
                                       v
[ V1: 12 V Main ] --(V_MAIN)--> [ K1: NO Contact ] --+
                                                    |
                                                  (COM)--> [ V_LOAD_OUT ] --> [ R2: 100 Ω Load ] --> GND
                                                    |
[ V2: 9 V Backup ] -(V_BACKUP)-> [ K1: NC Contact ] -+

[ V1: 12 V Main ] --(V_MAIN)--> [ R1: 1 kΩ ] --(NODE_LED)--> [ D2: Red LED ] --> GND

Electrical diagram

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Measurements and tests

1. Connect and activate both V1 (12 V) and V2 (9 V).
2. Measure the voltage at V_MAIN and V_BACKUP with a multimeter to verify both sources are stable.
3. Measure the voltage at V_LOAD_OUT. It should read approximately 12 V. The relay should emit an audible «click» upon power-up, and the indicator LED (D2) should be brightly lit.
4. Disconnect V1 to simulate a power outage (V_MAIN drops to 0 V).
5. Measure the voltage at V_LOAD_OUT again. It should now read approximately 9 V, confirming the load has successfully transferred to the backup battery. The LED should turn off.
6. Reconnect V1. Observe the relay clicking again as V_LOAD_OUT returns to 12 V.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Automatic power switching
.width out=256

* Power Sources
V1 V_MAIN 0 PULSE(12 0 200u 1u 1u 200u 500u)
V2 V_BACKUP 0 DC 9

* K1 Relay Coil (modeled as series inductor and resistor)
L_K1 V_MAIN K1_COIL_INT 1m
R_K1 K1_COIL_INT 0 400

* K1 Relay Contacts (modeled as voltage-controlled switches)
* Normally Open (NO) contact between V_MAIN and V_LOAD_OUT, controlled by V_MAIN
S_K1_NO V_MAIN V_LOAD_OUT V_MAIN 0 Relay_NO
* Normally Closed (NC) contact between V_BACKUP and V_LOAD_OUT, controlled by inverted V_MAIN
S_K1_NC V_BACKUP V_LOAD_OUT 0 V_MAIN Relay_NC

* D1 Flyback Diode (Anode to 0, Cathode to V_MAIN)
D1 0 V_MAIN 1N4007

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Automatic power switching
.width out=256

* Power Sources
V1 V_MAIN 0 PULSE(12 0 200u 1u 1u 200u 500u)
V2 V_BACKUP 0 DC 9

* K1 Relay Coil (modeled as series inductor and resistor)
L_K1 V_MAIN K1_COIL_INT 1m
R_K1 K1_COIL_INT 0 400

* K1 Relay Contacts (modeled as voltage-controlled switches)
* Normally Open (NO) contact between V_MAIN and V_LOAD_OUT, controlled by V_MAIN
S_K1_NO V_MAIN V_LOAD_OUT V_MAIN 0 Relay_NO
* Normally Closed (NC) contact between V_BACKUP and V_LOAD_OUT, controlled by inverted V_MAIN
S_K1_NC V_BACKUP V_LOAD_OUT 0 V_MAIN Relay_NC

* D1 Flyback Diode (Anode to 0, Cathode to V_MAIN)
D1 0 V_MAIN 1N4007

* Main Power Indicator
R1 V_MAIN NODE_LED 1k
D2 NODE_LED 0 DLED

* Simulated System Load
R2 V_LOAD_OUT 0 100

* Component Models
.model 1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1e-11 VJ=0.7 M=0.5 FC=0.5 TT=1e-07)
.model DLED D(IS=1e-15 RS=10 N=2.0)
.model Relay_NO SW(vt=6 vh=0.5 ron=0.05 roff=10Meg)
.model Relay_NC SW(vt=-6 vh=0.5 ron=0.05 roff=10Meg)

* Analysis Directives
.op
.tran 1u 500u
.print tran V(V_MAIN) V(V_LOAD_OUT) V(V_BACKUP) V(NODE_LED) I(L_K1)

.end

Simulation Results (Transient Analysis)

Analysis: The simulation shows V_MAIN starting at 12V, during which V_LOAD_OUT is approximately 12V. At t=200us, V_MAIN drops to 0V, and V_LOAD_OUT seamlessly switches to the 9V backup supply. When V_MAIN recovers at t=400us, V_LOAD_OUT returns to 12V.

Show raw data table (557 rows)

Index   time            v(v_main)       v(v_load_out)   v(v_backup)     v(node_led)     l_k1#branch
0	0.000000e+00	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
1	1.000000e-08	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
2	2.000000e-08	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
3	4.000000e-08	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
4	8.000000e-08	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
5	1.600000e-07	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
6	3.200000e-07	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
7	6.400000e-07	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
8	1.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
9	2.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
10	3.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
11	4.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
12	5.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
13	6.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
14	7.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
15	8.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
16	9.280000e-06	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
17	1.028000e-05	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
18	1.128000e-05	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
19	1.228000e-05	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
20	1.328000e-05	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
21	1.428000e-05	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
22	1.528000e-05	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
23	1.628000e-05	1.200000e+01	1.199400e+01	9.000000e+00	1.653685e+00	3.000000e-02
... (533 more rows) ...

Common mistakes and how to avoid them

• Relay coil voltage mismatch: Using a 5 V relay on a 12 V line will cause the coil to overheat and fail quickly. Always ensure the relay’s rated coil voltage matches the main supply voltage exactly.
• Omitting the flyback diode: Failing to install the reverse-biased diode across the relay coil can result in high-voltage spikes when the main power is abruptly disconnected, potentially damaging parallel components on the main power bus.
• Reversing NO and NC contacts: Wiring the backup battery to the NO contact and the main supply to the NC contact will result in a dead system when the main power fails. Verify the relay pinout before soldering or powering the circuit.

Troubleshooting

• Symptom: The load completely loses power when the main supply drops.
  • Cause: The backup battery is either dead or connected to the Normally Open (NO) terminal instead of the Normally Closed (NC) terminal.
  • Fix: Measure the battery voltage independently, then verify its connection to the NC terminal of the relay.
• Symptom: The relay chatters or buzzes continuously instead of switching cleanly.
  • Cause: The main power supply cannot provide enough current for both the relay coil and the load, causing the voltage to repeatedly dip below the relay’s hold threshold.
  • Fix: Upgrade the main power supply to a higher current rating, or add a large smoothing capacitor across the V_MAIN line.
• Symptom: The indicator LED does not light up, but the switching works.
  • Cause: The LED is inserted with reverse polarity, or the current limiting resistor is disconnected.
  • Fix: Verify that the flat side (cathode) of the LED is connected to ground.

Possible improvements and extensions

• Add a large electrolytic capacitor (e.g., 1000 µF) in parallel with the load (R2) to smooth out the brief power interruption (brownout) caused by the mechanical switching time of the relay contacts.
• Replace the mechanical relay with a solid-state diode OR-ing circuit (using Schottky diodes) for completely seamless, zero-delay switching without any moving parts.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are