Practical case: Adaptive Screen Brightness Regulator

Adaptive Screen Brightness Regulator prototype (Maker Style)

Level: Medium
Design a circuit that decreases LED backlight intensity as ambient light increases.

Objective and use case

In this practical case, you will build a PWM (Pulse Width Modulation) controller using a 555 timer and a photoresistor (LDR). The circuit will automatically adjust the duty cycle of the output signal based on ambient light levels, driving a power MOSFET to dim an LED strip.

Why it is useful:
* Energy Efficiency: Reduces power consumption in high-brightness environments where backlights might be less visible or needed (depending on display type).
* Automatic Night-Lights: Useful for systems that need to be dim during the day and bright at night (if logic is inverted) or vice-versa.
* Human Vision Comfort: Prevents glare by adjusting light intensity dynamically.
* Instrumentation: Often used in automotive dashboards or control panels.

Expected outcome:
* Signal Generation: A square wave output at pin 3 of the 555 timer.
* Inverse Response: When the LDR is exposed to strong light (Flashlight), the LED brightness decreases.
* Dark Response: When the LDR is covered (Darkness), the LED brightness increases to maximum.
* Target Audience: Intermediate electronics students and hobbyists.

Materials

  • V1: 9 V DC voltage source, function: Main circuit power.
  • R1: Photoresistor (LDR), function: Light sensor (Charge path).
  • R2: 10 kΩ resistor, function: Discharge path timing.
  • R3: 1 kΩ resistor, function: MOSFET Gate protection.
  • R4: 330 Ω resistor, function: LED current limiting.
  • C1: 100 nF capacitor, function: PWM timing capacitor.
  • C2: 10 nF capacitor, function: Control voltage noise filtering.
  • D1: 1N4148 diode, function: Steering diode for Charge path.
  • D2: 1N4148 diode, function: Steering diode for Discharge path.
  • D3: High-brightness White LED, function: Simulated Backlight.
  • Q1: 2N7000 (N-Channel MOSFET), function: LED driver switch.
  • U1: NE555 Precision Timer, function: PWM generator.

Wiring guide

This guide uses specific node names (VCC, 0, V_TRIG, V_GATE, etc.) to help you verify connections.

  • Power Supply:
  • Connect V1 positive terminal to node VCC.
  • Connect V1 negative terminal to node 0 (GND).
  • 555 Timer Power & Reset (U1):
  • Connect U1 pin 8 (VCC) to node VCC.
  • Connect U1 pin 1 (GND) to node 0.
  • Connect U1 pin 4 (Reset) to node VCC.
  • Timing Network (The PWM Core):
  • Connect R1 (LDR) between node VCC and node V_CHARGE.
  • Connect D1 (Anode) to V_CHARGE and D1 (Cathode) to node V_TIMING.
  • Connect D2 (Anode) to node V_TIMING and D2 (Cathode) to node V_DISCHARGE.
  • Connect R2 between node V_DISCHARGE and U1 pin 7 (Discharge).
  • Connect C1 between node V_TIMING and node 0.
  • Connect U1 pin 2 (Trigger) to node V_TIMING.
  • Connect U1 pin 6 (Threshold) to node V_TIMING.
  • Control Voltage:
  • Connect C2 between U1 pin 5 (CV) and node 0.
  • Output Stage:
  • Connect R3 between U1 pin 3 (Output) and node V_GATE.
  • Connect Q1 Gate to node V_GATE.
  • Connect Q1 Source to node 0.
  • Connect Q1 Drain to node V_LED_CATHODE.
  • Load (Backlight):
  • Connect R4 between node VCC and node V_LED_ANODE.
  • Connect D3 Anode to node V_LED_ANODE.
  • Connect D3 Cathode to node V_LED_CATHODE.

Conceptual block diagram

Conceptual block diagram — TEMPORIZADOR Adaptive PWM Generator
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Adaptive Screen Brightness Regulator

      [ INPUTS / TIMING NETWORK ]              [ LOGIC / CONTROL ]                 [ OUTPUT STAGE ]

[ V1: 9 V Source ] --(Power VCC)--------->+-----------------------+
                                         |                       |
(Light) -> [ R1: LDR ] --(Charge)------->|                       |
                                         |       U1: NE555       |
[ D1, D2, R2 ] --(Steering/Disch)------->|    (PWM Generator)    |--(Pin 3)--> [ R3: 1k ] --> [ Q1: MOSFET ]
                                         |                       |                                  |
[ C1: 100nF ] --(Timing Ramp)----------->|  Pins 2,6 (Trig/Thr)  |                                  |
                                         |  Pin 7 (Discharge)    |                           (Switches GND)
[ C2: 10nF ] --(Filter)----------------->|  Pin 5 (Ctrl Volt)    |                                  |
                                         |                       |                                  v
                                         +-----------------------+                       [ D3: LED + R4: 330R ]
                                                                                              (Backlight)
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Adaptive screen brightness regulator
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Perform these steps to validate the «Inverse» behavior (More light = Less Brightness).

  1. Baseline Check (Ambient Light):
    • Power the circuit with 9 V.
    • Observe the LED D3. It should be illuminated at a moderate level.
    • Measure voltage at V_GATE using an oscilloscope. You should see a square wave.
  2. High Light Test:
    • Shine a flashlight directly onto R1 (LDR).
    • Observation: The LED D3 should dim significantly or turn off.
    • Measurement: Check the duty cycle at V_GATE. Since the LDR resistance drops, the capacitor charges very quickly (short Ton) relative to the fixed discharge time (Toff). The Duty Cycle (Ton / Ttotal) decreases.
  3. Low Light Test:
    • Cover R1 (LDR) with your hand or a black cap.
    • Observation: The LED D3 should reach maximum brightness.
    • Measurement: The LDR resistance increases, making the charge time (Ton) much longer. The Duty Cycle increases towards 100%.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Adaptive Screen Brightness Regulator

* --- Power Supply ---
V1 VCC 0 DC 9

* --- Input Stage (Light Sensor) ---
R1 VCC V_CHARGE 20k

* --- PWM Timing Network ---
D1 V_CHARGE V_TIMING D1N4148
D2 V_TIMING V_DISCHARGE D1N4148
R2 V_DISCHARGE V_DISCH_PIN 10k
C1 V_TIMING 0 100n

* --- Control & Processing ---
* U1: NE555 Precision Timer
XU1 0 V_TIMING V_OUT_PIN VCC V_CV V_TIMING V_DISCH_PIN VCC NE555

* Control Voltage noise filtering
C2 V_CV 0 10n
* ... (truncated in public view) ...

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* Practical case: Adaptive Screen Brightness Regulator

* --- Power Supply ---
V1 VCC 0 DC 9

* --- Input Stage (Light Sensor) ---
R1 VCC V_CHARGE 20k

* --- PWM Timing Network ---
D1 V_CHARGE V_TIMING D1N4148
D2 V_TIMING V_DISCHARGE D1N4148
R2 V_DISCHARGE V_DISCH_PIN 10k
C1 V_TIMING 0 100n

* --- Control & Processing ---
* U1: NE555 Precision Timer
XU1 0 V_TIMING V_OUT_PIN VCC V_CV V_TIMING V_DISCH_PIN VCC NE555

* Control Voltage noise filtering
C2 V_CV 0 10n

* --- Output Driver Stage ---
R3 V_OUT_PIN V_GATE 1k

* Q1: N-Channel MOSFET
MQ1 V_LED_CATHODE V_GATE 0 0 2N7000

* --- Load (Backlight) ---
R4 VCC V_LED_ANODE 330
D3 V_LED_ANODE V_LED_CATHODE WHITE_LED

* --- Component Models ---
.model D1N4148 D (IS=2.682n N=1.836 RS=.5664 BV=100 IBV=100p CJO=4p TT=11.54n)
.model 2N7000 NMOS (Level=1 VTO=2.1 KP=0.5 Lambda=0.002 RD=1.5 RS=1.5 CGSO=10p CGDO=10p CGBO=10p)
.model WHITE_LED D (IS=1p N=5 RS=5 BV=5 IBV=10u CJO=50p)

* --- NE555 Behavioral Subcircuit ---
.subckt NE555 GND TRIG OUT RESET CV THRES DISCH VCC
    * Internal Voltage Divider
    R_div1 VCC CV 5k
    R_div2 CV TR 5k
    R_div3 TR GND 5k

    * Comparators (Sigmoid-based for smooth convergence)
    * Set Signal (Active High) when TRIG < 1/3 VCC (V_TR)
    B_set set_node 0 V = 2.5 + 2.5 * tanh(100 * (V(TR) - V(TRIG)))

    * Reset Signal Logic
    * Condition 1: THRES > CV
    B_c1 c1 0 V = 0.5 * (1 + tanh(100 * (V(THRES) - V(CV))))
    * Condition 2: RESET < 1.0V
    B_c2 c2 0 V = 0.5 * (1 + tanh(100 * (1.0 - V(RESET))))
    * Combine (Probabilistic OR logic): V_rst = c1 + c2 - c1*c2, scaled to 5V
    B_rst rst_node 0 V = 5 * (V(c1) + V(c2) - V(c1)*V(c2))

    * RC Delays to prevent algebraic loops in Flip-Flop
    R_sd set_node set_d 1k
    C_sd set_d 0 1p
    R_rd rst_node rst_d 1k
    C_rd rst_d 0 1p

    * SR Latch (Cross-coupled NOR logic with soft thresholds)
    * Q = ~(R | Qb)
    B_q  q_int  0 V = 5 / (1 + exp( 20 * (V(rst_d) + V(qb_int) - 2.5) ))
    * Qb = ~(S | Q)
    B_qb qb_int 0 V = 5 / (1 + exp( 20 * (V(set_d) + V(q_int) - 2.5) ))

    * Output Buffer
    E_out OUT_int 0 q_int 0 1
    R_out_prot OUT_int OUT 1

    * Discharge Transistor (Switch to GND when Qb is High / Output Low)
    S_disch DISCH 0 qb_int 0 SW_DISCH
    .model SW_DISCH SW(Vt=2.5 Ron=10 Roff=100Meg)
.ends

* --- Simulation Directives ---
.tran 10u 20m
.print tran V(V_TIMING) V(V_GATE) V(V_LED_CATHODE) V(V_LED_ANODE)
.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (4016 rows)
Index   time            v(v_timing)     v(v_gate)       v(v_led_cathode
0	0.000000e+00	3.183820e+00	9.643749e-22	8.709822e+00
1	1.000000e-07	3.183820e+00	9.643749e-22	8.709822e+00
2	2.000000e-07	3.183820e+00	-2.54330e-17	8.709822e+00
3	4.000000e-07	3.183820e+00	4.759196e-18	8.709822e+00
4	8.000000e-07	3.183820e+00	-5.90561e-18	8.709822e+00
5	1.600000e-06	3.183820e+00	1.843922e-17	8.709822e+00
6	3.200000e-06	3.183820e+00	4.911091e-18	8.709822e+00
7	6.400000e-06	3.183819e+00	9.652751e-18	8.709822e+00
8	1.280000e-05	3.183819e+00	-2.42211e-18	8.709822e+00
9	2.280000e-05	3.183818e+00	-2.25892e-17	8.709822e+00
10	3.280000e-05	3.183818e+00	-5.29878e-18	8.709822e+00
11	4.280000e-05	3.183817e+00	-8.38426e-18	8.709822e+00
12	5.280000e-05	3.183816e+00	-5.24090e-18	8.709822e+00
13	6.280000e-05	3.183815e+00	5.344924e-18	8.709822e+00
14	7.280000e-05	3.183815e+00	-6.20163e-18	8.709822e+00
15	8.280000e-05	3.183814e+00	-2.95146e-18	8.709822e+00
16	9.280000e-05	3.183813e+00	-1.95605e-17	8.709822e+00
17	1.028000e-04	3.183813e+00	5.833300e-18	8.709822e+00
18	1.128000e-04	3.183812e+00	-9.79628e-18	8.709822e+00
19	1.228000e-04	3.183812e+00	1.090495e-18	8.709822e+00
20	1.328000e-04	3.183811e+00	-1.79618e-17	8.709822e+00
21	1.428000e-04	3.183810e+00	6.632650e-18	8.709822e+00
22	1.528000e-04	3.183810e+00	-1.47697e-17	8.709822e+00
23	1.628000e-04	3.183809e+00	6.958764e-18	8.709822e+00
... (3992 more rows) ...

Common mistakes and how to avoid them

  1. Reversing Steering Diodes (D1, D2):
    • Error: Placing D1 or D2 backwards prevents the capacitor from charging or discharging properly.
    • Solution: Ensure the black band (cathode) of D1 points towards the capacitor and the black band of D2 points towards Pin 7.
  2. Connecting LDR to Pin 7 directly:
    • Error: Connecting the LDR without the steering diodes creates a standard astable oscillator where frequency changes drastically, but duty cycle control is less distinct.
    • Solution: Use the diode steering topology described to separate the Charge (LDR) and Discharge (R2) paths.
  3. MOSFET Pinout Confusion:
    • Error: Swapping Drain and Source on the 2N7000.
    • Solution: Verify the datasheet. For 2N7000 (TO-92), looking at the flat side, pins are usually Source, Gate, Drain (left to right).

Troubleshooting

  • Symptom: LED is always ON and does not change with light.
    • Cause: MOSFET Gate floating or Pin 3 stuck High.
    • Fix: Check R1 and C1 connections. Ensure Pin 2 and 6 are tied together.
  • Symptom: LED is always OFF.
    • Cause: LDR resistance is too low (short circuit) or LED connected backwards.
    • Fix: Check LED polarity. Measure resistance of LDR in darkness; if it is 0 Ω, it is defective.
  • Symptom: LED flickers visibly.
    • Cause: Frequency is too low.
    • Fix: Reduce the value of C1 (e.g., change from 100 nF to 10 nF) to increase the PWM frequency beyond human persistence of vision (> 100 Hz).

Possible improvements and extensions

  1. Minimum Brightness Clamp: Add a fixed resistor in series with the LDR (R1). This ensures that even in extremely bright light (low LDR resistance), there is still a minimum charge time, preventing the LED from turning off completely.
  2. Smoother Transition: Add a large capacitor across the LDR to filter out rapid changes in light (e.g., shadows from passing objects), creating a «fade» effect rather than an instant jump in brightness.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the circuit described in the text?




Question 2: Which component is responsible for sensing the ambient light levels?




Question 3: What type of signal modulation is used to control the LED brightness?




Question 4: According to the 'Expected outcome', what happens to the LED brightness when the LDR is covered (darkness)?




Question 5: Which component drives the LED strip based on the signal from the 555 timer?




Question 6: Why is this circuit considered useful for energy efficiency?




Question 7: Which pin of the 555 timer outputs the square wave signal?




Question 8: What is the role of the 555 timer in this specific circuit?




Question 9: How does the circuit respond when the LDR is exposed to strong light?




Question 10: Besides energy efficiency, what is another stated benefit of this circuit?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Single-axis solar tracker

Single-axis solar tracker prototype (Maker Style)

Level: Medium. Design a control circuit that compares light levels from two sensors to orient a motor towards the brightest light source.

Objective and use case

This practical case guides you through building an analog control loop that automatically orients a mechanism towards a light source using photoresistors (LDRs) and operational amplifiers. You will construct a «sun seeker» that actively balances two light inputs to drive a motor in the corresponding direction.

  • Real-world applications:
  • Solar Energy: Increases photovoltaic panel efficiency by keeping panels perpendicular to the sun throughout the day.
  • Robotics: Enables light-seeking behaviors (phototaxis) in autonomous robots.
  • Home Automation: Controls smart blinds to regulate room temperature based on sunlight intensity.
  • Expected outcome:
  • When the light source is balanced, the motor remains stationary.
  • When LDR1 is shaded, the voltage difference triggers the motor to spin Clockwise (CW).
  • When LDR2 is shaded, the motor spins Counter-Clockwise (CCW).
  • Target audience: Electronics students familiar with voltage dividers and OpAmps.

Materials

  • V1: 9 V DC power supply (Power source).
  • R1: Photoresistor (LDR), function: Left light sensor.
  • R2: Photoresistor (LDR), function: Right light sensor.
  • R3: 10 kΩ resistor, function: Voltage divider bottom leg for R1.
  • R4: 10 kΩ resistor, function: Voltage divider bottom leg for R2.
  • U1: LM358, function: Dual Operational Amplifier (Comparators).
  • U2: L293D, function: H-Bridge Motor Driver IC.
  • M1: 9 V DC Gear Motor, function: Tracking actuator.
  • C1: 100 nF capacitor, function: Power supply decoupling.

Wiring guide

This circuit uses two parallel voltage dividers compared by two OpAmps to determine motor direction.

  • Power Supply:
  • Connect V1 positive terminal to node VCC.
  • Connect V1 negative terminal to node GND (0).
  • Connect C1 between VCC and GND.

  • Sensors (Dual Voltage Divider):

  • Connect R1 (LDR Left) between VCC and node VA (Sensor Voltage A).
  • Connect R3 between VA and GND.
  • Connect R2 (LDR Right) between VCC and node VB (Sensor Voltage B).
  • Connect R4 between VB and GND.

  • Comparators (LM358 – U1):

  • Comparator A (Turn Right/CW Logic):
    • Connect U1 Non-inverting input (+) to node VA.
    • Connect U1 Inverting input (-) to node VB.
    • Connect U1 Output A to node SIG_CW.
  • Comparator B (Turn Left/CCW Logic):
    • Connect U1 Non-inverting input (+) to node VB.
    • Connect U1 Inverting input (-) to node VA.
    • Connect U1 Output B to node SIG_CCW.
  • Connect U1 VCC pin to VCC and GND pin to GND.

  • Motor Driver (L293D – U2):

  • Connect U2 Input 1 to node SIG_CW.
  • Connect U2 Input 2 to node SIG_CCW.
  • Connect U2 Enable 1 pin to VCC.
  • Connect U2 Output 1 to node M_POS.
  • Connect U2 Output 2 to node M_NEG.
  • Connect U2 VCC1 (Logic) and VCC2 (Power) to VCC.
  • Connect U2 GND pins to GND.

  • Actuator:

  • Connect M1 (Motor) between nodes M_POS and M_NEG.

Conceptual block diagram

Conceptual block diagram — LM358 Solar Tracking Logic
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ INPUTS / SENSORS ]               [ LOGIC / PROCESSING ]                  [ ACTUATOR ]

   [ Power Supply Block ]
   [ Source: V1 (9 V)    ] --(VCC/GND Power)--> (Distributes to all ICs and Sensors)
   [ Filter: C1 (100nF) ]

                                         [ U1: LM358 Dual OpAmp ]
                                         |                      |
   [ Left Light Sensor  ]                | Comparator A (Logic) |
   [ Top: R1 (LDR)      ] --(Signal VA)->| Input: VA > VB ?     |--(SIG_CW)--->+
   [ Bot: R3 (10k Ohm)  ]                | Output: Turn CW      |              |
                                         |                      |              |
                                         |                      |              v
                                         | Comparator B (Logic) |      [ U2: L293D H-Bridge ]
   [ Right Light Sensor ]                | Input: VB > VA ?     |      |                    |
   [ Top: R2 (LDR)      ] --(Signal VB)->| Output: Turn CCW     |      | Input 1: CW Sig    |
   [ Bot: R4 (10k Ohm)  ]                |                      |      | Input 2: CCW Sig   |===(High Current)==> [ M1: Gear Motor ]
                                         +----------+-----------+      | Enable: VCC        |      (9 V DC)
                                                    |                  | VCC1/VCC2: 9 V      |
                                                    +--(SIG_CCW)------>| GND: Common        |
                                                                       +--------------------+
Schematic (ASCII)

Measurements and tests

Follow these steps to validate the tracker logic:

  1. Static Equilibrium Test:

    • Expose both LDRs to ambient light equally.
    • Measure the voltage at node VA and VB. They should be approximately equal.
    • Measure SIG_CW and SIG_CCW. Both should be Low (approx. 0 V) or balanced, keeping the motor stopped.
  2. Left Shade Simulation:

    • Cover R1 (Left LDR) with your hand.
    • Observation: The resistance of R1 increases, causing voltage at VA to drop.
    • Logic Check: Since VB > VA, Comparator B (Non-inverting = VB) should go High (SIG_CCW ≈ VCC).
    • Actuator: The motor should spin Counter-Clockwise.
  3. Right Shade Simulation:

    • Expose R1 to light and cover R2 (Right LDR).
    • Observation: The resistance of R2 increases, causing voltage at VB to drop.
    • Logic Check: Since VA > VB, Comparator A (Non-inverting = VA) should go High (SIG_CW ≈ VCC).
    • Actuator: The motor should spin Clockwise.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Single-axis Solar Tracker Simulation
* Based on Practical Electronics Breadboard Case

* --- Power Supply ---
* V1: 9 V DC power supply
V1 VCC 0 DC 9V
* C1: 100 nF capacitor (Decoupling)
C1 VCC 0 100nF

* --- Dynamic Light Stimulus (Virtual Control) ---
* This source simulates the position of the sun moving from Left to Right.
* 0V = Light on Left Sensor, 5V = Light on Right Sensor.
* Sweeps linearly from 0V to 5V over 100ms.
V_LIGHT LIGHT_POS 0 PWL(0 0 100m 5)

* --- Sensors (LDRs) ---
* Modeled as voltage-dependent resistors controlled by LIGHT_POS.
* R1 (Left LDR): Resistance increases as Light moves Right (LIGHT_POS increases).
* Range: 1k (Bright) to 50k (Dark).
R1 VCC VA R = '1k + 49k * (V(LIGHT_POS)/5)'
* ... (truncated in public view) ...

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* Single-axis Solar Tracker Simulation
* Based on Practical Electronics Breadboard Case

* --- Power Supply ---
* V1: 9 V DC power supply
V1 VCC 0 DC 9V
* C1: 100 nF capacitor (Decoupling)
C1 VCC 0 100nF

* --- Dynamic Light Stimulus (Virtual Control) ---
* This source simulates the position of the sun moving from Left to Right.
* 0V = Light on Left Sensor, 5V = Light on Right Sensor.
* Sweeps linearly from 0V to 5V over 100ms.
V_LIGHT LIGHT_POS 0 PWL(0 0 100m 5)

* --- Sensors (LDRs) ---
* Modeled as voltage-dependent resistors controlled by LIGHT_POS.
* R1 (Left LDR): Resistance increases as Light moves Right (LIGHT_POS increases).
* Range: 1k (Bright) to 50k (Dark).
R1 VCC VA R = '1k + 49k * (V(LIGHT_POS)/5)'

* R2 (Right LDR): Resistance decreases as Light moves Right.
* Range: 50k (Dark) to 1k (Bright).
R2 VCC VB R = '1k + 49k * (1 - V(LIGHT_POS)/5)'

* --- Voltage Divider Bottom Legs ---
* R3: 10 kΩ resistor for R1
R3 VA 0 10k
* R4: 10 kΩ resistor for R2
R4 VB 0 10k

* --- Comparators (U1: LM358) ---
* U1 is a Dual OpAmp. We define a subcircuit matching the 8-pin DIP pinout.
* Pinout: 1=OutA, 2=In-A, 3=In+A, 4=GND, 5=In+B, 6=In-B, 7=OutB, 8=VCC
* Wiring Guide:
* Comparator A (CW): (+) VA, (-) VB -> Out SIG_CW
* Comparator B (CCW): (+) VB, (-) VA -> Out SIG_CCW
XU1 SIG_CW VB VA 0 VB VA SIG_CCW VCC LM358_DIP8

* --- Motor Driver (U2: L293D) ---
* U2 is an H-Bridge Driver. We define a subcircuit for the used pins.
* Pinout used: 1=EN1, 2=IN1, 3=OUT1, 4/5=GND, 6=OUT2, 7=IN2, 8=VCC2, 16=VCC1
* Wiring Guide:
* IN1=SIG_CW, IN2=SIG_CCW, OUT1=M_POS, OUT2=M_NEG, EN1=VCC
XU2 VCC SIG_CW M_POS 0 0 M_NEG SIG_CCW VCC VCC L293D_BRIDGE

* --- Actuator (M1: 9V DC Gear Motor) ---
* Modeled as a resistive/inductive load.
R_M1 M_POS M_INT 20
L_M1 M_INT M_NEG 5mH

* --- Subcircuit Definitions ---

.subckt LM358_DIP8 OUTA INMA INPA GND INPB INMB OUTB VCC
* Comparator A Behavior (Sigmoid for convergence)
* Output swings approx 0V to VCC-1.5V
B_OUTA OUTA 0 V = (V(VCC)-1.5) / (1 + exp(-50*(V(INPA)-V(INMA)))) + 0.05
* Comparator B Behavior
B_OUTB OUTB 0 V = (V(VCC)-1.5) / (1 + exp(-50*(V(INPB)-V(INMB)))) + 0.05
.ends

.subckt L293D_BRIDGE EN1 IN1 OUT1 GND1 GND2 OUT2 IN2 VCC2 VCC1
* Logic Threshold approx 2.0V.
* Output Voltage ~ VCC2 - 1.4V drop.
* Enable Logic
B_EN node_en 0 V = 1 / (1 + exp(-50*(V(EN1)-2.0)))
* Output 1 (M_POS)
B_O1 OUT1 0 V = V(node_en) * (1/(1+exp(-50*(V(IN1)-2.0)))) * (V(VCC2)-1.4)
* Output 2 (M_NEG)
B_O2 OUT2 0 V = V(node_en) * (1/(1+exp(-50*(V(IN2)-2.0)))) * (V(VCC2)-1.4)
.ends

* --- Simulation Directives ---
.op
* Transient analysis: 100ms duration to capture the full light sweep
.tran 100u 100m

* Print signals to verify logic:
* VA/VB: Sensor Voltages
* SIG_CW/CCW: Comparator Logic Outputs
* M_POS/M_NEG: Motor Drive Voltages
.print tran V(VA) V(VB) V(SIG_CW) V(SIG_CCW) V(M_POS) V(M_NEG) V(LIGHT_POS)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (3024 rows)
Index   time            v(va)           v(vb)           v(sig_cw)
0	0.000000e+00	8.181818e+00	1.500000e+00	7.550000e+00
1	1.000000e-06	8.181454e+00	1.500012e+00	7.550000e+00
2	2.000000e-06	8.181089e+00	1.500025e+00	7.550000e+00
3	4.000000e-06	8.180361e+00	1.500049e+00	7.550000e+00
4	8.000000e-06	8.178903e+00	1.500098e+00	7.550000e+00
5	1.600000e-05	8.175990e+00	1.500196e+00	7.550000e+00
6	3.200000e-05	8.170168e+00	1.500392e+00	7.550000e+00
7	6.400000e-05	8.158542e+00	1.500784e+00	7.550000e+00
8	1.280000e-04	8.135365e+00	1.501569e+00	7.550000e+00
9	2.280000e-04	8.099394e+00	1.502797e+00	7.550000e+00
10	3.280000e-04	8.063833e+00	1.504028e+00	7.550000e+00
11	4.280000e-04	8.028586e+00	1.505260e+00	7.550000e+00
12	5.280000e-04	7.993645e+00	1.506495e+00	7.550000e+00
13	6.280000e-04	7.959008e+00	1.507732e+00	7.550000e+00
14	7.280000e-04	7.924669e+00	1.508970e+00	7.550000e+00
15	8.280000e-04	7.890626e+00	1.510211e+00	7.550000e+00
16	9.280000e-04	7.856873e+00	1.511454e+00	7.550000e+00
17	1.028000e-03	7.823409e+00	1.512699e+00	7.550000e+00
18	1.128000e-03	7.790228e+00	1.513945e+00	7.550000e+00
19	1.228000e-03	7.757327e+00	1.515194e+00	7.550000e+00
20	1.328000e-03	7.724703e+00	1.516445e+00	7.550000e+00
21	1.428000e-03	7.692352e+00	1.517698e+00	7.550000e+00
22	1.528000e-03	7.660271e+00	1.518953e+00	7.550000e+00
23	1.628000e-03	7.628457e+00	1.520211e+00	7.550000e+00
... (3000 more rows) ...

Common mistakes and how to avoid them

  1. LDRs placed too close together:

    • Symptom: The system is insensitive and requires extreme light angles to react.
    • Solution: Mount the LDRs with a physical blinder (a piece of cardboard or plastic) between them so a shadow is cast on one LDR when the light is not perfectly centered.
  2. Driving the motor directly from OpAmps:

    • Symptom: The motor hums but doesn’t turn, or the OpAmp overheats and fails.
    • Solution: Always use a current driver stage like the L293D or a transistor H-Bridge. OpAmps cannot supply the current required by motors (typically >100 mA).
  3. Lack of Deadband (Jittering):

    • Symptom: The motor constantly vibrates back and forth when the light is centered.
    • Solution: This basic topology is a «bang-bang» controller. In advanced designs, add hysteresis resistors to the OpAmps to create a small voltage window where the motor remains off.

Troubleshooting

  • Motor spins in the wrong direction:
    • Cause: The motor polarity is reversed relative to the sensor placement.
    • Fix: Swap the connections of M1 (M_POS and M_NEG) OR physically swap the positions of R1 and R2.
  • Motor runs continuously even in equal light:
    • Cause: Large tolerance difference between the two LDRs or fixed resistors (R3/R4).
    • Fix: Replace one fixed resistor (e.g., R3) with a 10k trim potentiometer to calibrate the bridge balance manually.
  • Nothing happens when light changes:
    • Cause: L293D Enable pin not connected high.
    • Fix: Ensure the Enable pin of the driver is connected to VCC.

Possible improvements and extensions

  1. Sensitivity Control: Replace the fixed resistors R3 and R4 with a single multi-turn potentiometer. Connect the wiper to ground and the ends to the LDRs to allow fine-tuning of the center point.
  2. Solar Power Integration: Replace V1 with a small solar panel and a charging circuit to make the tracker self-sustaining.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary objective of the control circuit described in the text?




Question 2: Which component is used as the light sensor in this circuit?




Question 3: What is a real-world application of this 'sun seeker' circuit mentioned in the text?




Question 4: How does the motor behave when the light source is balanced between the two sensors?




Question 5: What happens to the motor when LDR1 is shaded?




Question 6: What happens to the motor when LDR2 is shaded?




Question 7: Which component is identified as U1 in the context of this circuit?




Question 8: Which component is identified as U2 and is responsible for driving the motor?




Question 9: What is the role of the 10 kΩ resistors (R3 and R4) in the circuit design?




Question 10: Who is the specific target audience for this practical case?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: R-2R Resistor Network (Simple DAC)

R-2R Resistor Network (Simple DAC) prototype (Maker Style)

Level: Medium. Construct a resistive ladder to convert 4-bit binary signals into precise analog voltage levels.

Objective and use case

In this session, you will build a 4-bit Digital-to-Analog Converter (DAC) using an R-2R resistor ladder topology. This circuit sums binary weighted inputs to produce an analog output proportional to the digital value.

Why it is useful:
* Audio Synthesis: Used in simple function generators to create sine or triangle waves from digital microcontrollers.
* Video Signals: Historically used in VGA adapters to generate color intensity levels.
* Cost-Effective Control: Allows generating variable control voltages without dedicated DAC chips.
* Signal Processing Education: Demonstrates superposition and Thevenin’s theorem in a practical way.

Expected outcome:
* A stable output voltage (VOUT) that ranges from 0 V to approximately 4.68 V (given a 5 V supply).
* Sixteen distinct voltage steps (from binary 0000 to 1111).
* Linear relationship between the binary input value and the measured analog voltage.

Target audience and level: Electronics students and hobbyists familiar with basic circuit laws.

Materials

  • V1: 5 V DC supply, function: Logic high reference and main power.
  • R1: 10 kΩ resistor, function: Series resistor (R) in ladder spine (Bit 0-1).
  • R2: 10 kΩ resistor, function: Series resistor (R) in ladder spine (Bit 1-2).
  • R3: 10 kΩ resistor, function: Series resistor (R) in ladder spine (Bit 2-3).
  • R4: 20 kΩ resistor, function: Parallel resistor (2R) for Bit 0 (LSB).
  • R5: 20 kΩ resistor, function: Parallel resistor (2R) for Bit 1.
  • R6: 20 kΩ resistor, function: Parallel resistor (2R) for Bit 2.
  • R7: 20 kΩ resistor, function: Parallel resistor (2R) for Bit 3 (MSB).
  • R8: 20 kΩ resistor, function: Termination resistor (2R) connected to Ground.
  • SW1: SPDT switch (or jumper wire), function: Bit 0 input (LSB), switches between VCC and GND.
  • SW2: SPDT switch (or jumper wire), function: Bit 1 input, switches between VCC and GND.
  • SW3: SPDT switch (or jumper wire), function: Bit 2 input, switches between VCC and GND.
  • SW4: SPDT switch (or jumper wire), function: Bit 3 input (MSB), switches between VCC and GND.

Wiring guide

This guide uses node names: VCC (5 V), 0 (GND), B0 (Bit 0 Input), B1 (Bit 1 Input), B2 (Bit 2 Input), B3 (Bit 3 Input), and internal ladder nodes N0, N1, N2. VOUT is the analog output.

  • V1 Connection: Connect V1 positive terminal to VCC and negative to 0.
  • Input Switches (Digital Inputs):
    • SW1: Common to B0, Position 1 to 0, Position 2 to VCC.
    • SW2: Common to B1, Position 1 to 0, Position 2 to VCC.
    • SW3: Common to B2, Position 1 to 0, Position 2 to VCC.
    • SW4: Common to B3, Position 1 to 0, Position 2 to VCC.
  • Ladder «R» Resistors (Spine):
    • R1: Connects between node N0 and node N1.
    • R2: Connects between node N1 and node N2.
    • R3: Connects between node N2 and node VOUT.
  • Ladder «2R» Resistors (Branches):
    • R8 (Termination): Connects between node N0 and 0.
    • R4: Connects between node B0 and node N0.
    • R5: Connects between node B1 and node N1.
    • R6: Connects between node B2 and node N2.
    • R7: Connects between node B3 and node VOUT.
  • Output: Monitor voltage at node VOUT relative to 0.

Conceptual block diagram

Conceptual block diagram — LM358 R-2R Ladder DAC
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ DIGITAL INPUTS ]              [ R-2R LADDER NETWORK ]                 [ ANALOG OUTPUT ]
(Switches toggle VCC/GND)           (Voltage Summing Logic)

                                                                           +--> [ Multimeter ]
                                                                           |    (Measure V)
[ SW4: Bit 3 (MSB) ] --(High/Low)--> [ R7: 20k (2R) ] --(Bit 3 Weight)---->+--> [ VOUT Node  ]
                                                            ^
                                                            |
                                                     [ R3: 10k (R) ]
                                                            |
[ SW3: Bit 2       ] --(High/Low)--> [ R6: 20k (2R) ] --(Bit 2 Weight)---->+ (Node N2)
                                                            ^
                                                            |
                                                     [ R2: 10k (R) ]
                                                            |
[ SW2: Bit 1       ] --(High/Low)--> [ R5: 20k (2R) ] --(Bit 1 Weight)---->+ (Node N1)
                                                            ^
                                                            |
                                                     [ R1: 10k (R) ]
                                                            |
[ SW1: Bit 0 (LSB) ] --(High/Low)--> [ R4: 20k (2R) ] --(Bit 0 Weight)---->+ (Node N0)
                                                            |
                                                            v
                                                     [ R8: 20k (2R) ]
                                                            |
                                                           GND
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Practical case: R-2R Resistor Network (Simple DAC)
Generated from the validated SPICE netlist for this case.

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Measurements and tests

To validate the DAC, you will set the switches to specific binary codes and measure the resulting voltage at VOUT. The formula for the output is:
$VOUT = Vref × ((Decimal Value) / 16)$

  1. Zero Check: Set all switches (SW1-SW4) to 0 (GND). Measure VOUT. It should be exactly 0 V.
  2. LSB Check (Bit 0): Set SW1 to VCC and others to 0 (Binary 0001).
    • Calculation: $5 V × (1/16) = 0.3125 V$.
    • Verify VOUT is approx 0.31 V.
  3. MSB Check (Bit 3): Set SW4 to VCC and others to 0 (Binary 1000).
    • Calculation: $5 V × (8/16) = 2.5 V$.
    • Verify VOUT is approx 2.5 V.
  4. Full Scale Check: Set all switches to VCC (Binary 1111).
    • Calculation: $5 V × (15/16) = 4.6875 V. * Verify VOUT is approx 4.69 V. <! – – SPICE_INSERT_POINT – – > ## Common mistakes and how to avoid them 1. Floating Inputs: Leaving a switch open (disconnected) instead of connecting it to Ground for logic «0». * Solution: R – 2R ladders require inputs to be strictly atV_{ref}$ or $0 V$. Use SPDT switches or verify your jumper wires connect to GND when «off».
  5. Swapping R and 2R: Placing a 10 kΩ resistor where a 20 kΩ is required (or vice versa).
    • Solution: Double-check color codes. 10 kΩ is usually Brown-Black-Orange; 20 kΩ is Red-Black-Orange.
  6. Loading the Output: Connecting a low-impedance load (like a speaker or LED) directly to VOUT.
    • Solution: This circuit has a relatively high output impedance ($R$). Always use an Op-Amp buffer (voltage follower) if you need to drive a load.

Troubleshooting

  • Symptom: $V_{OUT}$ is 2.5 V when it should be 1.25 V.
    • Cause: The MSB (Bit 3) might be stuck high, or resistors are swapped.
    • Fix: Check switch continuity and verify resistor placement at node VOUT.
  • Symptom: Output voltages are non-linear or random.
    • Cause: Poor connection on the «spine» resistors (R1, R2, R3).
    • Fix: Re-seat the resistors on the breadboard to ensure the ladder chain is intact.
  • Symptom: Output never reaches near 4.6 V.
    • Cause: Resistor tolerance accumulation or low power supply voltage.
    • Fix: Measure V1 actual voltage. Use 1% tolerance metal film resistors for better precision.

Possible improvements and extensions

  1. 8-Bit Expansion: Add four more stages to the ladder (using more R and 2R resistors) to create an 8-bit DAC with 256 voltage steps.
  2. Active Buffering: Connect VOUT to an LM358 Op-Amp configured as a unity-gain buffer to drive an LED or a small audio speaker safely.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the circuit described in the text?




Question 2: Which resistor topology is used to build the DAC in this session?




Question 3: What is the expected maximum output voltage (V_OUT) given a 5 V supply?




Question 4: How many distinct voltage steps can a 4-bit DAC produce?




Question 5: Which of the following is a historical use case mentioned for this type of circuit?




Question 6: What relationship is expected between the binary input value and the measured analog voltage?




Question 7: What theoretical concepts does this project demonstrate practically?




Question 8: Why is the R-2R ladder considered a cost-effective control method?




Question 9: Which application involves creating sine or triangle waves from digital microcontrollers?




Question 10: Who is the target audience for this project?




SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: R-2R Resistor Network (Simple DAC)

* --- Power Supply ---
* V1: 5 V DC supply, function: Logic high reference and main power
V1 VCC 0 DC 5

* --- Digital Inputs (Simulated Switches) ---
* Modeled as PULSE voltage sources to strictly simulate user input/switching.
* Generates a binary counting sequence (0000 to 1111) to test the full truth table.
* Logic High = 5V (VCC), Logic Low = 0V (GND).

* SW1 (Bit 0 LSB): Toggles every 100us (Period)
VB0 B0 0 PULSE(0 5 0 1u 1u 50u 100u)

* SW2 (Bit 1): Toggles every 200us (Period)
VB1 B1 0 PULSE(0 5 0 1u 1u 100u 200u)

* SW3 (Bit 2): Toggles every 400us (Period)
VB2 B2 0 PULSE(0 5 0 1u 1u 200u 400u)

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: R-2R Resistor Network (Simple DAC)

* --- Power Supply ---
* V1: 5 V DC supply, function: Logic high reference and main power
V1 VCC 0 DC 5

* --- Digital Inputs (Simulated Switches) ---
* Modeled as PULSE voltage sources to strictly simulate user input/switching.
* Generates a binary counting sequence (0000 to 1111) to test the full truth table.
* Logic High = 5V (VCC), Logic Low = 0V (GND).

* SW1 (Bit 0 LSB): Toggles every 100us (Period)
VB0 B0 0 PULSE(0 5 0 1u 1u 50u 100u)

* SW2 (Bit 1): Toggles every 200us (Period)
VB1 B1 0 PULSE(0 5 0 1u 1u 100u 200u)

* SW3 (Bit 2): Toggles every 400us (Period)
VB2 B2 0 PULSE(0 5 0 1u 1u 200u 400u)

* SW4 (Bit 3 MSB): Toggles every 800us (Period)
VB3 B3 0 PULSE(0 5 0 1u 1u 400u 800u)

* --- R-2R Ladder Network ---

* -- Spine Resistors (R = 10k) --
* R1: Connects between node N0 and node N1
R1 N0 N1 10k

* R2: Connects between node N1 and node N2
R2 N1 N2 10k

* R3: Connects between node N2 and node VOUT
R3 N2 VOUT 10k

* -- Branch/Termination Resistors (2R = 20k) --
* R8 (Termination): Connects between node N0 and 0 (GND)
R8 N0 0 20k

* R4 (Bit 0 Input): Connects between node B0 and node N0
R4 B0 N0 20k

* R5 (Bit 1 Input): Connects between node B1 and node N1
R5 B1 N1 20k

* R6 (Bit 2 Input): Connects between node B2 and node N2
R6 B2 N2 20k

* R7 (Bit 3 Input - MSB): Connects between node B3 and node VOUT
R7 B3 VOUT 20k

* --- Simulation Directives ---
* Transient analysis to capture the full binary counting sequence (approx 1ms)
.tran 2u 1000u

* --- Output Printing ---
* Monitor the Input Bits and the Analog Output Voltage
.print tran V(B0) V(B1) V(B2) V(B3) V(VOUT)

.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (1384 rows)
Index   time            v(b0)           v(b1)           v(b2)
0	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
1	1.000000e-08	5.000000e-02	5.000000e-02	5.000000e-02
2	2.000000e-08	1.000000e-01	1.000000e-01	1.000000e-01
3	4.000000e-08	2.000000e-01	2.000000e-01	2.000000e-01
4	8.000000e-08	4.000000e-01	4.000000e-01	4.000000e-01
5	1.600000e-07	8.000000e-01	8.000000e-01	8.000000e-01
6	3.200000e-07	1.600000e+00	1.600000e+00	1.600000e+00
7	6.400000e-07	3.200000e+00	3.200000e+00	3.200000e+00
8	1.000000e-06	5.000000e+00	5.000000e+00	5.000000e+00
9	1.064000e-06	5.000000e+00	5.000000e+00	5.000000e+00
10	1.192000e-06	5.000000e+00	5.000000e+00	5.000000e+00
11	1.448000e-06	5.000000e+00	5.000000e+00	5.000000e+00
12	1.960000e-06	5.000000e+00	5.000000e+00	5.000000e+00
13	2.984000e-06	5.000000e+00	5.000000e+00	5.000000e+00
14	4.984000e-06	5.000000e+00	5.000000e+00	5.000000e+00
15	6.984000e-06	5.000000e+00	5.000000e+00	5.000000e+00
16	8.984000e-06	5.000000e+00	5.000000e+00	5.000000e+00
17	1.098400e-05	5.000000e+00	5.000000e+00	5.000000e+00
18	1.298400e-05	5.000000e+00	5.000000e+00	5.000000e+00
19	1.498400e-05	5.000000e+00	5.000000e+00	5.000000e+00
20	1.698400e-05	5.000000e+00	5.000000e+00	5.000000e+00
21	1.898400e-05	5.000000e+00	5.000000e+00	5.000000e+00
22	2.098400e-05	5.000000e+00	5.000000e+00	5.000000e+00
23	2.298400e-05	5.000000e+00	5.000000e+00	5.000000e+00
... (1360 more rows) ...
Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: Unbalanced Wheatstone Bridge

Unbalanced Wheatstone Bridge prototype (Maker Style)

Level: Medium. Analyze differential voltage variation in a resistive bridge by modifying a sensor.

Objective and use case

You will build a Wheatstone bridge circuit using three fixed resistors and one variable resistor to simulate a resistive sensor. This circuit converts a change in resistance into a measurable differential voltage output.

Why it is useful:
* Precision Sensing: Used in load cells (weighing scales) and strain gauges where resistance changes are minute.
* Temperature Measurement: Fundamental for reading RTDs (Resistance Temperature Detectors) and thermistors.
* Zero Calibration: Allows systems to establish a «null point» (0 V output) to cancel out offset errors before taking measurements.
* Small Signal Detection: Filters out power supply noise common to both legs of the bridge (Common Mode Rejection).

Expected outcome:
* Balanced State: When the variable resistor matches the ratio of the fixed arm, the differential voltage (VAB) reads exactly 0 V.
* Unbalanced State: As the resistance changes, VAB becomes positive or negative depending on the direction of the change.
* Sensitivity: You will observe the non-linear relationship between the resistance change (\Delta R) and the output voltage (VOUT).

Target audience and level: Electronics students and hobbyists familiar with Ohm’s Law (Medium).

Materials

  • V1: 5 V DC voltage source, function: main power supply.
  • R1: 1 kΩ resistor, function: upper reference arm.
  • R2: 1 kΩ resistor, function: lower reference arm.
  • R3: 1 kΩ resistor, function: upper measurement arm.
  • R4: 2 kΩ potentiometer (linear), function: variable resistor (simulating a sensor like a thermistor or strain gauge).

Wiring guide

This circuit consists of two parallel voltage dividers connected to a common source. The output is taken differentially between the center points of these dividers.

  • V1 connects between node VCC (positive) and node 0 (GND).
  • R1 connects between node VCC and node VA (Reference Point).
  • R2 connects between node VA and node 0.
  • R3 connects between node VCC and node VB (Measurement Point).
  • R4 connects between node VB and node 0.
  • Measurement: The output VOUT is measured between node VA and node VB.

Conceptual block diagram

Conceptual block diagram — Unbalanced Wheatstone Bridge
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ SOURCE ]                     [ BRIDGE PROCESSING ]                     [ OUTPUT ]

                               +-----------------------------+
                               |   Reference Divider (Left)  |
                            +->|  (Fixed Ratio: R1 / R2)     |--(Node VA)-->+
                            |  |  [ R1: 1 kΩ ] + [ R2: 1 kΩ ]  |              |
                            |  +-----------------------------+              |
                            |                                               v
[ V1: 5 V DC ] --(Supply)--> +                                          [ V_OUT ]
                            |                                          (Differential)
                            |  +-----------------------------+         ( VA - VB )
                            |  |  Measurement Divider (Right)|              ^
                            +->|  (Variable Ratio: R3 / R4)  |--(Node VB)-->+
                               |  [ R3: 1 kΩ ] + [ R4: Pot ]  |
                               +-----------------------------+
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Unbalanced Wheatstone Bridge
Generated from the validated SPICE netlist for this case.

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Measurements and tests

Follow these steps to validate the bridge operation using a voltmeter or multimeter.

  1. Setup: Power the circuit with 5 V. Set your multimeter to measure DC Voltage in the 20 V or 2 V range.
  2. Verify Reference: Measure the voltage between VA and 0 (GND). With R1 and R2 being equal (1 kΩ), this should be stable at exactly 2.5 V.
  3. Find the Null Point: Connect the multimeter probes between VA (red probe) and VB (black probe). Adjust potentiometer R4 until the multimeter reads 0.00 V.
    • Observation: At this point, the bridge is balanced (R1 / R2 = R3 / R4). R4 should be approximately 1 kΩ.
  4. Simulate Sensor Increase: Increase the resistance of R4.
    • Observation: The voltage at VB rises. The differential reading (VA – VB) will become negative (assuming Red probe on A, Black on B).
  5. Simulate Sensor Decrease: Decrease the resistance of R4 below 1 kΩ.
    • Observation: The voltage at VB drops. The differential reading will become positive.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Unbalanced Wheatstone Bridge

* --- Power Supply ---
* V1: 5 V DC voltage source, main power supply
V1 VCC 0 DC 5

* --- Reference Arm (Left) ---
* R1: 1 kΩ, upper reference arm
R1 VCC VA 1k

* R2: 1 kΩ, lower reference arm
R2 VA 0 1k

* --- Measurement Arm (Right) ---
* R3: 1 kΩ, upper measurement arm
R3 VCC VB 1k

* R4: 2 kΩ potentiometer (simulating sensor), lower measurement arm
* Connected between VB and 0. Set to 2k to demonstrate unbalanced state.
R4 VB 0 2k
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Unbalanced Wheatstone Bridge

* --- Power Supply ---
* V1: 5 V DC voltage source, main power supply
V1 VCC 0 DC 5

* --- Reference Arm (Left) ---
* R1: 1 kΩ, upper reference arm
R1 VCC VA 1k

* R2: 1 kΩ, lower reference arm
R2 VA 0 1k

* --- Measurement Arm (Right) ---
* R3: 1 kΩ, upper measurement arm
R3 VCC VB 1k

* R4: 2 kΩ potentiometer (simulating sensor), lower measurement arm
* Connected between VB and 0. Set to 2k to demonstrate unbalanced state.
R4 VB 0 2k

* --- Simulation Setup ---
* Calculate DC operating point
.op

* Transient analysis (10ms duration to verify stability)
.tran 100u 10m

* --- Output Directives ---
* Monitor Supply, Reference Voltage (VA), and Sensor Voltage (VB)
* Differential Output VOUT = V(VA) - V(VB)
.print tran V(VCC) V(VA) V(VB)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (108 rows)
Index   time            v(vcc)          v(va)           v(vb)
0	0.000000e+00	5.000000e+00	2.500000e+00	3.333333e+00
1	1.000000e-06	5.000000e+00	2.500000e+00	3.333333e+00
2	2.000000e-06	5.000000e+00	2.500000e+00	3.333333e+00
3	4.000000e-06	5.000000e+00	2.500000e+00	3.333333e+00
4	8.000000e-06	5.000000e+00	2.500000e+00	3.333333e+00
5	1.600000e-05	5.000000e+00	2.500000e+00	3.333333e+00
6	3.200000e-05	5.000000e+00	2.500000e+00	3.333333e+00
7	6.400000e-05	5.000000e+00	2.500000e+00	3.333333e+00
8	1.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
9	2.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
10	3.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
11	4.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
12	5.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
13	6.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
14	7.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
15	8.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
16	9.280000e-04	5.000000e+00	2.500000e+00	3.333333e+00
17	1.028000e-03	5.000000e+00	2.500000e+00	3.333333e+00
18	1.128000e-03	5.000000e+00	2.500000e+00	3.333333e+00
19	1.228000e-03	5.000000e+00	2.500000e+00	3.333333e+00
20	1.328000e-03	5.000000e+00	2.500000e+00	3.333333e+00
21	1.428000e-03	5.000000e+00	2.500000e+00	3.333333e+00
22	1.528000e-03	5.000000e+00	2.500000e+00	3.333333e+00
23	1.628000e-03	5.000000e+00	2.500000e+00	3.333333e+00
... (84 more rows) ...

Common mistakes and how to avoid them

  1. Measuring relative to Ground: Students often measure VA to GND and VB to GND separately. While valid, the bridge is designed to be measured differentially (VA to VB) directly.
    • Solution: Place the voltmeter probes directly across the bridge midpoints.
  2. Using low-tolerance resistors: If R1 and R2 have high tolerance (e.g., 10%), the reference voltage VA will not be exactly VCC/2, making the null point hard to calculate.
    • Solution: Use 1% metal film resistors for R1, R2, and R3 for precision.
  3. Loading the bridge: Connecting a low-impedance load (like a motor or a low-resistance speaker) directly between VA and VB.
    • Solution: The bridge is for signal measurement, not power. Always connect the output nodes to a high-impedance input, such as an Op-Amp or microcontroller ADC.

Troubleshooting

  • Symptom: Output voltage is always 0 V regardless of potentiometer position.
    • Cause: Power supply is off or there is a short circuit between VA and VB.
    • Fix: Check V1 connections and ensure the two legs of the bridge are not shorted together.
  • Symptom: Cannot reach 0 V (Null point) output.
    • Cause: The fixed resistor R3 is significantly different from the range of potentiometer R4.
    • Fix: Ensure R4’s range includes the value of R3 (e.g., if R3 is 1 kΩ, R4 must be capable of reaching 1 kΩ).
  • Symptom: Readings are unstable or «jittery».
    • Cause: Noisy potentiometer wiper or loose breadboard contacts.
    • Fix: Replace the potentiometer or ensure solid connections on the breadboard.

Possible improvements and extensions

  1. Instrumentation Amplifier: Feed nodes VA and VB into an instrumentation amplifier (like the AD620) to amplify the small differential voltage for a microcontroller to read.
  2. Physical Sensor: Replace R4 with a photoresistor (LDR) or a thermistor (NTC). Observe how light or temperature changes the bridge balance.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the Wheatstone bridge circuit described in the objective?




Question 2: Which component in the circuit is used to simulate a resistive sensor like a thermistor or strain gauge?




Question 3: What is the expected differential voltage (V_AB) when the bridge is in a 'Balanced State'?




Question 4: Why is 'Zero Calibration' mentioned as a useful feature of this circuit?




Question 5: In the context of 'Small Signal Detection', what does the bridge circuit help filter out?




Question 6: What happens to the differential voltage (V_AB) in an 'Unbalanced State'?




Question 7: Which application is explicitly listed as a use case for precision sensing with this circuit?




Question 8: What relationship is generally observed between the resistance change and the output voltage in a Wheatstone bridge?




Question 9: What is the role of the component labeled V1 in the context of this circuit?




Question 10: Which specific type of temperature sensor is mentioned as fundamental for reading with this circuit?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: Empty Tank Level Indicator

Empty Tank Level Indicator prototype (Maker Style)

Level: Medium. Design a logic circuit that alerts the user when a water sensor stops detecting liquid using a NOT gate.

Objective and use case

In this case, you will build a monitoring circuit using a 74HC04 inverter that illuminates a red LED when a tank’s liquid level drops below a critical point.

  • Prevents pump damage: Stops water pumps from running dry in hydroponic systems.
  • Household safety: Alerts when rooftop reserve tanks are empty.
  • Industrial maintenance: Visual flag for coolant refill requirements.

Expected outcome:
* Water Present: The sensor is open (Logic 1 input) $\rightarrow$ LED remains OFF.
* Tank Empty: The sensor closes (Logic 0 input) $\rightarrow$ LED turns ON.
* Logic Level: $V_{in} \approx 0\text{ V}$ activates the alert; $V_{in} \approx 5\text{ V}$ indicates normal status.

Target audience: Electronics students and hobbyists familiar with basic digital logic.

Materials

  • V1: 5 V DC power supply, function: main circuit power
  • U1: 74HC04 Hex Inverter IC, function: logic inversion
  • S1: Float switch (SPST, configured to Close when Empty), function: liquid level sensor
  • R1: 10 kΩ resistor, function: pull-up for sensor signal
  • R2: 330 Ω resistor, function: LED current limiting
  • D1: Red LED, function: visual empty alert
  • C1: 100 nF ceramic capacitor, function: power supply decoupling

Pin-out of the IC used

Selected Chip: 74HC04 (Hex Inverter)

Pin Name Logic function Connection in this case
1 1A Input Connected to Sensor Node (SENSE_IN)
2 1Y Output Connected to LED circuit (ALERT_OUT)
7 GND Ground Connected to GND (0 V)
14 VCC Power Connected to 5 V Supply

Wiring guide

  • V1 connects between node VCC and node GND.
  • C1 connects between node VCC and node GND (placed physically close to U1).
  • R1 connects between node VCC and node SENSE_IN.
  • S1 connects between node SENSE_IN and node GND.
  • U1 pin 1 connects to node SENSE_IN.
  • U1 pin 2 connects to node ALERT_OUT.
  • U1 pin 14 connects to VCC; pin 7 connects to GND.
  • R2 connects between node ALERT_OUT and node LED_ANODE.
  • D1 connects between node LED_ANODE (Anode) and node GND (Cathode).

Conceptual block diagram

Conceptual block diagram — 74HC04 NOT gate

Schematic

[ INPUT / SENSOR ]                 [ LOGIC PROCESSING ]                 [ OUTPUT / ALERT ]

[ VCC 5V ] --> [ R1: 10k ] --+
               (Pull-Up)     |
                             |
                             V
                        (SENSE_IN) ---->+------------------+
                        (Pin 1)         |    U1: 74HC04    |
                             ^          |   Hex Inverter   |--(ALERT_OUT)--> [ R2: 330R ] --> [ D1: Red LED ] --> GND
                             |          |   (Pin 1 -> 2)   |  (Pin 2)        (Limiting)       (Anode/Cathode)
[ GND 0V ] --> [ S1: Float ]-+          +------------------+
               (Switch)                           ^
                                                  |
                                            [ C1: 100nF ]
                                            (Decoupling)
                                            (VCC / GND)
Schematic (ASCII)

Truth table

Water State Sensor Switch (S1) Input Voltage (Pin 1) Logic Input Output Voltage (Pin 2) LED State
Full OPEN 5 V (via Pull-up) 1 0 V OFF
Empty CLOSED 0 V (connected to GND) 0 5 V ON

Measurements and tests

  1. Supply Check: Measure voltage between VCC and GND. Ensure it is stable at 5 V.
  2. Full Tank Simulation: Manually lift the float (ensure S1 is OPEN). Measure voltage at SENSE_IN. It should be $\approx 5\text{ V}$. Verify LED is OFF.
  3. Empty Tank Simulation: Drop the float (ensure S1 is CLOSED). Measure voltage at SENSE_IN. It should be $\approx 0\text{ V}$.
  4. Logic Output: While S1 is closed (Empty), measure voltage at ALERT_OUT. It should be $\approx 5\text{ V}$.
  5. Current Draw: Measure the current through D1 ($I_{led}$) when ON. It should be approximately 10–12 mA depending on the specific LED voltage drop.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Empty Tank Level Indicator

* ==============================================================================
* BILL OF MATERIALS & COMPONENTS
* ==============================================================================

* --- Power Supply ---
* V1: 5 V DC power supply
V1 VCC 0 DC 5

* --- Decoupling ---
* C1: 100 nF ceramic capacitor (Power supply decoupling)
C1 VCC 0 100n

* --- Sensor Input Section ---
* R1: 10 kΩ resistor (Pull-up for sensor signal)
R1 VCC SENSE_IN 10k

* S1: Float switch (SPST)
* Wiring: Connects between node SENSE_IN and node GND.
* ... (truncated in public view) ...

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* Practical case: Empty Tank Level Indicator

* ==============================================================================
* BILL OF MATERIALS & COMPONENTS
* ==============================================================================

* --- Power Supply ---
* V1: 5 V DC power supply
V1 VCC 0 DC 5

* --- Decoupling ---
* C1: 100 nF ceramic capacitor (Power supply decoupling)
C1 VCC 0 100n

* --- Sensor Input Section ---
* R1: 10 kΩ resistor (Pull-up for sensor signal)
R1 VCC SENSE_IN 10k

* S1: Float switch (SPST)
* Wiring: Connects between node SENSE_IN and node GND.
* Simulation: Modeled as a Voltage Controlled Switch (SW).
* Logic: 
*   - Tank Full (Float Up) -> Switch Open -> SENSE_IN pulled to VCC.
*   - Tank Empty (Float Down) -> Switch Closed -> SENSE_IN pulled to GND.
* Control Source V_FLOAT_ACT simulates the float movement.
*   - 0V = Float Up (Full)
*   - 5V = Float Down (Empty)
S1 SENSE_IN 0 FLOAT_CTRL 0 SW_FLOAT
.model SW_FLOAT SW(Vt=2.5 Ron=0.1 Roff=10Meg)

* Stimulus: Float starts Up (Full), drops to Down (Empty) at 50us, returns at 200us.
V_FLOAT_ACT FLOAT_CTRL 0 PULSE(0 5 50u 1u 1u 150u 400u)

* --- Logic Processing ---
* U1: 74HC04 Hex Inverter
* Wiring Guide: Pin 1 (In) -> SENSE_IN, Pin 2 (Out) -> ALERT_OUT
* Power: Pin 14 -> VCC, Pin 7 -> GND
* Implemented as a subcircuit to strictly map pins.
XU1 SENSE_IN ALERT_OUT 0 VCC 74HC04_GATE

* Subcircuit definition for one gate of 74HC04
.subckt 74HC04_GATE IN OUT GND VCC
    * Behavioral voltage source for robust logic inversion
    * Uses sigmoid function for convergence: Vout = VCC if Vin < 2.5V
    B1 OUT GND V = V(VCC) * (1 / (1 + exp(50 * (V(IN) - 2.5))))
.ends

* --- Output Alert ---
* R2: 330 Ω resistor (LED current limiting)
R2 ALERT_OUT LED_ANODE 330

* D1: Red LED (Visual empty alert)
* Wiring: Anode -> LED_ANODE, Cathode -> GND
D1 LED_ANODE 0 LED_RED
.model LED_RED D(IS=1e-14 N=2 RS=5 BV=5 IBV=10u CJO=40p)

* ==============================================================================
* ANALYSIS COMMANDS
* ==============================================================================

* Operating Point Analysis
.op

* Transient Analysis
* Run for 500us to capture the float switch activation cycle
.tran 1u 500u

* Output Printing
* Monitor Sensor Input, Inverter Output, and LED Voltage
.print tran V(SENSE_IN) V(ALERT_OUT) V(LED_ANODE) V(FLOAT_CTRL)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (1190 rows)
Index   time            v(sense_in)     v(alert_out)    v(led_anode)
0	0.000000e+00	4.995005e+00	3.316079e-54	-1.70080e-28
1	1.000000e-08	4.995005e+00	3.316079e-54	-9.73961e-29
2	2.000000e-08	4.995005e+00	3.316079e-54	-1.41516e-29
3	4.000000e-08	4.995005e+00	3.316079e-54	8.723601e-29
4	8.000000e-08	4.995005e+00	3.316079e-54	1.163518e-28
5	1.600000e-07	4.995005e+00	3.316079e-54	4.380930e-29
6	3.200000e-07	4.995005e+00	3.316079e-54	-1.45299e-29
7	6.400000e-07	4.995005e+00	3.316079e-54	-1.01395e-29
8	1.280000e-06	4.995005e+00	3.316079e-54	-5.46095e-32
9	2.280000e-06	4.995005e+00	3.316079e-54	4.098577e-31
10	3.280000e-06	4.995005e+00	3.316079e-54	2.282032e-32
11	4.280000e-06	4.995005e+00	3.316079e-54	-9.50625e-33
12	5.280000e-06	4.995005e+00	3.316079e-54	-1.09186e-33
13	6.280000e-06	4.995005e+00	3.316079e-54	1.911218e-34
14	7.280000e-06	4.995005e+00	3.316079e-54	3.847480e-35
15	8.280000e-06	4.995005e+00	3.316079e-54	-2.97995e-36
16	9.280000e-06	4.995005e+00	3.316079e-54	-1.15977e-36
17	1.028000e-05	4.995005e+00	3.316079e-54	1.723722e-38
18	1.128000e-05	4.995005e+00	3.316079e-54	3.117034e-38
19	1.228000e-05	4.995005e+00	3.316079e-54	1.177223e-39
20	1.328000e-05	4.995005e+00	3.316079e-54	-7.52109e-40
21	1.428000e-05	4.995005e+00	3.316079e-54	-6.99870e-41
22	1.528000e-05	4.995005e+00	3.316079e-54	1.597704e-41
23	1.628000e-05	4.995005e+00	3.316079e-54	2.660714e-42
... (1166 more rows) ...

Common mistakes and how to avoid them

  1. Leaving inputs floating: Even though we only use one gate (Pin 1/2), unused inputs on CMOS chips (pins 3, 5, 9, 11, 13) should be tied to GND or VCC to prevent oscillation and excess power consumption.
  2. Incorrect Pull-up wiring: Connecting the resistor in series with the input instead of as a pull-up to VCC. Ensure R1 goes strictly to 5V.
  3. Sensor Logic inversion: Using a sensor that is Open when Empty without changing the circuit logic. This would cause the light to be ON when the tank is full. Ensure the mechanical action matches the truth table.

Troubleshooting

  • LED is always ON: Check if S1 is stuck in the Closed position or if pin 1 is shorted to ground.
  • LED never turns ON: Check if the float switch is actually closing the circuit to ground. Measure resistance across S1 terminals while moving the float.
  • Chip gets hot: Check for short circuits at the output or if VCC/GND are reversed (Pins 14 and 7).
  • LED flickers: The liquid might be turbulent. Add a capacitor (e.g., 10 µF) in parallel with S1 to create a hardware debounce delay.

Possible improvements and extensions

  1. Audio Alert: Add a 5V active buzzer in parallel with the LED/Resistor combo to provide an audible alarm when the tank is empty.
  2. Hysteresis: Replace the 74HC04 with a 74HC14 (Schmitt Trigger Inverter). This prevents the LED from jittering if the water level is right at the switching threshold.

More Practical Cases on Prometeo.blog

Quick Quiz

Question 1: What is the primary function of the circuit described in the objective?




Question 2: Which specific logic gate IC is used to perform the inversion in this circuit?




Question 3: How does the LED behave when the water sensor detects liquid (Logic 1 input)?




Question 4: What is the state of the sensor input when the tank is empty according to the expected outcome?




Question 5: What is the primary role of the 10 kΩ resistor (R1) in this specific circuit design?




Question 6: Which component serves as the visual indicator for the alert?




Question 7: What voltage level (Vin) corresponds to a 'normal status' where the alert is inactive?




Question 8: What is a listed practical application for this circuit?




Question 9: The float switch (S1) is configured to do what when the tank is empty?




Question 10: What logic level activates the alert (turns the LED ON)?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: Production Line Fault Monitoring

Production Line Fault Monitoring prototype (Maker Style)

Level: Medium. Implement a safety system that stops a conveyor belt if either the temperature sensor OR the jam sensor detects an anomaly.

Objective and use case

You will build a logic control circuit using an OR gate to combine signals from two distinct safety sensors (Temperature and Optical Jam). When either sensor detects a fault (Logic High), the system will output an active signal to trigger an indicator or stop mechanism.

Why it is useful:
* Industrial Safety: Prevents machinery from operating under dangerous conditions.
* Equipment Protection: Stops motors immediately if they overheat to prevent permanent damage.
* Process Efficiency: Detects physical jams on conveyor belts automatically, reducing waste.
* Redundancy: Allows multiple different error types to trigger the same emergency stop routine.

Expected outcome:
* System Standby: When both sensors are Low (0V), the output LED is OFF.
* Temperature Fault: If the temperature sensor triggers (High/5V), the LED turns ON.
* Jam Fault: If the jam sensor triggers (High/5V), the LED turns ON.
* Critical Failure: If both sensors trigger simultaneously, the LED remains ON.

Target audience and level: Electronics students and hobbyists, Level Medium.

Materials

  • V1: 5 V DC power supply, function: Main circuit power.
  • U1: 74HC32, function: Quad 2-input OR gate IC.
  • S1: SPST Toggle Switch, function: Simulates Temperature Sensor (Open=Normal, Closed=Overheat).
  • S2: SPST Toggle Switch, function: Simulates Jam Sensor (Open=Clear, Closed=Jam).
  • R1: 10 kΩ resistor, function: Pull-down for Temperature Input.
  • R2: 10 kΩ resistor, function: Pull-down for Jam Input.
  • R3: 330 Ω resistor, function: Current limiting for indicator LED.
  • D1: Red LED, function: Visual Fault Indicator.

Pin-out of the IC used

Selected Chip: 74HC32 (Quad 2-Input OR Gate)

Pin Name Logic function Connection in this case
1 1A Input A Connected to Temperature Sensor (S1)
2 1B Input B Connected to Jam Sensor (S2)
3 1Y Output Connected to LED driver (R3 + D1)
7 GND Ground Connected to Power Supply Negative (0V)
14 VCC Power (+) Connected to Power Supply Positive (5V)

Wiring guide

  • VCC: Connect V1 positive terminal to U1 pin 14.
  • 0 (GND): Connect V1 negative terminal to U1 pin 7.
  • VA (Temp Signal): Connect S1 terminal 2 to U1 pin 1.
  • VA (Temp Signal): Connect R1 between U1 pin 1 and 0.
  • VCC: Connect S1 terminal 1 to VCC.
  • VB (Jam Signal): Connect S2 terminal 2 to U1 pin 2.
  • VB (Jam Signal): Connect R2 between U1 pin 2 and 0.
  • VCC: Connect S2 terminal 1 to VCC.
  • V_OUT: Connect U1 pin 3 to R3 terminal 1.
  • LED_NODE: Connect R3 terminal 2 to D1 Anode.
  • 0 (GND): Connect D1 Cathode to 0.

Conceptual block diagram

Conceptual block diagram — 74HC32 OR gate

Schematic

Title: Production Line Fault Monitoring (OR Logic)

      [ INPUT SENSORS ]                       [ LOGIC PROCESSING ]                 [ VISUAL OUTPUT ]

                                                 (Pin 14: VCC)
                                                       |
                                                       v
[ VCC ] --> [ S1: Temp Switch ] --+--(Pin 1)-->+---------------+
                                  |            |               |
                             [ R1: 10k ]       |   U1: 74HC32  |
                                  |            |   (OR Gate)   |--(Pin 3)--> [ R3: 330 ] --> [ D1: LED ] --> [ GND ]
                               [ GND ]         |               |
                                               |               |
[ VCC ] --> [ S2: Jam Switch  ] --+--(Pin 2)-->+---------------+
                                  |                    ^
                             [ R2: 10k ]               |
                                  |               (Pin 7: GND)
                               [ GND ]
Schematic (ASCII)

Truth table

This circuit utilizes positive logic (Active High).

Sensor A (Temp) Sensor B (Jam) Output (Fault Indicator) LED State
Low (0) Low (0) Low (0) OFF
Low (0) High (1) High (1) ON
High (1) Low (0) High (1) ON
High (1) High (1) High (1) ON

Measurements and tests

  1. Standby Check: Ensure both switches S1 and S2 are open. Measure voltage at U1 Pin 3 relative to GND. It should be ~0 V. LED should be OFF.
  2. Temperature Fault Simulation: Close S1 while keeping S2 open. Measure voltage at Pin 1 (Input A). It should be 5 V. The Output Pin 3 should go to High (~5 V) and the LED must light up.
  3. Jam Fault Simulation: Open S1 and close S2. Measure voltage at Pin 2 (Input B). It should be 5 V. The LED must light up.
  4. Simultaneous Fault: Close both S1 and S2. The LED must remain ON.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Production Line Fault Monitoring

* --- Component Models ---
* Generic Red LED Model
.model DLED D (IS=1e-14 N=2 RS=10 BV=5 IBV=10u CJO=10p)

* --- Subcircuits ---
* 74HC32 Quad 2-input OR Gate
* Pinout: 1=InputA, 2=InputB, 3=Output, 7=GND, 14=VCC
* Implemented using a robust behavioral source with continuous functions
.subckt 74HC32 1 2 3 7 14
* Logic: Output = VCC if (A > 2.5V OR B > 2.5V)
* Using sigmoid function for smooth convergence: S(x) = 1/(1+exp(-k*(x-thresh)))
* max(V(1), V(2)) selects the higher voltage to compare against threshold (2.5V)
B_OR 3 7 V = V(14) * (1 / (1 + exp(-20 * (max(V(1), V(2)) - 2.5))))
.ends

* --- Main Power Supply ---
* V1: 5V DC Supply
* Wiring: Positive -> Node 14 (VCC), Negative -> Node 0 (GND)
V1 14 0 DC 5

* --- Input Sensors (Simulated Switches) ---
* S1: Temperature Sensor Switch
* Wiring: Connects VCC to VA (Pin 1). Modeled as Pulse Source to simulate toggling.
* Logic Sequence: High (Overheat) / Low (Normal)
VS1 VA 0 PULSE(0 5 0 1u 1u 200u 400u)

* S2: Jam Sensor Switch
* Wiring: Connects VCC to VB (Pin 2). Modeled as Pulse Source with faster period.
* ... (truncated in public view) ...

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* Practical case: Production Line Fault Monitoring

* --- Component Models ---
* Generic Red LED Model
.model DLED D (IS=1e-14 N=2 RS=10 BV=5 IBV=10u CJO=10p)

* --- Subcircuits ---
* 74HC32 Quad 2-input OR Gate
* Pinout: 1=InputA, 2=InputB, 3=Output, 7=GND, 14=VCC
* Implemented using a robust behavioral source with continuous functions
.subckt 74HC32 1 2 3 7 14
* Logic: Output = VCC if (A > 2.5V OR B > 2.5V)
* Using sigmoid function for smooth convergence: S(x) = 1/(1+exp(-k*(x-thresh)))
* max(V(1), V(2)) selects the higher voltage to compare against threshold (2.5V)
B_OR 3 7 V = V(14) * (1 / (1 + exp(-20 * (max(V(1), V(2)) - 2.5))))
.ends

* --- Main Power Supply ---
* V1: 5V DC Supply
* Wiring: Positive -> Node 14 (VCC), Negative -> Node 0 (GND)
V1 14 0 DC 5

* --- Input Sensors (Simulated Switches) ---
* S1: Temperature Sensor Switch
* Wiring: Connects VCC to VA (Pin 1). Modeled as Pulse Source to simulate toggling.
* Logic Sequence: High (Overheat) / Low (Normal)
VS1 VA 0 PULSE(0 5 0 1u 1u 200u 400u)

* S2: Jam Sensor Switch
* Wiring: Connects VCC to VB (Pin 2). Modeled as Pulse Source with faster period.
* Logic Sequence: High (Jam) / Low (Clear)
VS2 VB 0 PULSE(0 5 0 1u 1u 100u 200u)

* --- Pull-down Resistors ---
* R1: 10k Pull-down for Temp Input
R1 VA 0 10k
* R2: 10k Pull-down for Jam Input
R2 VB 0 10k

* --- Logic IC U1 ---
* U1: 74HC32 Quad OR Gate
* Connections per wiring guide:
* Pin 1 (A) -> VA
* Pin 2 (B) -> VB
* Pin 3 (Y) -> V_OUT
* Pin 7 (GND) -> 0
* Pin 14 (VCC) -> 14
XU1 VA VB V_OUT 0 14 74HC32

* --- Output Indicator ---
* R3: 330 Ohm Current Limiting Resistor
R3 V_OUT LED_NODE 330

* D1: Red LED Visual Indicator
* Anode -> LED_NODE, Cathode -> GND
D1 LED_NODE 0 DLED

* --- Analysis Directives ---
* Transient analysis to capture truth table states (00, 01, 10, 11)
.tran 1u 400u

* Print required voltages for verification
.print tran V(VA) V(VB) V(V_OUT) V(LED_NODE)

* Calculate DC operating point
.op

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (906 rows)
Index   time            v(va)           v(vb)           v(v_out)
0	0.000000e+00	0.000000e+00	0.000000e+00	9.643749e-22
1	1.000000e-08	5.000000e-02	5.000000e-02	1.928750e-21
2	2.000000e-08	1.000000e-01	1.000000e-01	5.242886e-21
3	4.000000e-08	2.000000e-01	2.000000e-01	2.137746e-20
4	8.000000e-08	4.000000e-01	4.000000e-01	2.632654e-19
5	1.600000e-07	8.000000e-01	8.000000e-01	2.587285e-17
6	3.200000e-07	1.600000e+00	1.600000e+00	7.614990e-08
7	4.700575e-07	2.350288e+00	2.350288e+00	2.384318e-01
8	6.126008e-07	3.063004e+00	3.063004e+00	4.999936e+00
9	7.041960e-07	3.520980e+00	3.520980e+00	5.000000e+00
10	7.932149e-07	3.966074e+00	3.966074e+00	5.000000e+00
11	9.007723e-07	4.503862e+00	4.503862e+00	5.000000e+00
12	1.000000e-06	5.000000e+00	5.000000e+00	5.000000e+00
13	1.021511e-06	5.000000e+00	5.000000e+00	5.000000e+00
14	1.064534e-06	5.000000e+00	5.000000e+00	5.000000e+00
15	1.150580e-06	5.000000e+00	5.000000e+00	5.000000e+00
16	1.322672e-06	5.000000e+00	5.000000e+00	5.000000e+00
17	1.666856e-06	5.000000e+00	5.000000e+00	5.000000e+00
18	2.355224e-06	5.000000e+00	5.000000e+00	5.000000e+00
19	3.355224e-06	5.000000e+00	5.000000e+00	5.000000e+00
20	4.355224e-06	5.000000e+00	5.000000e+00	5.000000e+00
21	5.355224e-06	5.000000e+00	5.000000e+00	5.000000e+00
22	6.355224e-06	5.000000e+00	5.000000e+00	5.000000e+00
23	7.355224e-06	5.000000e+00	5.000000e+00	5.000000e+00
... (882 more rows) ...

Common mistakes and how to avoid them

  1. Leaving Inputs Floating: Failing to install pull-down resistors (R1, R2) causes the inputs to «float» and pick up noise, causing the LED to flicker or stay ON randomly. Solution: Always use 10kΩ pull-down resistors on CMOS inputs connected to switches.
  2. Missing Current Limiting Resistor: Connecting the LED directly to the 74HC32 output pin without R3. Solution: Ensure R3 (330Ω) is in series with the LED to prevent burning out the IC or the LED.
  3. Confusing Pinout: Treating the 74HC32 like a different logic chip (e.g., 74HC02 NOR) due to similar package shape. Solution: Always verify the datasheet pin diagram; Pin 3 is output for the first gate on the 74HC32.

Troubleshooting

  • LED is always ON: Check if pull-down resistors R1 and R2 are connected to Ground. If inputs are disconnected, they float High.
  • LED is very dim: The resistor R3 might be too high (e.g., 10kΩ instead of 330Ω) or the power supply voltage is below 3V.
  • Nothing happens when switches close: Verify that U1 Pin 14 is connected to 5V and Pin 7 is connected to GND. Check switch continuity.
  • Logic is inverted (LED OFF when fault occurs): You may have accidentally used a NOR gate or wired the LED active-low (Anode to VCC, Cathode to Output).

Possible improvements and extensions

  1. Latching Alarm: Add an SR Flip-Flop or a feedback loop so that once a fault is detected, the alarm stays ON until a manual «Reset» button is pressed, even if the sensor returns to normal.
  2. Audible Alert: Connect a transistor driver and a 5V active buzzer in parallel with the LED to provide an audio warning for noisy factory environments.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary logic gate used in this safety system circuit?




Question 2: What happens to the output LED when both the temperature sensor and the jam sensor are Low (0V)?




Question 3: Which component is typically used to simulate the Temperature Sensor in a basic prototype of this project?




Question 4: What is the specific function of the 74HC32 IC in this circuit?




Question 5: Why are pull-down resistors typically used on the input switches in this logic circuit?




Question 6: If only the Jam Sensor triggers (High/5V), what is the expected state of the LED?




Question 7: What is the primary purpose of a resistor placed in series with the output LED?




Question 8: Which of the following is listed as a benefit of this system for 'Equipment Protection'?




Question 9: What is the standard logic voltage level (High) used for the sensors in this description?




Question 10: How does the system behave during a 'Critical Failure' where both sensors trigger simultaneously?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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