Practical case: Shadow detector for visual alert

Shadow detector for visual alert prototype (Maker Style)

Level: Medium — Build a stable shadow detector with visual indication and low false triggering.

Objective and use case

You will build a photoresistor-based circuit that detects a sudden drop in light caused by a shadow and turns on an LED in a stable way. The design uses an LDR voltage divider, an RC filter, and a comparator with hysteresis to reduce false activations.

Why it is useful:

  • Detect when a hand or object passes in front of a lighted opening.
  • Create a simple visual warning for access points, boxes, or cabinets.
  • Monitor brief shadow events in classroom experiments on light sensing.
  • Add a reliable light-change trigger to small automation prototypes.

Expected outcome:

  • Sensor voltage at VA changes with light level, typically from about 0.8 V to 4.2 V depending on illumination.
  • Filtered voltage at VB changes more slowly than VA, reducing short spikes and flicker.
  • Comparator output at VOUT switches cleanly between low and high states.
  • LED D1 turns on when light drops below the adjusted threshold and remains stable near the switching point.
  • Hysteresis of about 0.2 V to 0.5 V avoids repeated on/off oscillation.

Target audience and level: Students with basic knowledge of resistors, capacitors, and voltage measurement.

Materials

  • V1: 5 V DC supply
  • R1: LDR photoresistor, function: light-dependent upper arm of sensor divider
  • R2: 10 kΩ potentiometer, function: adjustable lower arm of sensor divider and threshold tuning aid
  • R3: 22 kΩ resistor, function: series resistor from sensor node to RC filter
  • C1: 10 µF capacitor, function: low-pass filter for shadow event stabilization
  • U1: LM393 comparator, function: compare filtered sensor voltage against adjustable reference
  • R4: 10 kΩ potentiometer, function: reference voltage adjustment for comparator
  • R5: 220 kΩ resistor, function: positive feedback to add hysteresis
  • R6: 10 kΩ resistor, function: pull-up for LM393 open-collector output
  • D1: red LED, function: visual alert output
  • R7: 330 Ω resistor, function: LED current limiting

Wiring guide

  • V1 connects between nodes VCC and 0.
  • R1 connects between nodes VCC and VA.
  • R2 connects between nodes VA and 0; use the potentiometer as a variable resistor to adjust the divider sensitivity.
  • R3 connects between nodes VA and VB.
  • C1 connects between nodes VB and 0.
  • R4 connects between nodes VCC and 0; connect the wiper of R4 to node VREF.
  • U1 LM393 power pins connect as follows: supply pin to VCC, ground pin to 0.
  • U1 comparator non-inverting input connects to node VREF.
  • U1 comparator inverting input connects to node VB.
  • R5 connects between nodes VOUT and VREF.
  • R6 connects between nodes VCC and VOUT.
  • R7 connects between nodes VCC and VLED.
  • D1 connects between nodes VLED and VOUT; orient the LED so it turns on when VOUT is pulled low by U1.

Conceptual block diagram

Conceptual block diagram — COMPARADOR Photoresistor (LDR)
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Practical case: Shadow detector for visual alert

Light / Shadow
      --> [ R1: LDR ]
      --> (VA: sensor divider node)
      --> [ R3: 22 kΩ ]
      --> (VB: filtered sensor signal)
      --> [ U1: LM393 Comparator (-) ]

VCC --> [ R2: 10 kΩ Pot, sensitivity adjust ] --> GND
                  \
                   --> (VA)

VCC --> [ R4: 10 kΩ Pot, reference adjust ] --> GND
                  \
                   --> (VREF)
                   --> [ U1: LM393 Comparator (+) ]

[ U1: LM393 Comparator Output VOUT ]
      --> [ R5: 220 kΩ Positive Feedback ] --> (VREF)
      --> [ D1: Red LED ] --> [ R7: 330 Ω ] --> VCC
      --> [ Alert Output: LED ON when VOUT goes LOW ]

VCC --> [ R6: 10 kΩ Pull-up ] --> (VOUT)

(VB) --> [ C1: 10 µF Low-Pass Filter ] --> GND

V1: 5 V DC --> VCC
V1: 0 V    --> GND
U1 power: VCC, GND
Electrical Schematic

Electrical diagram

Electrical diagram for the shadow detector for visual alert case
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

  1. Power-off inspection
  2. Check that VCC and 0 are not shorted.
  3. Confirm LED polarity.
  4. Verify that the LM393 output has a pull-up resistor R6.

  5. Supply check

  6. Power the circuit with V1 = 5 V.
  7. Measure between VCC and 0; expected value: 4.9 V to 5.1 V.

  8. Sensor voltage measurement

  9. Measure VA in bright light and then under a shadow.
  10. Expected result: VA should change clearly, often by more than 1 V.
  11. If the change is too small, adjust R2 or change the light angle on the LDR.

  12. Filtered response measurement

  13. Measure VB while suddenly covering the LDR.
  14. VB should not jump instantly; it should move with a short delay set by R3 × C1.
  15. With R3 = 22 kΩ and C1 = 10 µF, the time constant is about 0.22 s.

  16. Threshold adjustment

  17. Adjust R4 until D1 is off in normal light and turns on when a clear shadow is applied.
  18. Measure VREF; typical useful range is 1 V to 4 V.

  19. Hysteresis verification

  20. Slowly move a hand to create a partial shadow and then slowly remove it.
  21. Measure the switching voltage at VB when the LED turns on and when it turns off.
  22. The two values should differ slightly because of R5; a difference of 0.2 V to 0.5 V is a good target.

  23. Response time test

  24. Repeatedly create a sudden shadow and observe LED behavior.
  25. The LED should react within a fraction of a second, without flickering from very brief light variations.
  26. If the response is too slow, reduce C1 to 4.7 µF.
  27. If false triggering remains, increase C1 to 22 µF or increase R5 slightly for more hysteresis.

  28. False activation test

  29. Illuminate the LDR with room light and introduce small disturbances such as hand motion nearby but not fully covering it.
  30. The LED should remain stable unless the light drop is large enough to cross the threshold.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Shadow detector for visual alert
.width out=256

.param R2VAL=5k
.param R4POS=0.5
.param R4TOP={10000*(1-R4POS)+1m}
.param R4BOT={10000*(R4POS)+1m}
.param RLIGHT=2k
.param RDARK=50k

V1 VCC 0 DC 5

* Dynamic light/shadow stimulus: 0 = light, 1 = shadow
VLUX LUX 0 PULSE(0 1 50m 1m 1m 200m 400m)

* R1 LDR photoresistor: upper arm of divider
R1 VCC VA r='{RLIGHT + (RDARK-RLIGHT)*V(LUX)}'

* R2 10k potentiometer used as variable resistor
R2 VA 0 {R2VAL}
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Shadow detector for visual alert
.width out=256

.param R2VAL=5k
.param R4POS=0.5
.param R4TOP={10000*(1-R4POS)+1m}
.param R4BOT={10000*(R4POS)+1m}
.param RLIGHT=2k
.param RDARK=50k

V1 VCC 0 DC 5

* Dynamic light/shadow stimulus: 0 = light, 1 = shadow
VLUX LUX 0 PULSE(0 1 50m 1m 1m 200m 400m)

* R1 LDR photoresistor: upper arm of divider
R1 VCC VA r='{RLIGHT + (RDARK-RLIGHT)*V(LUX)}'

* R2 10k potentiometer used as variable resistor
R2 VA 0 {R2VAL}

R3 VA VB 22k
C1 VB 0 10u

* R4 10k potentiometer with wiper at VREF
R4A VCC VREF {R4TOP}
R4B VREF 0 {R4BOT}

* U1 LM393 approximation
* Non-inverting input: VREF
* Inverting input: VB
* Open-collector output: VOUT
B_U1DRV NBASE 0 V='0.95*(1+tanh(80*(V(VREF)-V(VB))))/2'
R_U1B NBASE 0 100k
Q_U1 VOUT NBASE 0 QLM393OC

R5 VOUT VREF 220k
R6 VCC VOUT 10k

R7 VCC VLED 330
D1 VLED VOUT DRED

* Probe aliases so .print can include V(IN) and V(OUT) first
V_INMON IN VB DC 0
V_OUTMON OUT VOUT DC 0

.model QLM393OC NPN(IS=1e-14 BF=100 VAF=100 CJE=5p CJC=3p TF=1n TR=10n)
.model DRED D(IS=1e-18 N=2.0 RS=10 CJO=5p VJ=0.75 M=0.33 TT=50n BV=5 IBV=10u)

.print tran V(IN) V(OUT) V(VB) V(VOUT) V(VREF) V(VA) V(VLED) V(LUX)
.op
.tran 100u 500m
.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation is consistent with a shadow detector. In bright condition, VA and VB are high, VB is above VREF, the LM393 output transistor is off, and VOUT stays high at about 4.89 V so the LED is off. After the light-to-shadow transition, VA drops, VB falls slowly because of the R3-C1 filter, and when VB crosses below VREF at about 0.168 s, VOUT is pulled low to about 18 mV and the LED turns on. When light returns, VB rises slowly again, so the alert remains on for a while before resetting, consistent with RC filtering and hysteresis.
* bom/wiring vs SPICE issues (modelo):
*   - The LM393 is not a specific manufacturer macro-model; it is only an approximation of open-collector comparator behavior. This is acceptable for logic/function teaching, but not for accurate device-level output saturation or input common-mode behavior.
* bom_vs_spice equivalences ignored:
*   - R2 is described in the wiring guide as a 10 kΩ potentiometer used as a variable resistor, but the netlist fixes it with .param R2VAL=5k. This is acceptable for one simulation run, but the adjustable setting is not exposed unless the parameter is changed manually.
*   - The 10 kΩ potentiometer R4 is validly modeled as two resistors R4A and R4B with the wiper at node VREF.
*   - The LDR R1 is validly modeled as a resistor whose value changes with a control stimulus (behavioral resistance driven by VLUX).
*   - The LED D1 is validly modeled as a diode, with R7 providing the series current limit.
*   - The LM393 comparator is validly modeled with behavioral circuitry plus an NPN open-collector output stage.
*   - The changing light/shadow condition is validly modeled by the PULSE source VLUX.
* overall_comment: This SPICE netlist is broadly faithful to the BOM and wiring and is usable as a didactic example of a shadow-triggered visual alarm. The divider, RC filter, adjustable reference, hysteresis, open-collector pull-up, and active-low LED wiring all match the intended circuit. The main caveat is pedagogical: the LM393 is only behaviorally approximated, and R2 is represented by a fixed chosen value rather than an interactively adjustable potentiometer position. Before classroom use, I would explain the active-low output, the delayed switching caused by R3-C1, and the role of positive feedback R5 in shifting VREF slightly between output states.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation is consistent with a shadow detector. In bright condition, VA and VB are high, VB is above VREF, the LM393 output transistor is off, and VOUT stays high at about 4.89 V so the LED is off. After the light-to-shadow transition, VA drops, VB falls slowly because of the R3-C1 filter, and when VB crosses below VREF at about 0.168 s, VOUT is pulled low to about 18 mV and the LED turns on. When light returns, VB rises slowly again, so the alert remains on for a while before resetting, consistent with RC filtering and hysteresis.
Show raw data table (5027 rows)
Index   time            v(in)           v(out)          v(vb)           v(vout)         v(vref)         v(va)           v(vled)         v(lux)
0	0.000000e+00	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
1	1.000000e-06	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
2	2.000000e-06	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
3	4.000000e-06	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
4	8.000000e-06	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
5	1.600000e-05	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
6	3.200000e-05	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
7	6.400000e-05	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
8	1.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
9	2.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
10	3.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
11	4.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
12	5.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
13	6.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
14	7.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
15	8.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
16	9.280000e-04	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
17	1.028000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
18	1.128000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
19	1.228000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
20	1.328000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
21	1.428000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
22	1.528000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
23	1.628000e-03	3.571429e+00	4.892473e+00	3.571429e+00	4.892473e+00	2.526882e+00	3.571429e+00	5.000000e+00	0.000000e+00
... (5003 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Shadow detector for visual alert
.width out=256

.param R2VAL=5k
.param R4POS=0.5
.param R4TOP={10000*(1-R4POS)+1m}
.param R4BOT={10000*(R4POS)+1m}
.param RLIGHT=2k
.param RDARK=50k

V1 VCC 0 DC 5

* Dynamic light/shadow stimulus: 0 = light, 1 = shadow
VLUX LUX 0 PULSE(0 1 50m 1m 1m 200m 400m)

* R1 LDR photoresistor: upper arm of divider
R1 VCC VA r='{RLIGHT + (RDARK-RLIGHT)*V(LUX)}'

* R2 10k potentiometer used as variable resistor
R2 VA 0 {R2VAL}

R3 VA VB 22k
C1 VB 0 10u

* R4 10k potentiometer with wiper at VREF
R4A VCC VREF {R4TOP}
R4B VREF 0 {R4BOT}

* U1 LM393 approximation
* Non-inverting input: VREF
* Inverting input: VB
* Open-collector output: VOUT
B_U1DRV NBASE 0 V='0.95*(1+tanh(80*(V(VREF)-V(VB))))/2'
R_U1B NBASE 0 100k
Q_U1 VOUT NBASE 0 QLM393OC

R5 VOUT VREF 220k
R6 VCC VOUT 10k

R7 VCC VLED 330
D1 VLED VOUT DRED

* Probe aliases so .print can include V(IN) and V(OUT) first
V_INMON IN VB DC 0
V_OUTMON OUT VOUT DC 0

.model QLM393OC NPN(IS=1e-14 BF=100 VAF=100 CJE=5p CJC=3p TF=1n TR=10n)
.model DRED D(IS=1e-18 N=2.0 RS=10 CJO=5p VJ=0.75 M=0.33 TT=50n BV=5 IBV=10u)

.print tran V(IN) V(OUT) V(VB) V(VOUT) V(VREF) V(VA) V(VLED) V(LUX)
.op
.tran 100u 500m
.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation is consistent with a shadow detector. In bright condition, VA and VB are high, VB is above VREF, the LM393 output transistor is off, and VOUT stays high at about 4.89 V so the LED is off. After the light-to-shadow transition, VA drops, VB falls slowly because of the R3-C1 filter, and when VB crosses below VREF at about 0.168 s, VOUT is pulled low to about 18 mV and the LED turns on. When light returns, VB rises slowly again, so the alert remains on for a while before resetting, consistent with RC filtering and hysteresis.
* bom/wiring vs SPICE issues (modelo):
*   - The LM393 is not a specific manufacturer macro-model; it is only an approximation of open-collector comparator behavior. This is acceptable for logic/function teaching, but not for accurate device-level output saturation or input common-mode behavior.
* bom_vs_spice equivalences ignored:
*   - R2 is described in the wiring guide as a 10 kΩ potentiometer used as a variable resistor, but the netlist fixes it with .param R2VAL=5k. This is acceptable for one simulation run, but the adjustable setting is not exposed unless the parameter is changed manually.
*   - The 10 kΩ potentiometer R4 is validly modeled as two resistors R4A and R4B with the wiper at node VREF.
*   - The LDR R1 is validly modeled as a resistor whose value changes with a control stimulus (behavioral resistance driven by VLUX).
*   - The LED D1 is validly modeled as a diode, with R7 providing the series current limit.
*   - The LM393 comparator is validly modeled with behavioral circuitry plus an NPN open-collector output stage.
*   - The changing light/shadow condition is validly modeled by the PULSE source VLUX.
* overall_comment: This SPICE netlist is broadly faithful to the BOM and wiring and is usable as a didactic example of a shadow-triggered visual alarm. The divider, RC filter, adjustable reference, hysteresis, open-collector pull-up, and active-low LED wiring all match the intended circuit. The main caveat is pedagogical: the LM393 is only behaviorally approximated, and R2 is represented by a fixed chosen value rather than an interactively adjustable potentiometer position. Before classroom use, I would explain the active-low output, the delayed switching caused by R3-C1, and the role of positive feedback R5 in shifting VREF slightly between output states.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation is consistent with a shadow detector. In bright condition, VA and VB are high, VB is above VREF, the LM393 output transistor is off, and VOUT stays high at about 4.89 V so the LED is off. After the light-to-shadow transition, VA drops, VB falls slowly because of the R3-C1 filter, and when VB crosses below VREF at about 0.168 s, VOUT is pulled low to about 18 mV and the LED turns on. When light returns, VB rises slowly again, so the alert remains on for a while before resetting, consistent with RC filtering and hysteresis.

Common mistakes and how to avoid them

  1. Connecting the LED directly to the comparator output without a resistor
  2. Always use R7 in series with D1 to limit current.

  3. Forgetting that the LM393 output is open collector

  4. Add R6 from VCC to VOUT, or the output will not produce a valid high level.

  5. Using no hysteresis near the threshold

  6. Keep R5 installed so the LED does not chatter when the light level is close to the switching point.

Troubleshooting

  • Symptom: LED never turns on
  • Cause: VREF is set too low or the LDR divider range is too small.
  • Fix: Adjust R4, then verify that VA and VB really change under a shadow.

  • Symptom: LED is always on

  • Cause: VREF is too high, or the LDR is wired incorrectly.
  • Fix: Lower VREF with R4 and confirm R1 is between VCC and VA.

  • Symptom: LED flickers near the switching point

  • Cause: insufficient filtering or hysteresis.
  • Fix: Increase C1 or reduce R5 moderately to strengthen hysteresis.

  • Symptom: Output voltage at VOUT never rises

  • Cause: missing or incorrect pull-up resistor R6.
  • Fix: Confirm R6 is connected between VCC and VOUT.

  • Symptom: Response is too slow

  • Cause: RC filter too large.
  • Fix: Reduce C1 or R3 to shorten the response time.

Possible improvements and extensions

  1. Add a buzzer output
  2. Connect a transistor driver to VOUT so the same shadow event activates both an LED and a buzzer for stronger alerting.

  3. Use a dual-threshold window

  4. Add a second comparator to detect both excessive darkness and excessive brightness, useful for light-condition monitoring rather than only shadow detection.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the main purpose of adding hysteresis to the shadow detector comparator?




Question 2: Which component is the key energy-storage element in the RC low-pass filter that stabilizes brief shadow events?




Question 3: What typically happens to the voltage at VA when the light level changes?




Question 4: Why does the voltage at VB change more slowly than VA?




Question 5: What is the role of U1 in the circuit?




Question 6: When is LED D1 intended to turn on in this design?




Question 7: Which component is paired with the LDR to form the sensor voltage divider?




Question 8: What is a stated useful application of this shadow detector?




Question 9: What hysteresis range is mentioned for avoiding repeated switching?




Question 10: For what audience is this project mainly intended?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Base Biasing with Resistor

Base Biasing with Resistor prototype (Maker Style)

Level: Medium — Calculate and verify a base resistor to switch an NPN transistor safely from a logic output.

Objective and use case

You will build a simple transistor switch where a 5 V logic output drives an NPN transistor through a base resistor. The goal is to choose the resistor so the transistor turns the load on reliably without exceeding the allowed logic output current.

Why it is useful:
– To drive a relay module, buzzer, or small lamp from a microcontroller pin.
– To control loads that require more current than a logic output can supply directly.
– To protect a logic output from excessive base current.
– To learn how to verify transistor saturation with real voltage and current measurements.

Expected outcome:
– When the logic output is LOW, the transistor remains OFF and the load is de-energized.
– When the logic output is HIGH, the transistor turns ON and the load current is about 20 mA.
– Base current stays below the logic output limit, target about 4.3 mA.
– Measured base-emitter voltage is about 0.7 V when ON.
– Measured collector-emitter voltage is low in saturation, typically below 0.2 V.

Target audience and level: Students with basic DC circuit and transistor knowledge.

Materials

  • V1: 5 V DC supply
  • VSIG: 0 V / 5 V logic source, function: control signal for transistor base
  • R1: 1 kΩ resistor, function: base current limiting
  • R2: 150 Ω resistor, function: load current limiting for LED branch
  • D1: red LED, function: visible collector load indicator
  • Q1: 2N2222 NPN transistor, function: low-side switch
  • M1: digital multimeter, function: voltage and current measurements
  • M2: optional second multimeter, function: simultaneous current check

Wiring guide

Use these node names: VCC, 0, VIN, VB, VC.

  • V1 connects between VCC and 0.
  • VSIG connects between VIN and 0.
  • R1 connects between VIN and VB.
  • Q1 collector connects to VC.
  • Q1 base connects to VB.
  • Q1 emitter connects to 0.
  • R2 connects between VCC and the anode node of D1.
  • D1 anode connects to R2; D1 cathode connects to VC.

Practical design values:
– Load current target: about Ic = (5 V - 2.0 V - 0.2 V) / 150 Ω ≈ 18.7 mA
– Forced gain for saturation: use β_forced ≈ 10
– Required base current: Ib ≈ Ic / 10 ≈ 1.9 mA
– Base resistor estimate: R1 ≈ (5 V - 0.7 V) / 1.9 mA ≈ 2.26 kΩ

To make switching more robust, choose a lower standard value:
– Selected R1 = 1 kΩ
– Expected base current: Ib ≈ (5 V - 0.7 V) / 1 kΩ ≈ 4.3 mA

This value is suitable only if the logic output can safely source at least 4.3 mA.

Conceptual block diagram

Conceptual block diagram — Base-biased NPN switch
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Practical case: Base Biasing with Resistor

Power / load path:
[ V1: 5 V DC Supply ] --(VCC)--> [ R2: 150 ohm ] --(LED current limit)--> [ D1: Red LED ] --(cathode at VC)--> [ Q1:C 2N2222 ]
[ Q1:C 2N2222 ] --(collector-emitter path)--> [ Q1:E 2N2222 ] --(0 / GND)--> [ V1: 0 V ]

Control / base path:
[ VSIG: 0/5 V Logic Source ] --(VIN)--> [ R1: 1 kohm ] --(VB)--> [ Q1:B 2N2222 ]
[ Q1:B 2N2222 ] --(base-emitter junction)--> [ Q1:E 2N2222 ] --(0 / GND)--> [ VSIG: 0 V ]

Node labels:
[ VIN ] --> [ R1 ] --> [ VB ] --> [ Q1:B ]
[ VCC ] --> [ R2 ] --> [ D1 Anode ]
[ D1 Cathode ] --> [ VC ] --> [ Q1:C ]
[ Q1:E ] --> [ 0 / GND ]

Optional measurements:
[ M1 DMM ] --(measure V_B or V_C vs 0)--> [ VB / VC ] --> [ 0 / GND ]
[ M2 DMM ] --(current mode, inserted in series where needed)--> [ Base path or Load path ]
Electrical Schematic

Electrical diagram

Electrical diagram for Practical case: Base biasing with resistor
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

  1. Power-off check
  2. Verify all connections before applying power.
  3. Confirm Q1 emitter goes to 0.
  4. Confirm R1 is in series between VIN and VB.

  5. OFF-state test

  6. Set VSIG = 0 V.
  7. Measure Vb from VB to 0: expected near 0 V.
  8. Measure Vce from VC to 0: expected near 5 V.
  9. Observe D1: it should be OFF.
  10. Measure Ib: expected approximately 0 mA.
  11. Measure Ic: expected approximately 0 mA.

  12. ON-state test

  13. Set VSIG = 5 V.
  14. Measure Vb: expected about 0.7 V.
  15. Measure Vbe: expected about 0.65 V to 0.8 V.
  16. Measure Ib by placing the meter in series with R1: expected about 4.3 mA.
  17. Measure Vc: expected low, typically below 0.2 V to 0.3 V.
  18. Measure Vce: expected below 0.2 V if saturation is achieved.
  19. Measure Ic in series with the collector path: expected about 18 mA to 20 mA.
  20. Observe D1: it should be clearly ON.

  21. Logic output safety check

  22. Compare the measured Ib with the maximum source current allowed by the logic output.
  23. If the logic output rating is less than the measured base current, increase R1.

  24. Verification calculation

  25. Compute measured gain in switching mode: Ic / Ib.
  26. Example with measured values: 19 mA / 4.3 mA ≈ 4.4
  27. This is consistent with saturated switching, where the transistor is intentionally overdriven.

  28. Pass criteria

  29. Ib does not exceed the logic output limit.
  30. D1 turns fully ON at logic HIGH and fully OFF at logic LOW.
  31. Vce in ON state is low enough to confirm saturation.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Base Biasing with Resistor
.width out=256

V1 VCC 0 DC 5
VSIG VIN 0 PULSE(0 5 10m 1u 1u 245m 1s)

R1 VIN VB 1k
R2 VCC VLED 150
D1 VLED VC DRED
Q1 VC VB 0 Q2N2222

* Optional multimeter loading approximations (high impedance voltmeters)
RM1 VC 0 10Meg
RM2 VB 0 10Meg

* Alias nodes for guaranteed logging
VALIASIN IN VIN 0
VALIASOUT OUT VC 0

.model DRED D(IS=1e-18 N=2.0 RS=10 CJO=20p VJ=0.75 M=0.5 TT=50n BV=5 IBV=10u)
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Base Biasing with Resistor
.width out=256

V1 VCC 0 DC 5
VSIG VIN 0 PULSE(0 5 10m 1u 1u 245m 1s)

R1 VIN VB 1k
R2 VCC VLED 150
D1 VLED VC DRED
Q1 VC VB 0 Q2N2222

* Optional multimeter loading approximations (high impedance voltmeters)
RM1 VC 0 10Meg
RM2 VB 0 10Meg

* Alias nodes for guaranteed logging
VALIASIN IN VIN 0
VALIASOUT OUT VC 0

.model DRED D(IS=1e-18 N=2.0 RS=10 CJO=20p VJ=0.75 M=0.5 TT=50n BV=5 IBV=10u)
.model Q2N2222 NPN(IS=1e-14 BF=200 VAF=100 IKF=0.1 ISE=1e-13 NE=1.5 BR=5 NR=1.0 VAR=25 IKR=0.05
+ RC=0.5 RE=0.2 RB=10 CJE=25p VJE=0.75 MJE=0.33 TF=0.4n XTF=2 CJC=8p VJC=0.55 MJC=0.33 TR=50n)

.save V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.op
.print op V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.tran 0.1m 250m
.print tran V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (2528 rows)
Index   time            v(in)           v(out)          v(vin)          v(vc)           v(vb)           v(vled)         v1#branch       vsig#branch
0	0.000000e+00	0.000000e+00	3.623103e+00	0.000000e+00	3.623103e+00	3.624741e-09	4.999946e+00	-3.62318e-07	3.624741e-12
1	1.000000e-06	0.000000e+00	3.623104e+00	0.000000e+00	3.623104e+00	6.699379e-09	4.999946e+00	-3.62321e-07	6.699379e-12
2	2.000000e-06	0.000000e+00	3.623105e+00	0.000000e+00	3.623105e+00	6.506970e-09	4.999946e+00	-3.62321e-07	6.506970e-12
3	4.000000e-06	0.000000e+00	3.623106e+00	0.000000e+00	3.623106e+00	5.984372e-09	4.999946e+00	-3.62320e-07	5.984372e-12
4	8.000000e-06	0.000000e+00	3.623108e+00	0.000000e+00	3.623108e+00	5.188535e-09	4.999946e+00	-3.62320e-07	5.188535e-12
5	1.600000e-05	0.000000e+00	3.623110e+00	0.000000e+00	3.623110e+00	4.293865e-09	4.999946e+00	-3.62319e-07	4.293865e-12
6	3.200000e-05	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.693772e-09	4.999946e+00	-3.62318e-07	3.693772e-12
7	6.400000e-05	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.610539e-09	4.999946e+00	-3.62318e-07	3.610539e-12
8	1.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.631021e-09	4.999946e+00	-3.62318e-07	3.631021e-12
9	2.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.621414e-09	4.999946e+00	-3.62318e-07	3.621414e-12
10	3.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.626121e-09	4.999946e+00	-3.62318e-07	3.626121e-12
11	4.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.624676e-09	4.999946e+00	-3.62318e-07	3.624676e-12
12	5.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.623957e-09	4.999946e+00	-3.62318e-07	3.623957e-12
13	6.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.626113e-09	4.999946e+00	-3.62318e-07	3.626113e-12
14	7.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.623011e-09	4.999946e+00	-3.62318e-07	3.623011e-12
15	8.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.626745e-09	4.999946e+00	-3.62318e-07	3.626745e-12
16	9.280000e-04	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.622584e-09	4.999946e+00	-3.62318e-07	3.622584e-12
17	1.028000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.627045e-09	4.999946e+00	-3.62318e-07	3.627045e-12
18	1.128000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.622367e-09	4.999946e+00	-3.62318e-07	3.622367e-12
19	1.228000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.627168e-09	4.999946e+00	-3.62318e-07	3.627168e-12
20	1.328000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.622305e-09	4.999946e+00	-3.62318e-07	3.622305e-12
21	1.428000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.627229e-09	4.999946e+00	-3.62318e-07	3.627229e-12
22	1.528000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.622257e-09	4.999946e+00	-3.62318e-07	3.622257e-12
23	1.628000e-03	0.000000e+00	3.623112e+00	0.000000e+00	3.623112e+00	3.627228e-09	4.999946e+00	-3.62318e-07	3.627228e-12
... (2504 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Base Biasing with Resistor
.width out=256

V1 VCC 0 DC 5
VSIG VIN 0 PULSE(0 5 10m 1u 1u 245m 1s)

R1 VIN VB 1k
R2 VCC VLED 150
D1 VLED VC DRED
Q1 VC VB 0 Q2N2222

* Optional multimeter loading approximations (high impedance voltmeters)
RM1 VC 0 10Meg
RM2 VB 0 10Meg

* Alias nodes for guaranteed logging
VALIASIN IN VIN 0
VALIASOUT OUT VC 0

.model DRED D(IS=1e-18 N=2.0 RS=10 CJO=20p VJ=0.75 M=0.5 TT=50n BV=5 IBV=10u)
.model Q2N2222 NPN(IS=1e-14 BF=200 VAF=100 IKF=0.1 ISE=1e-13 NE=1.5 BR=5 NR=1.0 VAR=25 IKR=0.05
+ RC=0.5 RE=0.2 RB=10 CJE=25p VJE=0.75 MJE=0.33 TF=0.4n XTF=2 CJC=8p VJC=0.55 MJC=0.33 TR=50n)

.save V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.op
.print op V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.tran 0.1m 250m
.print tran V(IN) V(OUT) V(VIN) V(VC) V(VB) V(VLED) I(V1) I(VSIG)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Using no base resistor
  2. Error: connecting the logic output directly to the transistor base.
  3. Result: excessive base current and possible damage to the logic output.
  4. Fix: always place R1 between VIN and VB.

  5. Choosing a base resistor that is too large

  6. Error: using R1 = 10 kΩ without checking current.
  7. Result: base current may be too low, so the transistor may not saturate.
  8. Fix: calculate Ib from the load current and use a forced gain of about 10 for switching.

  9. Reversing transistor terminals

  10. Error: swapping collector and emitter.
  11. Result: abnormal voltages, weak load current, or no switching.
  12. Fix: confirm the 2N2222 pinout from its datasheet before wiring.

Troubleshooting

  • Symptom: LED never turns ON
  • Cause: VSIG is not reaching 5 V, or Q1 base is not connected through R1.
  • Fix: measure VIN and VB; verify R1 continuity and transistor pinout.

  • Symptom: LED is dim

  • Cause: transistor is not saturated because R1 is too large.
  • Fix: reduce R1 after checking the logic output current limit.

  • Symptom: Logic output voltage drops when ON

  • Cause: base current demand is too high for the logic source.
  • Fix: increase R1 or use a transistor driver stage.

  • Symptom: LED stays ON all the time

  • Cause: wrong wiring at the collector node or unintended base bias.
  • Fix: check that Q1 emitter is at 0 and that VIN actually goes to 0 V in the LOW state.

  • Symptom: Measured Vce is high when ON

  • Cause: insufficient base current or incorrect collector load wiring.
  • Fix: verify Ib, recalculate R1, and check R2 and D1 orientation.

Possible improvements and extensions

  • Add a 10 kΩ pull-down resistor from VB to 0 so the transistor stays OFF if the logic source becomes disconnected or high-impedance.
  • Replace the LED load with a relay coil and add a flyback diode across the coil to study transistor switching with inductive loads.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the main purpose of the base resistor in the 5 V logic-driven NPN switch?




Question 2: According to the article, what load current is expected when the transistor is ON?




Question 3: What is the target base current mentioned for reliable switching?




Question 4: If the logic output is HIGH at 5 V and the base-emitter voltage is about 0.7 V, what voltage is approximately across the 1 kΩ base resistor?




Question 5: Using the article values, what base current flows through a 1 kΩ resistor when driven from 5 V with V_BE about 0.7 V?




Question 6: Why is a forced beta of around 5 reasonable here?




Question 7: What collector-emitter voltage indicates the transistor is in saturation according to the article?




Question 8: What should happen when the logic output is LOW?




Question 9: Which transistor is used as the low-side switch in this example?




Question 10: If a microcontroller pin can safely supply up to 5 mA, is the article's target base current acceptable?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Light switching from two points

Light switching from two points prototype (Maker Style)

Level: Medium. Implement an XOR logic function using universal NAND gates to control a light source from two independent locations.

Objective and use case

In this case, you will build a digital logic circuit that replicates a residential 2-way switching system (hallway light) using a single 74HC00 Quad NAND Gate IC. By combining four NAND gates, you will synthesize the Exclusive-OR (XOR) function, proving that NAND gates are «universal» building blocks.

Why it is useful:
* Residential wiring simulation: Demonstrates how two switches can independently toggle a single load (hallway/staircase logic).
* Digital Logic Synthesis: Teaches how to build complex logic (XOR) from basic universal gates (NAND).
* Arithmetic Circuits: This specific XOR topology is the fundamental component of a digital «Half-Adder» used in CPU ALUs.
* Error Detection: XOR logic is used to calculate parity bits for data transmission.

Expected outcome:
* State 00: When both switches are OFF, the LED is OFF.
* State 01/10: When only one switch is ON, the LED is ON (High logic level > 3.5 V).
* State 11: When both switches are ON, the LED is OFF.
* Universality: Successful demonstration that 4 NAND gates = 1 XOR gate.

Target audience: Electronics students and hobbyists familiar with basic logic gates.

Materials

  • V1: 5 V DC power supply, function: Main circuit power.
  • U1: 74HC00, function: Quad 2-input NAND gate IC.
  • S1: SPST Switch, function: Input A (Switch 1).
  • S2: SPST Switch, function: Input B (Switch 2).
  • R1: 10 kΩ resistor, function: Pull-down for Input A.
  • R2: 10 kΩ resistor, function: Pull-down for Input B.
  • R3: 330 Ω resistor, function: LED current limiting.
  • D1: Red LED, function: Output indicator (Light).

Pin-out of the IC used

Selected Chip: 74HC00 (Quad 2-Input NAND Gate)

Pin Name Logic Function Connection in this case
1 1 A Input Gate 1 Connect to Node INPUT_A
2 1B Input Gate 1 Connect to Node INPUT_B
3 1Y Output Gate 1 Internal Node NAND_1_OUT
4 2 A Input Gate 2 Connect to Node INPUT_A
5 2B Input Gate 2 Connect to Node NAND_1_OUT
6 2Y Output Gate 2 Internal Node NAND_2_OUT
7 GND Ground Connect to Node 0 (GND)
8 3Y Output Gate 3 Internal Node NAND_3_OUT
9 3 A Input Gate 3 Connect to Node NAND_1_OUT
10 3B Input Gate 3 Connect to Node INPUT_B
11 4Y Output Gate 4 Connect to Node FINAL_OUT
12 4 A Input Gate 4 Connect to Node NAND_2_OUT
13 4B Input Gate 4 Connect to Node NAND_3_OUT
14 VCC Power Supply Connect to Node VCC (+5 V)

Wiring guide

  • V1: Connect positive terminal to node VCC and negative terminal to node 0.
  • U1 (Power): Connect Pin 14 to VCC and Pin 7 to 0.
  • S1: Connect one side to VCC and the other to node INPUT_A.
  • R1: Connect between node INPUT_A and node 0.
  • S2: Connect one side to VCC and the other to node INPUT_B.
  • R2: Connect between node INPUT_B and node 0.
  • U1 (Gate 1): Connect Pin 1 to INPUT_A, Pin 2 to INPUT_B. Pin 3 is node NAND_1_OUT.
  • U1 (Gate 2): Connect Pin 4 to INPUT_A, Pin 5 to NAND_1_OUT. Pin 6 is node NAND_2_OUT.
  • U1 (Gate 3): Connect Pin 10 to INPUT_B, Pin 9 to NAND_1_OUT. Pin 8 is node NAND_3_OUT.
  • U1 (Gate 4): Connect Pin 12 to NAND_2_OUT, Pin 13 to NAND_3_OUT. Pin 11 is node FINAL_OUT.
  • R3: Connect between node FINAL_OUT and the Anode of D1.
  • D1: Connect the Cathode to node 0.

Conceptual block diagram

Conceptual block diagram — 74HC00 NAND gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Light switching from two points (XOR Logic)

INPUT STAGE                  LOGIC PROCESSING (74HC00)                  OUTPUT STAGE
(User Controls)              (NAND-based XOR Circuit)                   (Indicator)

                                     (Pin 4)
VCC --> [ S1 ] --(Node A)----------> [ U1:Gate 2 ] --(NAND_2)--\
          |                          (Pin 5,6)                  \
       [ R1 ]                            ^                       \
          v                              |                        \
         GND                        (NAND_1_OUT)                   \
                                         |                          \
                                         |                           \
(Node A) & (Node B) -----------> [ U1:Gate 1 ]                        --> [ U1:Gate 4 ] --(FINAL)--> [ R3 ] --> [ D1: LED ] --> GND
                                 (Pin 1,2->3)                        /    (Pin 12,13->11)
                                         |                          /
                                         |                         /
                                    (NAND_1_OUT)                  /
          ^                              |                       /
       [ R2 ]                            v                      /
          |                          (Pin 9)                   /
VCC --> [ S2 ] --(Node B)----------> [ U1:Gate 3 ] --(NAND_3)-/
                                     (Pin 10,8)
Electrical Schematic

Electrical diagram

Electrical diagram for case: Light switching from two points
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Truth table (Synthesized XOR)

Switch A (S1) Switch B (S2) LED State (D1) Logic Function
0 (OFF) 0 (OFF) OFF (0) No active input
0 (OFF) 1 (ON) ON (1) Inputs differ
1 (ON) 0 (OFF) ON (1) Inputs differ
1 (ON) 1 (ON) OFF (0) Inputs match

Measurements and tests

  1. Initial State Check: Ensure both S1 and S2 are open. Measure voltage at Pin 11 (FINAL_OUT). It should be < 0.5 V (Logic 0). D1 should be dark.
  2. First Switch Toggle: Close S1 only. Measure voltage at Pin 11. It should be close to 5 V (Logic 1). D1 should light up.
  3. Second Switch Toggle: Open S1 and close S2. Observe D1. It should light up again (Logic 1).
  4. Collision Check: Close both S1 and S2 simultaneously. Measure voltage at Pin 3 (NAND_1_OUT). Since both inputs are High, Pin 3 must be Low. Consequently, Pin 11 (FINAL_OUT) should go Low, turning D1 OFF.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Light switching from two points
* Title: Light switching from two points

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================

* Simple LED Model
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=10p BV=5 IBV=10u)

* Voltage Controlled Switch Model for Buttons
* Vt=2.5V threshold, Ron=1 ohm, Roff=10Meg ohm
.model SW_PUSH SW(Vt=2.5 Ron=1 Roff=10Meg)

* ==============================================================================
* MAIN CIRCUIT
* ==============================================================================

* --- Power Supply ---
* V1: 5 V DC power supply
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Light switching from two points
* Title: Light switching from two points

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================

* Simple LED Model
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=10p BV=5 IBV=10u)

* Voltage Controlled Switch Model for Buttons
* Vt=2.5V threshold, Ron=1 ohm, Roff=10Meg ohm
.model SW_PUSH SW(Vt=2.5 Ron=1 Roff=10Meg)

* ==============================================================================
* MAIN CIRCUIT
* ==============================================================================

* --- Power Supply ---
* V1: 5 V DC power supply
V1 VCC 0 DC 5

* --- Input A (Switch 1) ---
* Simulating physical switch S1 connecting VCC to INPUT_A
* Controlled by V_ACT_S1 (User pressing the button)
* Timing: Period 100us, Width 50us (Toggles faster)
V_ACT_S1 S1_CTRL 0 PULSE(0 5 0 1u 1u 50u 100u)
S1 VCC INPUT_A S1_CTRL 0 SW_PUSH

* R1: 10 kΩ pull-down for Input A
R1 INPUT_A 0 10k

* --- Input B (Switch 2) ---
* Simulating physical switch S2 connecting VCC to INPUT_B
* Controlled by V_ACT_S2 (User pressing the button)
* Timing: Period 200us, Width 100us (Toggles slower)
V_ACT_S2 S2_CTRL 0 PULSE(0 5 0 1u 1u 100u 200u)
S2 VCC INPUT_B S2_CTRL 0 SW_PUSH

* R2: 10 kΩ pull-down for Input B
R2 INPUT_B 0 10k

* --- Logic IC U1: 74HC00 ---
* Quad 2-input NAND gate IC
* Pin connections per Wiring Guide:
* P1=INPUT_A, P2=INPUT_B, P3=NAND_1_OUT
* P4=INPUT_A, P5=NAND_1_OUT, P6=NAND_2_OUT
* P7=0 (GND)
* P8=NAND_3_OUT, P9=NAND_1_OUT, P10=INPUT_B
* P11=FINAL_OUT, P12=NAND_2_OUT, P13=NAND_3_OUT
* P14=VCC
XU1 INPUT_A INPUT_B NAND_1_OUT INPUT_A NAND_1_OUT NAND_2_OUT 0 NAND_3_OUT NAND_1_OUT INPUT_B FINAL_OUT NAND_2_OUT NAND_3_OUT VCC 74HC00

* --- Output Stage ---
* R3: 330 Ω resistor
R3 FINAL_OUT LED_NODE 330

* D1: Red LED
D1 LED_NODE 0 DLED

* ==============================================================================
* SUBCIRCUITS
* ==============================================================================

* Subcircuit for 74HC00 Quad 2-Input NAND Gate
* Uses continuous behavioral sources for robust convergence
* Pinout: 1=1A, 2=1B, 3=1Y, 4=2A, 5=2B, 6=2Y, 7=GND, 8=3Y, 9=3A, 10=3B, 11=4Y, 12=4A, 13=4B, 14=VCC
.subckt 74HC00 1 2 3 4 5 6 7 8 9 10 11 12 13 14
    * Gate 1 (1,2 -> 3)
    * Logic: Vout = VCC * (1 - (High(A) * High(B)))
    Bg1 3 7 V={V(14,7)*(1-(1/(1+exp(-50*(V(1,7)-2.5))))*(1/(1+exp(-50*(V(2,7)-2.5)))))}

    * Gate 2 (4,5 -> 6)
    Bg2 6 7 V={V(14,7)*(1-(1/(1+exp(-50*(V(4,7)-2.5))))*(1/(1+exp(-50*(V(5,7)-2.5)))))}

    * Gate 3 (9,10 -> 8)
    Bg3 8 7 V={V(14,7)*(1-(1/(1+exp(-50*(V(9,7)-2.5))))*(1/(1+exp(-50*(V(10,7)-2.5)))))}

    * Gate 4 (12,13 -> 11)
    Bg4 11 7 V={V(14,7)*(1-(1/(1+exp(-50*(V(12,7)-2.5))))*(1/(1+exp(-50*(V(13,7)-2.5)))))}
.ends

* ==============================================================================
* ANALYSIS COMMANDS
* ==============================================================================

.op
.tran 1u 500u

* Print critical nodes including Inputs and the Output driving the LED
.print tran V(INPUT_A) V(INPUT_B) V(FINAL_OUT) V(LED_NODE)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation confirms the XOR logic behavior required for 2-way switching. When inputs differ (e.g., t=51us: A=0, B=1 -> Out=5V; t=101us: A=1, B=1 -> Out=0V; t=180us: A=1, B=0 -> Out=5V), the LED is ON (approx 1.88V drop). When inputs match (0,0 or 1,1), the output is near 0V.
* bom_vs_spice equivalences ignored:
*   - Physical switches S1 and S2 are modeled as voltage-controlled switches (SW_PUSH) driven by PULSE sources (V_ACT_S1, V_ACT_S2) to simulate user interaction.
*   - The 74HC00 Quad NAND IC is modeled as a behavioral subcircuit using mathematical expressions for logic gates.
*   - The LED D1 is modeled as a generic diode DLED with specific parameters.
* overall_comment: The circuit is a classic XOR implementation using four NAND gates, correctly wired to simulate a 2-way light switch (staircase switch). The SPICE netlist accurately represents the BOM and wiring guide. The simulation results perfectly match the provided truth table: the LED lights up only when the switch states are different.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation confirms the XOR logic behavior required for 2-way switching. When inputs differ (e.g., t=51us: A=0, B=1 -> Out=5V; t=101us: A=1, B=1 -> Out=0V; t=180us: A=1, B=0 -> Out=5V), the LED is ON (approx 1.88V drop). When inputs match (0,0 or 1,1), the output is near 0V.
Show raw data table (773 rows)
Index   time            v(input_a)      v(input_b)      v(final_out)    v(led_node)
0	0.000000e+00	4.995005e-03	4.995005e-03	-3.70921e-68	-1.32951e-36
1	1.000000e-08	4.995005e-03	4.995005e-03	-3.70921e-68	-3.37339e-37
2	2.000000e-08	4.995005e-03	4.995005e-03	-3.70921e-68	1.661518e-37
3	4.000000e-08	4.995005e-03	4.995005e-03	-3.70921e-68	2.976605e-37
4	8.000000e-08	4.995005e-03	4.995005e-03	-3.70921e-68	8.146600e-38
5	1.600000e-07	4.995005e-03	4.995005e-03	-3.70921e-68	-2.74917e-38
6	3.200000e-07	4.995005e-03	4.995005e-03	-3.70921e-68	-1.00046e-38
7	3.562500e-07	4.995005e-03	4.995005e-03	-3.70921e-68	-9.54478e-40
8	4.196875e-07	4.995005e-03	4.995005e-03	-3.70921e-68	1.440911e-39
9	4.372461e-07	4.995005e-03	4.995005e-03	-3.70921e-68	5.873353e-40
10	4.679736e-07	4.995005e-03	4.995005e-03	-3.70921e-68	-1.64244e-40
11	5.019934e-07	4.999500e+00	4.999500e+00	-3.70921e-68	5.471353e-16
12	5.700330e-07	4.999500e+00	4.999500e+00	-3.70921e-68	1.883035e-16
13	7.061121e-07	4.999500e+00	4.999500e+00	-3.70921e-68	-1.89304e-16
14	9.782703e-07	4.999500e+00	4.999500e+00	-3.70921e-68	1.713539e-16
15	1.000000e-06	4.999500e+00	4.999500e+00	-3.70921e-68	-8.76370e-17
16	1.043459e-06	4.999500e+00	4.999500e+00	-3.70921e-68	2.969253e-18
17	1.130378e-06	4.999500e+00	4.999500e+00	-3.70921e-68	1.336375e-17
18	1.304216e-06	4.999500e+00	4.999500e+00	-3.70921e-68	1.285658e-18
19	1.651892e-06	4.999500e+00	4.999500e+00	-3.70921e-68	-4.38731e-19
20	2.347244e-06	4.999500e+00	4.999500e+00	-3.70921e-68	-3.76487e-20
21	3.347244e-06	4.999500e+00	4.999500e+00	-3.70921e-68	3.641502e-21
22	4.347244e-06	4.999500e+00	4.999500e+00	-3.70921e-68	3.034717e-22
23	5.347244e-06	4.999500e+00	4.999500e+00	-3.70921e-68	-2.04956e-23
... (749 more rows) ...

Common mistakes and how to avoid them

  1. Floating Inputs: Forgetting R1 or R2 causes the inputs to «float,» often reading as High due to electromagnetic noise. Solution: Always ensure inputs are pulled to Ground when the switch is open.
  2. Incorrect Gate Feedback: Wiring Pin 3 output to the wrong inputs on Gates 2 or 3 destroys the logic. Solution: Double-check that the output of the first NAND (Pin 3) connects to BOTH the second (Pin 5) and third (Pin 9) gates.
  3. Forgetting Power: Logic chips do not work passively. Solution: Verify 5 V on Pin 14 and continuity to Ground on Pin 7 before inserting signals.

Troubleshooting

  • Symptom: LED is always ON, regardless of switch position.
    • Cause: Wiring error at the final NAND gate (Gate 4) or output shorted to VCC.
    • Fix: Check connections at Pins 11, 12, and 13. Ensure Pin 11 is not touching the positive rail.
  • Symptom: LED behaves like an OR gate (stays ON when both switches are ON).
    • Cause: The first NAND gate (Gate 1) is not effectively inhibiting the signal.
    • Fix: Check continuity on Pins 1, 2, and 3. If Gate 1 output stays High when inputs are High, the XOR logic fails.
  • Symptom: Circuit works erratically when touching the wires.
    • Cause: Missing pull-down resistors (floating inputs).
    • Fix: Verify R1 and R2 are securely connected between the input pins and Ground.

Possible improvements and extensions

  1. 3-Way Switching: Add a third switch and another XOR stage (using a second 74HC00 or a 74HC86) to control the light from three locations.
  2. Comparison with Dedicated IC: Build the same circuit using a 74HC86 (Quad XOR) alongside this one to compare propagation delay and wiring complexity.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What specific real-world application does this digital logic circuit simulate?




Question 2: Which logic function is synthesized using the NAND gates in this experiment?




Question 3: Which specific Integrated Circuit (IC) is used to build this circuit?




Question 4: Why are NAND gates referred to as "universal" building blocks?




Question 5: According to the expected outcome, what is the state of the LED when only one switch is ON?




Question 6: What happens to the LED when both switches are turned ON (State 11)?




Question 7: How many NAND gates are combined to synthesize the XOR function in this topology?




Question 8: In the context of CPU ALUs, what arithmetic component is this XOR topology the fundamental part of?




Question 9: How is XOR logic utilized in data transmission applications?




Question 10: What voltage level is indicated as the threshold for a High logic level (LED ON) in this context?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Debouncing SR Latch with NAND

Debouncing SR Latch with NAND prototype (Maker Style)

Level: Medium – Build a stable memory circuit to eliminate mechanical switch noise using cross-coupled NAND gates.

Objective and use case

In this practical case, you will build a Set-Reset (SR) Latch using a 74HC00 IC. By arranging two NAND gates in a cross-coupled feedback topology, the circuit creates a bistable memory element that ignores the mechanical «bouncing» noise generated when a physical switch contacts are closed.

Why it is useful:
* Mechanical switch interfacing: Essential for reading buttons in digital systems without false triggering.
* Microcontroller interrupts: Provides a clean edge (rising/falling) to trigger hardware interrupts reliably.
* State retention: Maintains the last known state (Set or Reset) even after the input trigger is released (return to idle).
* Industrial control: Used in «Start/Stop» motor control circuits where stability is safety-critical.

Expected outcome:
* Q Output: Stays HIGH (5 V) when Set is triggered and remains HIGH until Reset is triggered.
* Q_bar Output: Always the inverse of Q (Logic LOW when Q is HIGH).
* Visual feedback: Two LEDs (Green and Red) indicating the stored state clearly.
* Noise immunity: The output transitions once cleanly, even if the switch contacts bounce multiple times in milliseconds.

Target audience and level: Electronics students and intermediate hobbyists.

Materials

  • V1: 5 V DC supply
  • U1: 74HC00 (Quad 2-Input NAND Gate)
  • SW1: SPDT (Single Pole Double Throw) switch, function: Set/Reset selector
  • R1: 10 kΩ resistor, function: pull-up for SET_N
  • R2: 10 kΩ resistor, function: pull-up for RESET_N
  • R3: 330 Ω resistor, function: LED current limiting for Q
  • R4: 330 Ω resistor, function: LED current limiting for Q_bar
  • D1: Green LED, function: Indicator for State Q (Active)
  • D2: Red LED, function: Indicator for State Q_bar (Inactive)
  • C1: 100 nF capacitor, function: decoupling for U1 power pins

Pin-out of the IC used

Chip: 74HC00 (Quad 2-Input NAND Gate)

Pin Name Logic function Connection in this case
1 1 A Input Connects to Node SET_N
2 1B Input Connects to Node Q_BAR (Feedback)
3 1Y Output Connects to Node Q
4 2 A Input Connects to Node RESET_N
5 2B Input Connects to Node Q (Feedback)
6 2Y Output Connects to Node Q_BAR
7 GND Ground Connects to Node 0
14 VCC Power Connects to Node VCC (5 V)

Wiring guide

  • Power Supply:
  • Connect V1 positive terminal to node VCC.
  • Connect V1 negative terminal to node 0 (GND).
  • Connect C1 between VCC and 0 (close to U1).
  • Connect U1 pin 14 to VCC.
  • Connect U1 pin 7 to 0.

  • Input Stage (Switch and Pull-ups):

  • Connect R1 between VCC and node SET_N.
  • Connect R2 between VCC and node RESET_N.
  • Connect SW1 Common terminal to node 0.
  • Connect SW1 Normally Open (NO) terminal to node SET_N.
  • Connect SW1 Normally Closed (NC) terminal to node RESET_N. (Note: Toggling SW1 pulls one line Low while the other stays High).

  • Logic Core (Cross-coupled NANDs):

  • Connect U1 pin 1 (1 A) to node SET_N.
  • Connect U1 pin 2 (1B) to node Q_BAR.
  • Connect U1 pin 3 (1Y) to node Q.
  • Connect U1 pin 4 (2 A) to node RESET_N.
  • Connect U1 pin 5 (2B) to node Q.
  • Connect U1 pin 6 (2Y) to node Q_BAR.

  • Output Stage (Indicators):

  • Connect R3 between node Q and D1 Anode.
  • Connect D1 Cathode to node 0.
  • Connect R4 between node Q_BAR and D2 Anode.
  • Connect D2 Cathode to node 0.

Conceptual block diagram

Conceptual block diagram — 74HC00 Feedback: Q sends state to …
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Debouncing SR Latch with NAND

      INPUT STAGE (Switch & Pull-ups)           LOGIC CORE (74HC00 Latch)               OUTPUT STAGE (Indicators)
      ================================          =========================               =========================

      [ VCC ]
         |
         V
      [ R1: 10k Pull-up ]
         |
         V
      (Node: SET_N) --------------------------> [ U1: NAND Gate A ] --(Signal: Q)-----> [ R3: 330 ] --> [ D1: Green LED ] --> GND
         ^                                      ^       |
         |                                      |       |
      [ SW1: SPDT Switch ]                      |       +--(Feedback: Q sends state to Gate B)
      (Connects GND to SET_N or RESET_N)        |
         |                                      +--(Feedback: Q_BAR maintains state of Gate A)
         v                                              |
      (Node: RESET_N) ------------------------> [ U1: NAND Gate B ] --(Signal: Q_BAR)-> [ R4: 330 ] --> [ D2: Red LED ] ----> GND
         ^
         |
      [ R2: 10k Pull-up ]
         |
         ^
         |
      [ VCC ]


      POWER & DECOUPLING:
      [ VCC ] --(Power)--> [ U1: Pin 14 ]
      [ GND ] --(Ground)--> [ U1: Pin 7 ]
      [ VCC ] --(Filter)--> [ C1: 100nF ] --> [ GND ]
Electrical Schematic

Electrical diagram

Electrical diagram for case: Debouncing SR Latch with NAND
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Truth table

The NAND SR Latch inputs are Active Low.

SET_N (Input) RESET_N (Input) Q (Output) Q_bar (Output) State Description
1 (High) 1 (High) Previous Q Previous Q_bar Hold (Memory)
0 (Low) 1 (High) 1 0 Set
1 (High) 0 (Low) 0 1 Reset
0 (Low) 0 (Low) 1 1 Invalid (Avoid)

Measurements and tests

  1. Initial Power-Up: Turn on the 5 V supply. Ensure SW1 is in one specific position.
  2. Verify Reset: Toggle SW1 to pull RESET_N Low (and SET_N High).
    • Confirm Red LED (D2, Q_bar) turns ON.
    • Confirm Green LED (D1, Q) turns OFF.
    • Measure voltage at Q: should be approx 0 V.
  3. Verify Set: Toggle SW1 to pull SET_N Low.
    • Confirm Green LED (D1, Q) turns ON.
    • Confirm Red LED (D2, Q_bar) turns OFF.
    • Measure voltage at Q: should be approx 5 V.
  4. Debounce Test: While moving the switch, observe the LEDs. They should switch states instantly without flickering, even if the switch contact is imperfect.
  5. Disconnect Test (Hold State): If you unplug the switch wires so both inputs are pulled High by R1/R2, the LEDs must maintain their last valid state.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Title: Practical case: Debouncing SR Latch with NAND
* NGSPICE Netlist
.width out=256

* --- Power Supply ---
V1 VCC 0 DC 5
C1 VCC 0 100n

* --- Input Stage (Switch and Pull-ups) ---
* R1 Pull-up for SET_N
R1 VCC SET_N 10k
* R2 Pull-up for RESET_N
R2 VCC RESET_N 10k

* --- Switch Simulation (SW1 SPDT) ---
* Control Signal Source
V_SW_CTRL CTRL 0 PULSE(0 5 100u 1u 1u 200u 600u)

* Inverted control signal for the NC contact
B_SW_INV CTRL_N 0 V=5-V(CTRL)
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

* Title: Practical case: Debouncing SR Latch with NAND
* NGSPICE Netlist
.width out=256

* --- Power Supply ---
V1 VCC 0 DC 5
C1 VCC 0 100n

* --- Input Stage (Switch and Pull-ups) ---
* R1 Pull-up for SET_N
R1 VCC SET_N 10k
* R2 Pull-up for RESET_N
R2 VCC RESET_N 10k

* --- Switch Simulation (SW1 SPDT) ---
* Control Signal Source
V_SW_CTRL CTRL 0 PULSE(0 5 100u 1u 1u 200u 600u)

* Inverted control signal for the NC contact
B_SW_INV CTRL_N 0 V=5-V(CTRL)

* Switch Models (Threshold 2.5V)
.model SW_MECH SW(Vt=2.5 Vh=0.1 Ron=0.1 Roff=100Meg)

* S1 (NO Contact): Connects SET_N to 0 when CTRL is High
S1 SET_N 0 CTRL 0 SW_MECH

* S2 (NC Contact): Connects RESET_N to 0 when CTRL_N is High (CTRL is Low)
S2 RESET_N 0 CTRL_N 0 SW_MECH

* --- Logic Core (74HC00 Quad 2-Input NAND) ---
* Subcircuit for 74HC00 using robust behavioral NAND gates
* Pinout: 1=1A, 2=1B, 3=1Y, 4=2A, 5=2B, 6=2Y, 7=GND, 14=VCC
.subckt 74HC00 1 2 3 4 5 6 7 14
    * Gate 1 (Pins 1, 2 -> Output 3)
    * Logic: NAND. Implementation: Sigmoid-based continuous function for convergence.
    * Vout = VCC * (1 - (Sigmoid(A) * Sigmoid(B)))
    B_NAND1 3 7 V=V(14) * (1 - ( (1/(1+exp(-50*(V(1)-2.5)))) * (1/(1+exp(-50*(V(2)-2.5)))) ))

    * Gate 2 (Pins 4, 5 -> Output 6)
    B_NAND2 6 7 V=V(14) * (1 - ( (1/(1+exp(-50*(V(4)-2.5)))) * (1/(1+exp(-50*(V(5)-2.5)))) ))
.ends

* --- Instantiate U1 ---
* Wiring per guide: 1=SET_N, 2=Q_BAR, 3=Q, 4=RESET_N, 5=Q, 6=Q_BAR, 7=0, 14=VCC
XU1 SET_N Q_BAR Q RESET_N Q Q_BAR 0 VCC 74HC00

* --- Output Stage (Indicators) ---
* R3 between node Q and D1 Anode
R3 Q D1_A 330
* D1 Green LED (Q Active)
D1 D1_A 0 LED_GREEN

* R4 between node Q_BAR and D2 Anode
R4 Q_BAR D2_A 330
* D2 Red LED (Q_BAR Inactive)
D2 D2_A 0 LED_RED

* LED Models
.model LED_GREEN D(Is=1e-22 Rs=5 N=1.5 Eg=2.1)
.model LED_RED D(Is=1e-22 Rs=5 N=1.5 Eg=1.8)

* --- Simulation Commands ---
.op
.tran 1u 1ms

* --- Measurements ---
* Listing SET_N (Input) and Q (Output) first
.print tran V(SET_N) V(Q) V(RESET_N) V(Q_BAR) V(CTRL)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation confirms correct SR Latch behavior. At t=0, SET_N is Low and RESET_N is High, resulting in Q=High (Set state). At t=100us, the switch toggles: SET_N goes High and RESET_N goes Low, causing Q to go Low and Q_BAR to go High (Reset state). The latch holds state correctly between transitions.
* bom_vs_spice equivalences ignored:
*   - SW1 (SPDT Switch) is modeled using a voltage-controlled switch pair (S1, S2) driven by a PULSE source (V_SW_CTRL) and its inverse.
*   - U1 (74HC00 Quad NAND) is modeled using a behavioral subcircuit with sigmoid-based voltage sources.
* overall_comment: The circuit is a textbook example of a NAND-based SR latch used for switch debouncing. The SPICE implementation faithfully follows the wiring guide, using a clever behavioral model for the 74HC00 and a dual-switch setup to simulate the SPDT action. The transient analysis clearly demonstrates the Set and Reset actions corresponding to the switch position, matching the provided truth table perfectly.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation confirms correct SR Latch behavior. At t=0, SET_N is Low and RESET_N is High, resulting in Q=High (Set state). At t=100us, the switch toggles: SET_N goes High and RESET_N goes Low, causing Q to go Low and Q_BAR to go High (Reset state). The latch holds state correctly between transitions.
Show raw data table (1072 rows)
Index   time            v(set_n)        v(q)            v(reset_n)      v(q_bar)        v(ctrl)
0	0.000000e+00	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
1	1.000000e-08	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
2	2.000000e-08	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
3	4.000000e-08	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
4	8.000000e-08	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
5	1.600000e-07	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
6	3.200000e-07	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
7	6.400000e-07	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
8	1.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
9	2.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
10	3.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
11	4.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
12	5.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
13	6.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
14	7.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
15	8.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
16	9.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
17	1.028000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
18	1.128000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
19	1.228000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
20	1.328000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
21	1.428000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
22	1.528000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
23	1.628000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
... (1048 more rows) ...

Common mistakes and how to avoid them

  1. Leaving inputs floating: If you remove the switch and don’t have resistors R1/R2, the inputs float, causing unpredictable oscillation. Solution: Always use pull-up resistors (10 kΩ) on NAND latch inputs.
  2. Confusing Active Low vs. Active High: Users often expect «1» to set the latch. A NAND latch sets when the input goes to «0». Solution: Remember that NAND latches trigger on ground (Low) pulses.
  3. Forbidden State: pressing two buttons simultaneously (if using buttons instead of SPDT) creates Logic 0 on both inputs, forcing both outputs High. Solution: Mechanically prevent simultaneous presses or design logic to prioritize one input.

Troubleshooting

  • Both LEDs are ON:
    • Cause: Both SET_N and RESET_N are connected to Ground (Logic 0) simultaneously.
    • Fix: Check the switch wiring; ensure you are not shorting both inputs to ground.
  • Circuit does not latch (LEDs flicker or follow switch loosely):
    • Cause: Missing feedback connection.
    • Fix: Ensure the wire from Pin 3 (Q) goes to Pin 5, and Pin 6 (Q_BAR) goes to Pin 2.
  • Chip gets hot:
    • Cause: Output short circuit or reversed supply polarity.
    • Fix: Check that R3 and R4 are present (do not connect LEDs directly to outputs) and verify Pin 14 is 5 V and Pin 7 is GND.

Possible improvements and extensions

  1. Gated SR Latch: Add two extra NAND gates (using the remaining two in the 74HC00) to add an «Enable» signal, turning it into a synchronous memory cell.
  2. Digital Counter Driver: Use the Q output to drive the clock input of a CD4017 or 74HC4017 counter, proving that the manual button press generates exactly one clean clock pulse.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: Which IC is used to build the SR Latch in this practical case?




Question 2: What specific topology is used to connect the two NAND gates to create the latch?




Question 3: What is the primary problem this circuit solves when interfacing with mechanical switches?




Question 4: According to the expected outcome, what is the state of the Q Output when Set is triggered?




Question 5: What is the relationship between the Q output and the Q_bar output?




Question 6: What happens to the stored state when the input trigger is released and returns to idle?




Question 7: Why is this circuit described as a 'bistable' memory element?




Question 8: Which of the following is a specific use case mentioned for this circuit?




Question 9: In an industrial context, what type of control circuit relies on this stability?




Question 10: What visual feedback is used in this practical case to indicate the stored state?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Linear supply voltage smoothing

Linear supply voltage smoothing prototype (Maker Style)

Level: Medium. Compare voltage ripple in a basic power supply by varying filtering capacitance under load.

Objective and use case

In this practical case, you will build a Full-Wave Bridge Rectifier circuit coupled with a selectable filter capacitor bank and a resistive load. You will analyze how the value of the filter capacitor affects the quality of the DC output by measuring the «ripple» voltage superimposed on the DC signal.

  • Audio Power Supplies: Reducing 50/60 Hz hum in amplifiers and speakers.
  • Digital Logic Power: Ensuring stable voltage levels to prevent microcontroller resets or erratic behavior.
  • Sensor Conditioning: Providing clean DC power to analog sensors for accurate readings.
  • Battery Charging: Smoothing the charging current to prolong battery life.

Expected outcome:
* Waveform Transformation: Visual observation of AC sine wave converting to pulsing DC, then to smooth DC.
* Ripple Voltage (Vripple): A high peak-to-peak ripple voltage (> 5 V) with a small capacitor (10 µF).
* Smoothing Effect: A significantly reduced ripple voltage (< 0.5 V) when switching to a large capacitor (470 µF).
* Target Audience: Intermediate electronics students and hobbyists familiar with AC/DC concepts.

Materials

  • V1: 12 V (RMS) AC transformer secondary or AC function generator (60 Hz), function: AC power source.
  • D1: 1N4007 Diode, function: Bridge rectifier top-left.
  • D2: 1N4007 Diode, function: Bridge rectifier top-right.
  • D3: 1N4007 Diode, function: Bridge rectifier bottom-left.
  • D4: 1N4007 Diode, function: Bridge rectifier bottom-right.
  • R1: 220 Ω resistor (2 Watt rating recommended), function: Static Load.
  • C1: 10 µF electrolytic capacitor (25 V or higher), function: Low-value filter.
  • C2: 470 µF electrolytic capacitor (25 V or higher), function: High-value filter.
  • S1: SPDT Switch or jumper wire, function: Selects between C1 and C2.
  • Test Equipment: Oscilloscope (preferred) or Multimeter with AC/DC measurement capabilities.

Wiring guide

Construct the circuit using the following node connections. Ensure electrolytic capacitors are connected with correct polarity (Positive terminal to V_DC, Negative terminal to 0 / GND).

  • V1 (Source): Connects between node AC_L and node AC_N.
  • D1: Anode connects to AC_L, Cathode connects to V_DC.
  • D2: Anode connects to AC_N, Cathode connects to V_DC.
  • D3: Anode connects to 0 (GND), Cathode connects to AC_L.
  • D4: Anode connects to 0 (GND), Cathode connects to AC_N.
  • R1 (Load): Connects between node V_DC and node 0 (GND).
  • C1 (Test Case A): Positive terminal to V_DC, Negative terminal to 0 (GND).
  • C2 (Test Case B): Positive terminal to V_DC, Negative terminal to 0 (GND) (Replace C1 with C2 for second test).

Conceptual block diagram

Conceptual block diagram — LM7812 Linear Power Supply Smoothing
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ INPUT SOURCE ]              [ RECTIFICATION ]                [ FILTER STAGE ]                 [ OUTPUT LOAD ]

                                                                  +-> [ Capacitor C1 ] -+
                                                                  |     (10 uF)         |
 [ AC Source V1 ] --(12 V AC)--> [ Bridge Rectifier ] --(Raw DC)-->+                     +--(V_DC)--> [ Load Resistor R1 ]
    (12 V RMS)                   [  D1, D2, D3, D4  ]              |   [ Switch S1  ]    |            (220 Ohm)
                                                                  +-> [ Capacitor C2 ] -+                |
                                                                        (470 uF)                         |
                                                                                                         |
                                                                                                         v
                                                                                                  [ Oscilloscope ]
                                                                                                  (Measure Ripple)
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Linear supply voltage smoothing
Generated from the validated SPICE netlist for this case.

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Measurements and tests

Follow these steps to validate the smoothing efficiency:

  1. Baseline (No Capacitor): Temporarily remove any capacitor. Measure V_DC with an oscilloscope. You should see a full-wave rectified signal (humps going to 0 V) at 120 Hz (or 100 Hz).
  2. Small Capacitor Test (C1 = 10 µ F):
    • Insert $C1$.
    • Measure the peak voltage (Vpeak) and the minimum valley voltage (Vmin).
    • Calculate Ripple: Vripple = Vpeak – Vmin.
    • Expectation: Significant sawtooth ripple (fast discharge).
  3. Large Capacitor Test (C2 = 470 µ F):
    • Replace $C1$ with $C2$.
    • Measure Vpeak and Vmin again.
    • Expectation: The DC line is much flatter; Vmin stays close to Vpeak.
  4. DC Average: Switch your multimeter to DC Volts. Compare the reading of $C1$ vs $C2$. The average voltage with $C2$ will be higher because the capacitor maintains the charge longer.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Linear supply voltage smoothing
*
* Description:
* This netlist simulates a full-wave bridge rectifier power supply with a 
* selectable smoothing capacitor.
* - 0ms to 100ms: C1 (10uF) is connected (High Ripple case).
* - 100ms to 200ms: C2 (470uF) is connected (Low Ripple case), simulating
*   switch S1 toggling.
*
* Connections:
* V1 (AC Source) -> Nodes AC_L, AC_N
* D1-D4 (Bridge) -> Nodes AC_L, AC_N, V_DC, 0 (GND)
* R1 (Load)      -> Nodes V_DC, 0
* S1 (Switch)    -> Modeled via S_C1 and S_C2 connecting V_DC to C1/C2
*
* -----------------------------------------------------------------------------

* --- AC Power Source ---
* 12V RMS AC, 60Hz. 
* Peak Voltage = 12 * sqrt(2) = 16.97 V
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Linear supply voltage smoothing
*
* Description:
* This netlist simulates a full-wave bridge rectifier power supply with a 
* selectable smoothing capacitor.
* - 0ms to 100ms: C1 (10uF) is connected (High Ripple case).
* - 100ms to 200ms: C2 (470uF) is connected (Low Ripple case), simulating
*   switch S1 toggling.
*
* Connections:
* V1 (AC Source) -> Nodes AC_L, AC_N
* D1-D4 (Bridge) -> Nodes AC_L, AC_N, V_DC, 0 (GND)
* R1 (Load)      -> Nodes V_DC, 0
* S1 (Switch)    -> Modeled via S_C1 and S_C2 connecting V_DC to C1/C2
*
* -----------------------------------------------------------------------------

* --- AC Power Source ---
* 12V RMS AC, 60Hz. 
* Peak Voltage = 12 * sqrt(2) = 16.97 V
V1 AC_L AC_N SIN(0 16.97 60)

* --- Bridge Rectifier (1N4007) ---
* D1: Anode=AC_L, Cathode=V_DC
D1 AC_L V_DC D1N4007
* D2: Anode=AC_N, Cathode=V_DC
D2 AC_N V_DC D1N4007
* D3: Anode=GND, Cathode=AC_L
D3 0 AC_L D1N4007
* D4: Anode=GND, Cathode=AC_N
D4 0 AC_N D1N4007

* --- Load Resistor ---
* 220 Ohm resistor across the DC output
R1 V_DC 0 220

* --- Filter Capacitors & Switching Logic ---
* We simulate the SPDT switch S1 by using two voltage-controlled switches.
* S_C1 connects V_DC to C1. S_C2 connects V_DC to C2.
* Control signals ensure only one is active at a time (break-before-make effectively).

* Capacitor C1 (10uF) path
S_C1 V_DC NET_C1 CTRL_C1 0 SW_MODEL
C1 NET_C1 0 10u

* Capacitor C2 (470uF) path
S_C2 V_DC NET_C2 CTRL_C2 0 SW_MODEL
C2 NET_C2 0 470u

* --- Control Signals (Dynamic Stimuli) ---
* CTRL_C1: Starts High (5V), goes Low (0V) at 100ms.
* Keeps C1 connected for the first 100ms.
V_CTRL_C1 CTRL_C1 0 PULSE(5 0 100m 1u 1u 1 2)

* CTRL_C2: Starts Low (0V), goes High (5V) at 100ms.
* Connects C2 for the remainder of the simulation.
V_CTRL_C2 CTRL_C2 0 PULSE(0 5 100m 1u 1u 1 2)

* --- Component Models ---
* Generic model for 1N4007 Power Diode
.model D1N4007 D(IS=7.03n RS=0.034 N=1.8 BV=1000 IBV=5u CJO=10p TT=100n)

* Ideal Switch Model (Threshold=2.5V, On-Res=10mOhm, Off-Res=100MegOhm)
.model SW_MODEL SW(Vt=2.5 Ron=0.01 Roff=100Meg)

* --- Analysis Directives ---
* Transient analysis: 200ms total time, 50us step size.
* This captures approx 6 cycles with C1 and 6 cycles with C2.
.tran 50u 200m

* Print directives for simulation log/plotting
.print tran V(V_DC) V(AC_L) V(AC_N)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (4050 rows)
Index   time            v(v_dc)         v(ac_l)         v(ac_n)
0	0.000000e+00	6.658603e-23	4.156609e-18	4.156609e-18
1	5.000000e-07	1.885342e-19	1.599385e-03	-1.59938e-03
2	1.000000e-06	6.893339e-12	3.198770e-03	-3.19877e-03
3	2.000000e-06	3.416858e-11	6.397539e-03	-6.39754e-03
4	4.000000e-06	1.718574e-10	1.279507e-02	-1.27951e-02
5	8.000000e-06	9.966330e-10	2.559012e-02	-2.55901e-02
6	1.325366e-05	3.861142e-09	4.239524e-02	-4.23952e-02
7	2.095388e-05	1.446061e-08	6.702595e-02	-6.70259e-02
8	3.129676e-05	5.099200e-08	1.001088e-01	-1.00109e-01
9	4.482862e-05	1.835180e-07	1.433897e-01	-1.43390e-01
10	6.128867e-05	6.888081e-07	1.960312e-01	-1.96031e-01
11	8.042390e-05	2.827323e-06	2.572195e-01	-2.57217e-01
12	1.019046e-04	1.303092e-05	3.258956e-01	-3.25883e-01
13	1.254895e-04	6.815023e-05	4.012964e-01	-4.01228e-01
14	1.509795e-04	4.024321e-04	4.828893e-01	-4.82487e-01
15	1.782228e-04	2.626479e-03	5.709779e-01	-5.68351e-01
16	2.071492e-04	1.723315e-02	6.705660e-01	-6.53333e-01
17	2.380619e-04	8.388777e-02	8.024272e-01	-7.18539e-01
18	2.734880e-04	2.529945e-01	9.997734e-01	-7.46779e-01
19	3.097680e-04	4.785526e-01	1.227902e+00	-7.49349e-01
20	3.521718e-04	7.463483e-01	1.496384e+00	-7.50036e-01
21	3.938443e-04	1.008721e+00	1.759554e+00	-7.50833e-01
22	4.438443e-04	1.322891e+00	2.074586e+00	-7.51694e-01
23	4.938443e-04	1.636032e+00	2.388601e+00	-7.52568e-01
... (4026 more rows) ...

Common mistakes and how to avoid them

  • Reversed Capacitor Polarity: Electrolytic capacitors will explode if connected backwards. Solution: Ensure the side marked with a stripe (negative) connects to the 0 (GND) node and the other side to the positive rectifier output.
  • Under-rated Resistor Power: A 220 Ω resistor at ~15 V DC dissipates about 1 Watt (P = V^2 / R). Using a standard 1/4 W resistor will burn it. Solution: Use a power resistor (2 W+) or increase resistance to 1 kΩ (though this reduces ripple visibility).
  • Measuring Ripple on DC Setting: A standard multimeter on DC mode averages the voltage, hiding the ripple. Solution: Use an oscilloscope for visual analysis, or set the multimeter to AC mode to measure the RMS value of the ripple component only.

Troubleshooting

  • Symptom: No output voltage at V_DC.
    • Cause: AC source not on or bridge diodes open/connected incorrectly.
    • Fix: Check V1 output and verify diode orientation (ring marks on cathodes).
  • Symptom: Ripple does not change when swapping capacitors.
    • Cause: Load resistor $R1$ is missing or open circuit. Without a load, the capacitor has no path to discharge, so voltage stays at peak regardless of capacitance.
    • Fix: Ensure $R1$ is securely connected parallel to the capacitor.
  • Symptom: Fuse blows or transformer hums loudly.
    • Cause: Short circuit in the bridge (e.g., D1 and D3 shorting AC mains).
    • Fix: Power off immediately and check wiring. Ensure AC_L and AC_N are not directly connected to 0 or each other.

Possible improvements and extensions

  1. Voltage Regulator: Add an LM7812 or LM317 linear regulator after the capacitor to see how active regulation eliminates the remaining ripple.
  2. RC Pi Filter: Add a series resistor and a second capacitor ($C-R-C$) to create a passive low-pass filter, further reducing ripple without active components (at the cost of voltage drop).

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary objective of the practical case described in the text?




Question 2: Which component is responsible for converting the AC sine wave into pulsing DC in the described circuit?




Question 3: In the context of audio power supplies, what is a key benefit of reducing voltage ripple?




Question 4: What is the expected outcome for ripple voltage when using a small capacitor (10 µF)?




Question 5: Why is stable voltage important for Digital Logic Power as mentioned in the use cases?




Question 6: According to the expected outcome, how does the waveform transform through the circuit stages?




Question 7: Based on the diagram context, what is the RMS voltage of the AC source?




Question 8: Which component is placed in parallel with the capacitor bank to simulate a load?




Question 9: What is the specific value of the larger capacitor (C2) mentioned in the diagram context?




Question 10: How does smoothing the charging current benefit battery charging applications?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: RC audio low-pass filter

RC audio low-pass filter prototype (Maker Style)

Level: Medium — Design and analyze a circuit that attenuates high frequencies using a capacitor and a resistor to verify the cutoff frequency.

Objective and use case

In this practical case, you will build a passive first-order Low-Pass Filter (LPF) using a resistor and a capacitor connected in series. You will analyze how the capacitor’s reactance changes with frequency, allowing low frequencies to pass while attenuating signals above a calculated cutoff point.

Why it is useful:
* Audio noise reduction: Removes high-frequency hiss or static from audio recordings.
* Subwoofer crossovers: Directs only low-frequency bass notes to the subwoofer driver.
* Signal conditioning: Acts as an anti-aliasing filter before Analog-to-Digital Conversion (ADC) to prevent digital artifacts.
* Power supply smoothing: Filters out high-frequency ripple noise from DC power lines.

Expected outcome:
* Passband: Frequencies below ~1 kHz retain approximately their original amplitude (Vin ≈ Vout).
* Cutoff point: At the calculated cutoff frequency (fc), the output voltage drops to approximately 70.7% of the input voltage (-3 dB).
* Stopband: Frequencies significantly higher than 1 kHz are heavily attenuated.
* Phase shift: Observe a phase lag of -45° at the cutoff frequency.

Target audience and level: Electronics students and audio enthusiasts; Level: Medium.

Materials

  • V1: AC Voltage Source (Sine Wave, 5 Vpk, tunable frequency), function: Input audio signal simulation.
  • R1: 1.6 kΩ resistor, function: Current limiting and voltage division partner.
  • C1: 100 nF capacitor (ceramic or film), function: Frequency-dependent shunt to ground.
  • Measurement Tool: Oscilloscope (Dual channel) or Bode Plotter.

Wiring guide

Construct the circuit using the following connections. Note the explicit node names for analysis.

  • V1 (Source): Connect the positive terminal to node VIN and the negative terminal to node 0 (GND).
  • R1: Connect one leg to node VIN and the other leg to node VOUT.
  • C1: Connect one leg to node VOUT and the other leg to node 0 (GND).
  • Oscilloscope Ch1: Connect probe tip to VIN and ground clip to 0.
  • Oscilloscope Ch2: Connect probe tip to VOUT and ground clip to 0.

Conceptual block diagram

Conceptual block diagram — RC Low Pass Filter
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ SIGNAL SOURCE ]               [ RC FILTER STAGE ]                 [ MEASUREMENT ]

                              +--------------------------------------> [ Scope Ch1 (Input) ]
                              |
[ V1: AC Source ] --(VIN)-->--+--> [ R1: 1.6k Resistor ] --(VOUT)-->--+--> [ Scope Ch2 (Output) ]
      (5 Vpk)                                                         |
                                                                      +--> [ C1: 100nF Cap ] --> GND
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: RC audio low-pass filter
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Follow these steps to validate the filter design (fc ≈ 1 kHz):

  1. Low Frequency Test (Passband):

    • Set V1 to 100 Hz.
    • Measure Vout peak-to-peak. It should be nearly identical to Vin (approx. 5 V).
  2. Cutoff Frequency Verification (fc):

    • Increase V1 frequency to 1 kHz.
    • Measure Vout. It should drop to approximately 0.707 × Vin (approx. 3.53 V).
    • Measure the phase difference between Ch1 and Ch2. Vout should lag Vin by roughly 45°.
  3. High Frequency Test (Stopband):

    • Set V1 to 10 kHz (one decade above cutoff).
    • Measure Vout. The amplitude should be significantly attenuated (approx. 0.5 V or -20 dB relative to input).
  4. Bode Plot Analysis (Optional):

    • If using a simulation or Bode plotter, sweep from 10 Hz to 100 kHz. Observe the «roll-off» slope of -20 dB/decade after the cutoff point.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: RC audio low-pass filter

* --- Components per BOM and Wiring Guide ---
* V1: AC Voltage Source (Sine Wave, 5 Vpk, 1kHz, AC 1V for Bode)
* Connected: Positive -> VIN, Negative -> 0 (GND)
V1 VIN 0 DC 0 AC 1 SIN(0 5 1000)

* R1: 1.6 kOhm resistor
* Connected: VIN -> VOUT
R1 VIN VOUT 1.6k

* C1: 100 nF capacitor
* Connected: VOUT -> 0 (GND)
C1 VOUT 0 100n

* --- Simulation Commands ---
* Using .control block to sequence analyses and printing correctly in ngspice
.control
    * Transient Analysis: 1kHz signal, run for 5ms
    tran 10u 5ms
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: RC audio low-pass filter

* --- Components per BOM and Wiring Guide ---
* V1: AC Voltage Source (Sine Wave, 5 Vpk, 1kHz, AC 1V for Bode)
* Connected: Positive -> VIN, Negative -> 0 (GND)
V1 VIN 0 DC 0 AC 1 SIN(0 5 1000)

* R1: 1.6 kOhm resistor
* Connected: VIN -> VOUT
R1 VIN VOUT 1.6k

* C1: 100 nF capacitor
* Connected: VOUT -> 0 (GND)
C1 VOUT 0 100n

* --- Simulation Commands ---
* Using .control block to sequence analyses and printing correctly in ngspice
.control
    * Transient Analysis: 1kHz signal, run for 5ms
    tran 10u 5ms
    * Print transient results (Oscilloscope)
    print V(VIN) V(VOUT)

    * AC Analysis: Bode Plot, 10 Hz to 100 kHz
    ac dec 10 10 100k
    * Print AC results (Bode Plotter)
    print V(VOUT)

    * Operating Point
    op
.endc

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (512 rows)
Index   time            v(vin)          v(vout)
0	0.000000e+00	0.000000e+00	0.000000e+00
1	1.000000e-07	3.141592e-03	1.962269e-06
2	1.084035e-07	3.405596e-03	2.141025e-06
3	1.252105e-07	3.933604e-03	2.526248e-06
4	1.588245e-07	4.989618e-03	3.462948e-06
5	2.260525e-07	7.101647e-03	6.001184e-06
6	3.605086e-07	1.132570e-02	1.373560e-05
7	6.294206e-07	1.977378e-02	3.982505e-05
8	1.167245e-06	3.666975e-02	1.343969e-04
9	2.242893e-06	7.046023e-02	4.923968e-04
10	4.394190e-06	1.380300e-01	1.878099e-03
11	8.696783e-06	2.730815e-01	7.282571e-03
12	1.730197e-05	5.424874e-01	2.825846e-02
13	2.730197e-05	8.535162e-01	6.884897e-02
14	3.730197e-05	1.161176e+00	1.257276e-01
15	4.730197e-05	1.464254e+00	1.976662e-01
16	5.730197e-05	1.761553e+00	2.834382e-01
17	6.730197e-05	2.051900e+00	3.818193e-01
18	7.730197e-05	2.334149e+00	4.915893e-01
19	8.730197e-05	2.607186e+00	6.115335e-01
20	9.730197e-05	2.869934e+00	7.404442e-01
21	1.073020e-04	3.121356e+00	8.771230e-01
22	1.173020e-04	3.360458e+00	1.020383e+00
23	1.273020e-04	3.586299e+00	1.169049e+00
... (488 more rows) ...

Common mistakes and how to avoid them

  1. Swapping components (High-Pass vs. Low-Pass):
    • Error: Connecting C1 in series and R1 to ground creates a High-Pass filter.
    • Solution: Ensure the Capacitor is the component connected between the output node and Ground.
  2. Ignoring Load Impedance:
    • Error: Connecting a low-impedance load (like an 8 Ω speaker) directly to VOUT.
    • Solution: This passive filter has high output impedance. Use an op-amp buffer if driving a heavy load.
  3. Using Polarized Capacitors Incorrectly:
    • Error: Using an electrolytic capacitor with reverse polarity in an AC circuit without a DC bias.
    • Solution: For pure AC audio signals, use non-polarized capacitors (ceramic, film, or bipolar electrolytic).

Troubleshooting

  • Symptom: Vout is zero at all frequencies.
    • Cause: Short circuit across C1 or open circuit at R1.
    • Fix: Check continuity across C1; if it beeps, the capacitor is shorted or the node is grounded accidentally.
  • Symptom: No attenuation occurs at high frequencies.
    • Cause: C1 is open (broken) or R1 is shorted.
    • Fix: Replace C1. Verify R1 measures 1.6 kΩ.
  • Symptom: Cutoff frequency is totally wrong.
    • Cause: Incorrect component values (e.g., using 100 pF instead of 100 nF).
    • Fix: Double-check color codes on resistors and markings on capacitors (104 code = 100 nF).

Possible improvements and extensions

  1. Second-Order Filter: Cascade two RC stages in series to achieve a steeper roll-off (-40 dB/decade) for better noise rejection.
  2. Active Low-Pass Filter: Add an Operational Amplifier (Op-Amp) to create an active filter, allowing for signal gain and preventing the load from affecting the filter’s frequency response.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the passive first-order Low-Pass Filter (LPF) described in the text?




Question 2: Which two components are connected in series to build this specific filter?




Question 3: At the cutoff frequency (fc), what percentage of the input voltage is the output voltage approximately equal to?




Question 4: What is the decibel drop at the cutoff frequency?




Question 5: Which of the following is NOT listed as a use case for this circuit?




Question 6: In the expected outcome, what happens to frequencies in the passband (below ~1 kHz)?




Question 7: Why is this filter useful before Analog-to-Digital Conversion (ADC)?




Question 8: How does the capacitor behave in this circuit to achieve filtering?




Question 9: What is a specific application of this filter in audio systems mentioned in the text?




Question 10: What does this circuit filter out from DC power lines?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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