Practical case: Modulated light audio receiver

Modulated light audio receiver prototype (Maker Style)

Level: Medium – Build a receiver capable of demodulating an audio signal transmitted via an LED light beam using a photodiode.

Objective and use case

In this practical case, you will build an analog optical receiver using a high-speed photodiode configured in photoconductive mode, followed by a Transimpedance Amplifier (TIA) and an audio power amplifier. This circuit detects changes in light intensity modulated by an audio source and converts them back into electrical signals to drive a speaker.

Why it is useful:
* Optical Wireless Communication (OWC): Demonstrates the fundamental physics behind Li-Fi and infrared remote controls.
* Galvanic Isolation: Allows audio transmission between devices without a physical ground connection, preventing ground loops.
* Security: Unlike radio frequency (RF), optical signals are confined to the room and cannot pass through opaque walls.
* Interference Immunity: Immune to electromagnetic interference (EMI) that typically affects copper wire transmission.

Expected outcome:
* Signal Output: A measurable voltage waveform at the TIA output (V_PRE) that mirrors the transmitted audio waveform.
* Audio Output: Clear sound reproduction through the loudspeaker (LS1) when the photodiode receives modulated light.
* Voltage Levels: The TIA output should ride on a DC bias (approx. VCC/2) with an AC signal swing depending on light intensity.
* Volume Control: Adjustment of the audio level via the potentiometer (R_VOL).

Target audience: Electronics students and hobbyists interested in analog signal conditioning.

Materials

V1: 9 V DC voltage source, function: Main circuit power supply.
D1: BPW34 Photodiode, function: Optical sensor (light to current converter).
U1: TL071 Operational Amplifier, function: Transimpedance Amplifier (TIA).
U2: LM386N-1 Audio Amplifier IC, function: Power amplification for speaker.
R_F: 100 kΩ resistor, function: TIA feedback resistor (sets gain).
R_B1: 10 kΩ resistor, function: Voltage divider top for VCC/2 bias.
R_B2: 10 kΩ resistor, function: Voltage divider bottom for VCC/2 bias.
R_VOL: 10 kΩ potentiometer, function: Audio volume control.
C_DEC: 100 nF ceramic capacitor, function: Power supply decoupling.
C_BIAS: 10 µF electrolytic capacitor, function: Stabilize VCC/2 bias point.
C_COUP: 4.7 µF electrolytic capacitor, function: DC blocking between TIA and Audio Amp.
C_OUT: 220 µF electrolytic capacitor, function: Output coupling for speaker.
C_GAIN: 10 µF electrolytic capacitor, function: LM386 gain setting (Pins 1-8).
LS1: 8 Ω / 0.5W Speaker, function: Audio transducer.

Wiring guide

This guide defines the connections using specific SPICE node names: VCC, 0 (GND), V_BIAS, N_INV (Inverting input), V_PRE (Pre-amp out), V_WIPER (Potentiometer out), and V_SPK (Amp out).

Power and Bias:
* V1: Positive terminal to VCC, Negative terminal to 0.
* R_B1: Connects between VCC and V_BIAS.
* R_B2: Connects between V_BIAS and 0.
* C_BIAS: Positive lead to V_BIAS, Negative lead to 0.
* C_DEC: Connects between VCC and 0 (near U1).

Transimpedance Amplifier (Stage 1):
* U1 (Op-Amp): V+ pin to VCC, V- pin to 0. Non-inverting input (+) to V_BIAS. Inverting input (-) to N_INV. Output pin to V_PRE.
* D1 (Photodiode): Cathode to VCC, Anode to N_INV (Reverse biased).
* R_F: Connects between N_INV and V_PRE.

Signal Coupling:
* C_COUP: Positive lead to V_PRE, Negative lead to NODE_POT_TOP.
* R_VOL: Top terminal to NODE_POT_TOP, Bottom terminal to 0, Wiper to V_WIPER.

Power Amplifier (Stage 2):
* U2 (LM386): Vs (Pin 6) to VCC, GND (Pin 4) to 0. Non-inverting Input (Pin 3) to V_WIPER. Inverting Input (Pin 2) to 0.
* C_GAIN: Connects between Pin 1 and Pin 8 of U2 (Positive to Pin 1).
* C_OUT: Positive lead to U2 Output (Pin 5), Negative lead to V_SPK.
* LS1: Connects between V_SPK and 0.

Conceptual block diagram

Schematic

Title: Practical case: Modulated light audio receiver

      [ INPUT / SENSOR ]               [ STAGE 1: TIA PRE-AMP ]                  [ INTERSTAGE ]                [ STAGE 2: POWER AMP ]              [ OUTPUT ]

                                     +-----------[ R_F: 100k ]-----------+
                                     |           (Feedback)              |
                                     v                                   |
(Light) ~~~> [ D1: BPW34 ] --(I)--> [ (-) N_INV      U1: TL071      OUT ] --(V_PRE)--> [ C_COUP ] --> [ R_VOL: 10k ] --(V_WIPER)-->+
             (Photodiode)           |                                    |             (4.7uF)        (Volume Pot)                 |
                                    | (+) V_BIAS                         |                                                         |
                                    +----------------^-------------------+                                                         |
                                                     |                                                                             |
      [ POWER & BIAS ]                               |                                                                             v
                                                     |                                                                     [ IN+  U2: LM386  OUT ] --(V_SPK)--> [ C_OUT ] --> [ LS1: Speaker ]
    [ V1: 9 V DC Source ] --(VCC)--> (Powers U1, U2)  |                                                                     |                 |                (220uF)        (8 Ohm)
             |                                       |                                                                     |  Gain Pins 1-8  |                                  |
             +---> [ Bias Divider ] --(VCC/2 Ref)----+                                                                     +--------+--------+                                 GND
                   (R_B1, R_B2,                                                                                                     |
                    C_BIAS)                                                                                                    [ C_GAIN ]
                                                                                                                                (10uF)

Schematic (ASCII)

Electrical diagram

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Measurements and tests

Bias Point Check: Use a multimeter to measure the voltage at node V_BIAS. It should be approximately 4.5 V (half of VCC). If not, check R_B1 and R_B2.
Ambient Light Level: Measure the DC voltage at V_PRE without any modulated signal (just ambient light). It should be slightly lower than V_BIAS depending on the ambient brightness hitting D1.
Signal Acquisition:
- Point a modulated light source (e.g., an LED connected to an audio output or a signal generator) at D1.
- Use an oscilloscope at V_PRE. You should see an AC waveform superimposed on the DC level.
- Measure the Vpp (Peak-to-Peak Voltage). It should be in the range of 100 mV to 1 V depending on the distance and light intensity.
Audio Test: Turn R_VOL up slowly. You should hear the transmitted audio clearly from LS1.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Modulated light audio receiver

* --- Component Models ---
* Generic Photodiode Model
.model D_BPW34 D(Is=1n Rs=5 Cjo=10p)

* --- Subcircuits ---

* TL071 Operational Amplifier Macro Model
* Pinout: 1=NonInv 2=Inv 3=V+ 4=V- 5=Out
.SUBCKT TL071 P_NI P_INV P_VCC P_VEE P_OUT
  * Input Impedance
  Rin P_NI P_INV 1T
  * Output Stage (Behavioral with Rail Limiting)
  * Models high open-loop gain and saturation at Rails +/- 1.5V
  B1 P_OUT 0 V=V(P_VEE) + 1.5 + (V(P_VCC)-V(P_VEE)-3) * (1 / (1 + exp(-100000 * (V(P_NI)-V(P_INV)))))
.ENDS TL071

* LM386 Audio Amplifier Macro Model
* Pinout: 1=Gain 2=Inv 3=NonInv 4=GND 5=Out 6=Vs 8=Gain
* ... (truncated in public view) ...

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* Practical case: Modulated light audio receiver

* --- Component Models ---
* Generic Photodiode Model
.model D_BPW34 D(Is=1n Rs=5 Cjo=10p)

* --- Subcircuits ---

* TL071 Operational Amplifier Macro Model
* Pinout: 1=NonInv 2=Inv 3=V+ 4=V- 5=Out
.SUBCKT TL071 P_NI P_INV P_VCC P_VEE P_OUT
  * Input Impedance
  Rin P_NI P_INV 1T
  * Output Stage (Behavioral with Rail Limiting)
  * Models high open-loop gain and saturation at Rails +/- 1.5V
  B1 P_OUT 0 V=V(P_VEE) + 1.5 + (V(P_VCC)-V(P_VEE)-3) * (1 / (1 + exp(-100000 * (V(P_NI)-V(P_INV)))))
.ENDS TL071

* LM386 Audio Amplifier Macro Model
* Pinout: 1=Gain 2=Inv 3=NonInv 4=GND 5=Out 6=Vs 8=Gain
.SUBCKT LM386 P_G1 P_INV P_NI P_GND P_OUT P_VS P_G8
  * Internal Gain Resistor (1.35k) connecting Pins 1 and 8
  R_GAIN_INT P_G1 P_G8 1.35k
  * High resistance to GND to prevent floating node errors for the Gain capacitor
  R_C1 P_G1 0 100Meg
  R_C8 P_G8 0 100Meg
  
  * Audio Amplifier Behavioral Source
  * Self-biasing output to Vs/2
  * Fixed Gain approx 200 (Assuming C_GAIN is present externally)
  B_OUT P_OUT P_GND V=V(P_VS)/2 + 200*(V(P_NI)-V(P_INV))
.ENDS LM386

* --- Main Circuit ---

* Power Supply (9V)
V1 VCC 0 DC 9

* Power Supply Decoupling
C_DEC VCC 0 100n

* Bias Voltage Generator (VCC/2)
R_B1 VCC V_BIAS 10k
R_B2 V_BIAS 0 10k
C_BIAS V_BIAS 0 10u

* --- Stage 1: Transimpedance Amplifier (TIA) ---
* U1 TL071 Op-Amp
* Connections: NI=V_BIAS, INV=N_INV, V+=VCC, V-=0, OUT=V_PRE
XU1 V_BIAS N_INV VCC 0 V_PRE TL071

* Photodiode Sensor (Reverse Biased)
* Cathode to VCC, Anode to N_INV
D1 N_INV VCC D_BPW34

* Optical Signal Simulation
* Current source representing modulated light (1kHz square wave)
* Connected parallel to photodiode (Anode to Cathode current flow)
I_LIGHT N_INV VCC PULSE(0 2u 0 1u 1u 500u 1000u)

* Feedback Resistor
R_F N_INV V_PRE 100k

* --- Signal Coupling ---
* DC Blocking Capacitor
C_COUP V_PRE NODE_POT_TOP 4.7u

* Volume Potentiometer (10k)
* Modeled as voltage divider. Wiper set to 20% to manage gain.
* Top Resistor (8k)
R_VOL_TOP NODE_POT_TOP V_WIPER 8k
* Bottom Resistor (2k)
R_VOL_BOT V_WIPER 0 2k

* --- Stage 2: Power Amplifier ---
* U2 LM386 Audio Amp
* Connections: 1=GAIN_P, 2=0, 3=V_WIPER, 4=0, 5=V_AMP_OUT, 6=VCC, 8=GAIN_N
XU2 GAIN_P 0 V_WIPER 0 V_AMP_OUT VCC GAIN_N LM386

* Gain Setting Capacitor (Pins 1-8)
C_GAIN GAIN_P GAIN_N 10u

* Output Coupling Capacitor
C_OUT V_AMP_OUT V_SPK 220u

* Speaker Load (8 Ohm)
LS1 V_SPK 0 8

* --- Simulation Directives ---
* Transient analysis for 5ms to see 5 cycles of 1kHz audio
.tran 10u 5ms

* Output data for plotting
.print tran V(V_PRE) V(V_WIPER) V(V_SPK)

.end

Simulation Results (Transient Analysis)

Show raw data table (623 rows)

Index   time            v(v_pre)        v(v_wiper)      v(v_spk)
0	0.000000e+00	4.499900e+00	0.000000e+00	0.000000e+00
1	1.000000e-08	4.501899e+00	3.998838e-04	7.997676e-02
2	1.083984e-08	4.502067e+00	4.334770e-04	8.669540e-02
3	1.251953e-08	4.502403e+00	5.006638e-04	1.001328e-01
4	1.587889e-08	4.503075e+00	6.350376e-04	1.270075e-01
5	2.259763e-08	4.504418e+00	9.037850e-04	1.807570e-01
6	3.603509e-08	4.507106e+00	1.441280e-03	2.882560e-01
7	6.291003e-08	4.512481e+00	2.516269e-03	5.032538e-01
8	1.166599e-07	4.523231e+00	4.666245e-03	9.332491e-01
9	2.241596e-07	4.544731e+00	8.966191e-03	1.793238e+00
10	4.391591e-07	4.587730e+00	1.756605e-02	3.513210e+00
11	8.691581e-07	4.673729e+00	3.476566e-02	6.953131e+00
12	1.000000e-06	4.699898e+00	3.999919e-02	7.999838e+00
13	1.086000e-06	4.699898e+00	3.999923e-02	7.999847e+00
14	1.257999e-06	4.699898e+00	3.999909e-02	7.999818e+00
15	1.601999e-06	4.699898e+00	3.999879e-02	7.999759e+00
16	2.289997e-06	4.699898e+00	3.999821e-02	7.999642e+00
17	3.665994e-06	4.699898e+00	3.999704e-02	7.999408e+00
18	6.417987e-06	4.699898e+00	3.999470e-02	7.998939e+00
19	1.192197e-05	4.699898e+00	3.999001e-02	7.998002e+00
20	2.192197e-05	4.699898e+00	3.998151e-02	7.996300e+00
21	3.192197e-05	4.699898e+00	3.997300e-02	7.994598e+00
22	4.192197e-05	4.699898e+00	3.996450e-02	7.992895e+00
23	5.192197e-05	4.699898e+00	3.995599e-02	7.991193e+00
... (599 more rows) ...

Common mistakes and how to avoid them

Reversed Photodiode Polarity: Connecting the anode to VCC will forward bias the diode, causing it to conduct fully and saturate the amplifier. Solution: Ensure the Cathode (usually marked with a flat side or shorter lead) goes to VCC.
Omitting DC Blocking Capacitors: Connecting the output of the TIA directly to the LM386 volume pot can upset the biasing of the audio amp. Solution: Always use C_COUP to pass only the audio signal and block the DC offset.
Optical Saturation: Testing under direct sunlight or very strong artificial light saturates the photodiode, flattening the signal. Solution: Use an optical shield (a black tube) around D1 to limit the field of view to the transmitter only.

Troubleshooting

Symptom: Constant loud hum or buzzing.
- Cause: 50Hz/60Hz noise pickup from ambient room lighting (fluorescent/mains).
- Fix: Turn off room lights or use an optical filter (red/IR plastic) over D1.
Symptom: No audio, but V_PRE shows signal.
- Cause: R_VOL is at minimum or LM386 wiring is incorrect.
- Fix: Check the wiper connection of the potentiometer and ensure U2 power pins are correct.
Symptom: Signal is clipped (squared off) at the TIA.
- Cause: Gain resistor R_F is too high for the light intensity received.
- Fix: Reduce R_F to 47 kΩ or move the transmitter further away.

Possible improvements and extensions

Bandpass Filter: Replace R_F with a T-network or add a capacitor in parallel to create a low-pass filter, and add a high-pass filter stage to remove 50/60Hz mains hum.
Schmitt Trigger Output: Feed the output of V_PRE into a comparator or Schmitt trigger (like a 74HC14) to convert the analog audio receiver into a digital data receiver for UART transmission.

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Practical case: Optical tachometer for DC motor

Optical tachometer for DC motor prototype (Maker Style)

Level: Medium – Design an RPM measurement system using a photodiode in photoconductive mode to detect light interruptions.

Objective and use case

In this practical case, you will build a non-contact optical sensor circuit that converts light interruptions caused by a rotating propeller into a clean digital pulse stream. The system uses a photodiode in reverse bias (photoconductive mode) to detect light intensity changes, a comparator to digitize the analog signal, and a logic inverter to buffer the output.

Why it is useful:
* Speed Control Systems: Provides feedback for PID controllers to maintain constant motor speed under varying loads.
* Conveyor Belt Monitoring: Detects jams or stoppages by monitoring the rotation of drive rollers.
* Fan Failure Detection: Used in servers and industrial equipment to trigger alarms if cooling fans stop spinning.
* Non-contact Measurement: Allows measurement of high-speed mechanical parts without adding friction or physical wear.

Expected outcome:
* Signal generation: A square wave output (VOUT) where the frequency is proportional to the motor speed.
* Visual indication: An indicator LED flashes in sync with the propeller blade passing (visible at low speeds).
* Voltage levels: The analog sensor voltage swings between ≈ 0 V (dark) and $>2 V$ (light), converted to valid 5 V TTL logic levels at the output.
* Target audience: Electronics students and hobbyists familiar with basic Op-Amps and discrete semiconductors.

Materials

Bill of Materials:
* V1: 5 V DC supply, function: Main circuit power.
* V2: 5 V DC supply, function: Power for the external light source (or shared with V1).
* D1: BPW34 (or generic) Photodiode, function: Light sensor (Reverse biased).
* R1: 100 kΩ resistor, function: Current-to-voltage conversion (Gain resistor).
* RV1: 10 kΩ potentiometer, function: Adjustable reference voltage (VREF) for the comparator.
* U1: LM358 Op-Amp, function: Voltage comparator.
* U2: 74HC04 Hex Inverter, function: Signal buffering and inversion.
* R2: 330 Ω resistor, function: Output LED current limiting.
* D2: Red LED, function: Pulse indicator.
* L1: White LED or Flashlight, function: External light source pointing at D1.
* M1: DC Motor with a propeller/fan, function: Object to measure (cuts the light beam).

Pin-out of the IC used

Selected Chip: 74HC04 (Hex Inverter)

Pin	Name	Logic Function	Connection in this case
1	1 A	Input	Connected to Comparator Output (`VCOMP`)
2	1Y	Output	Connected to Output Node (`VOUT`)
7	GND	Ground	Connected to Circuit Ground (`0`)
14	VCC	Power Supply	Connected to `VCC` (5 V)

Note: The LM358 Op-Amp pinout is standard (Pin 8: VCC, Pin 4: GND, Pin 3: Non-inverting input, Pin 2: Inverting input, Pin 1: Output).

Wiring guide

Construct the circuit following these node connections. Ensure the photodiode is shielded from ambient light for best results.

Power Nodes:
- VCC: Connect positive terminal of V1, Pin 8 of U1 (LM358), Pin 14 of U2 (74HC04), and one side of RV1.
- 0 (GND): Connect negative terminal of V1, Pin 4 of U1, Pin 7 of U2, the other side of RV1, Anode of D1, and Cathode of D2.
Sensor Stage (Photoconductive Mode):
- VSENS: Connect Cathode of D1 (Photodiode), one end of R1, and Pin 3 (Non-inverting input) of U1.
- Connect the other end of R1 to VCC.
- Note: This configuration creates a voltage divider. When light hits D1, reverse current flows, dropping voltage at VSENS. Dark = High Voltage (near VCC); Light = Low Voltage.
Comparator Stage:
- VREF: Connect the wiper (middle pin) of RV1 to Pin 2 (Inverting input) of U1.
- VCOMP: Connect Pin 1 (Output) of U1 to Pin 1 (Input 1 A) of U2.
Output Stage:
- VOUT: Connect Pin 2 (Output 1Y) of U2 to one end of R2. This is your measurement point for the oscilloscope.
- Connect the other end of R2 to the Anode of D2 (LED).

Conceptual block diagram

Schematic

Title: Practical case: Optical tachometer for DC motor

      [ INPUTS / SENSORS ]                     [ LOGIC / PROCESSING ]                  [ OUTPUTS ]

[ Light Source L1 ]
        |
   (Light Beam)
        |
        v
[ Motor M1 (Propeller) ]
        |
 (Interrupted Beam)
        |
        v
[ Photodiode D1 ] --(VSENS: Pin 3)-->+----------------+
(Rev-Biased w/ R1)                   |                |
                                     |   U1: LM358    |
                                     |   Comparator   | --(VCOMP: Pin 1)-->+
                                     |                |                    |
[ Potentiometer RV1 ] --(VREF: Pin 2)-->+----------------+                    |
(Adjust Sensitivity)                                                       |
                                                                           v
                                                                   +----------------+
                                                                   |                |
                                                                   |   U2: 74HC04   |
                                                                   |  Hex Inverter  |
                                                                   |                |
                                                                   +-------+--------+
                                                                           |
                                                                     (VOUT: Pin 2)
                                                                           |
                                                                           +--------(Scope Probe)-->
                                                                           |
                                                                           v
                                                                    [ Resistor R2 ]
                                                                           |
                                                                           v
                                                                      [ LED D2 ]
                                                                           |
                                                                           v
                                                                         (GND)

Schematic (ASCII)

Electrical diagram

Truth table (Logic Stage)

This table describes the logic flow from the physical state to the final electrical output.

State of Propeller	Light at Photodiode (D1)	Voltage at `VSENS`	Comparator Out (`VCOMP`)	Inverter Out (`VOUT`)	LED (`D2`)
Blocking Light	Low / Dark	High (> VREF)	High (Logic 1)	Low (Logic 0)	OFF
Pass Through	High / Bright	Low (< VREF)	Low (Logic 0)	High (Logic 1)	ON

Note: Since the sensor configuration pulls VSENS low when illuminated, the Comparator output goes Low when lit. The 74HC04 inverts this, so the LED turns ON when light passes through.

Measurements and tests

Calibration (Static Test):
- Power on the system (V1 = 5 V).
- Ensure the light source L1 is shining directly on D1.
- Measure VSENS with a multimeter. It should be low (e.g., 1 V – 2 V) due to photocurrent.
- Block the light with your hand. VSENS should rise close to VCC (e.g., 4.5 V).
- Adjust potentiometer RV1 so that VREF is exactly in the middle of these two values (e.g., if Dark=4.5 V and Light=1.5 V, set VREF to 3.0 V).
Dynamic Test:
- Place the motor M1 so its propeller cuts the beam between L1 and D1.
- Connect Channel 1 of your oscilloscope to VOUT.
- Run the motor. You should see a square wave train.
Calculation:
- Measure the frequency ($f$) of the signal at VOUT in Hertz.
- Count the number of blades ($N$) on your propeller.
- Calculate RPM: RPM = ≤ft( (f / N) \right) × 60.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Optical tachometer for DC motor

* ==========================================
* Models and Definitions
* ==========================================

* Photodiode Model (Generic BPW34)
.model D_BPW34 D(IS=10n N=1.1 RS=5 CJO=20p)

* Output LED Model (Red)
.model LED_Red D(IS=1u N=1.8 RS=5 BV=5 IBV=10u)

* External Light Source LED Model (White)
.model LED_White D(IS=1n N=2.5 RS=10 BV=5 IBV=10u)

* Subcircuit: LM358 Op-Amp (Comparator Mode)
* Pins: OUT INM INP GND VCC
.subckt LM358 OUT INM INP GND VCC
* Dummy resistors to ensure DC path for all pins (avoids floating node warnings)
R_supply VCC GND 100Meg
* ... (truncated in public view) ...

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* Practical case: Optical tachometer for DC motor

* ==========================================
* Models and Definitions
* ==========================================

* Photodiode Model (Generic BPW34)
.model D_BPW34 D(IS=10n N=1.1 RS=5 CJO=20p)

* Output LED Model (Red)
.model LED_Red D(IS=1u N=1.8 RS=5 BV=5 IBV=10u)

* External Light Source LED Model (White)
.model LED_White D(IS=1n N=2.5 RS=10 BV=5 IBV=10u)

* Subcircuit: LM358 Op-Amp (Comparator Mode)
* Pins: OUT INM INP GND VCC
.subckt LM358 OUT INM INP GND VCC
* Dummy resistors to ensure DC path for all pins (avoids floating node warnings)
R_supply VCC GND 100Meg
R_inM    INM GND 100Meg
R_inP    INP GND 100Meg
* Behavioral Output: High (VCC) if INP > INM, Low (GND) otherwise
B_Out OUT GND V = (V(VCC)-V(GND)) * (1 / (1 + exp(-100 * (V(INP)-V(INM)))))
.ends LM358

* Subcircuit: 74HC04 Hex Inverter (Single Gate)
* Pins: IN OUT GND VCC
.subckt 74HC04_Gate IN OUT GND VCC
* Dummy resistors
R_supply VCC GND 100Meg
R_in     IN  GND 100Meg
* Inverter Logic: High if IN < 2.5V
B_Out OUT GND V = (V(VCC)-V(GND)) * (1 / (1 + exp(100 * (V(IN) - 2.5))))
.ends 74HC04_Gate

* ==========================================
* Circuit Instantiation
* ==========================================

* --- Power Supply Section ---
* V1: 5V DC Supply for the main circuit (VCC)
V1 VCC 0 DC 5

* V2: 5V DC Supply for external components (Motor/Light)
V2 VCC_EXT 0 DC 5

* --- Environment (Physical BOM Components) ---
* L1: White LED (External Light Source)
* Modeled as electrical load on V2. Light emission is implicit.
R_L1 VCC_EXT N_L1 220
D_L1 N_L1 0 LED_White

* M1: DC Motor (Propeller)
* Modeled as electrical load on V2. Rotation is simulated by the chopper signal.
R_M1 VCC_EXT N_M1 20
L_M1 N_M1 0 10m

* Optical Interaction Simulation:
* V_Chopper simulates the propeller cutting the light beam from L1 to D1.
* 1V = Light Passing (Gap), 0V = Light Blocked (Blade).
* Frequency approx 500Hz (2ms period).
V_Chopper V_OPT_LINK 0 PULSE(0 1 0 100u 100u 800u 2000u)

* --- Sensor Stage ---
* R1: 100k Resistor (Pull-up) connecting VCC to VSENS
R1 VCC VSENS 100k

* D1: BPW34 Photodiode
* Wiring: Cathode to VSENS, Anode to GND (Reverse Biased)
D1 0 VSENS D_BPW34

* Photocurrent Injection (Behavioral):
* Represents light hitting D1 when V_OPT_LINK is High.
* Current flows Cathode to Anode (VSENS to GND). I_photo = 50uA.
B_Photo VSENS 0 I = V(V_OPT_LINK) * 50u

* --- Comparator Stage ---
* RV1: 10k Potentiometer (Reference Voltage)
* Configured as 50% divider (5k + 5k) setting VREF to ~2.5V.
R_RV1_Top VCC VREF 5k
R_RV1_Bot VREF 0 5k

* U1: LM358 Op-Amp configured as Comparator
* Pin 8=VCC, Pin 4=GND, Pin 3=VSENS (Non-Inv), Pin 2=VREF (Inv), Pin 1=VCOMP
XU1 VCOMP VREF VSENS 0 VCC LM358

* --- Buffer/Inverter Stage ---
* U2: 74HC04 Hex Inverter (Gate 1)
* Pin 14=VCC, Pin 7=GND, Pin 1=VCOMP (Input), Pin 2=VOUT (Output)
XU2 VCOMP VOUT 0 VCC 74HC04_Gate

* --- Output Stage ---
* R2: 330 Ohm Current Limiting Resistor
R2 VOUT LED_A 330

* D2: Red LED (Signal Indicator)
* Wiring: Anode to R2, Cathode to GND
D2 LED_A 0 LED_Red

* ==========================================
* Analysis Commands
* ==========================================

* Transient analysis: 10ms to capture 5 pulses
.tran 100u 10ms

* Monitor signals
.print tran V(VSENS) V(VREF) V(VCOMP) V(VOUT) V(LED_A) V(V_OPT_LINK)

.end

Simulation Results (Transient Analysis)

Show raw data table (526 rows)

Index   time            v(vsens)        v(vref)         v(vcomp)
0	0.000000e+00	4.994005e+00	2.499938e+00	5.000000e+00
1	1.000000e-06	4.966501e+00	2.499938e+00	5.000000e+00
2	2.000000e-06	4.926705e+00	2.499938e+00	5.000000e+00
3	4.000000e-06	4.836178e+00	2.499938e+00	5.000000e+00
4	8.000000e-06	4.635945e+00	2.499938e+00	5.000000e+00
5	1.600000e-05	4.238426e+00	2.499938e+00	5.000000e+00
6	3.200000e-05	3.442420e+00	2.499938e+00	5.000000e+00
7	6.400000e-05	1.854804e+00	2.499938e+00	4.799431e-28
8	1.000000e-04	8.527235e-02	2.499938e+00	5.000000e-99
9	1.009874e-04	5.613111e-02	2.499938e+00	5.038370e-99
10	1.029622e-04	1.810390e-02	2.499938e+00	5.069277e-99
11	1.055177e-04	3.702381e-03	2.499938e+00	5.376972e-99
12	1.063053e-04	2.444841e-03	2.499938e+00	6.193694e-99
13	1.072769e-04	1.458053e-03	2.499938e+00	5.050362e-99
14	1.083003e-04	8.469348e-04	2.499938e+00	4.694441e-99
15	1.095417e-04	4.347045e-04	2.499938e+00	5.049162e-99
16	1.109578e-04	2.013374e-04	2.499938e+00	4.883316e-99
17	1.123791e-04	9.296145e-05	2.499938e+00	4.945812e-99
18	1.143288e-04	3.056502e-05	2.499938e+00	4.968802e-99
19	1.167173e-04	7.196143e-06	2.499938e+00	4.988316e-99
20	1.202744e-04	2.927790e-07	2.499938e+00	4.996548e-99
21	1.252257e-04	-3.66547e-08	2.499938e+00	4.999835e-99
22	1.343972e-04	1.488928e-08	2.499938e+00	5.000026e-99
23	1.527400e-04	-9.71180e-09	2.499938e+00	4.999988e-99
... (502 more rows) ...

Common mistakes and how to avoid them

Photodiode polarity reversed: In photoconductive mode, the photodiode MUST be reverse-biased (Cathode to positive potential relative to Anode). If connected forward, it acts like a regular diode and won’t sense light effectively.
- Fix: Check the flat side or shorter lead of the photodiode and ensure it connects to the VSENS node (which is pulled up to VCC via R1).
Improper Reference Voltage (VREF): If VREF is set too high (above the dark voltage) or too low (below the light voltage), the comparator will never toggle.
- Fix: Always measure VSENS in both dark and light states before setting RV1.
Ambient Light Interference: Room lighting (especially fluorescent lights flickering at 50/60Hz) can trigger the sensor falsely.
- Fix: Use an opaque tube (heat shrink or a pen casing) around the photodiode to narrow its field of view strictly to the light source.

Troubleshooting

Symptom: LED is always ON or always OFF.
- Cause: VREF is not set correctly or the light source is too weak.
- Fix: Retune RV1. Ensure L1 is bright and aligned.
Symptom: Output signal is jittery or has multiple glitches per pulse.
- Cause: Noisy transitions when the voltage crosses the threshold slowly.
- Fix: Add a small hysteresis resistor (e.g., 1 MΩ) between VCOMP and Pin 3 of U1, or ensure the optical transition is sharp (focused beam).
Symptom: VSENS does not change significantly with light.
- Cause: R1 value is too low for the sensitivity of D1.
- Fix: Increase R1 to 220 kΩ or 470 kΩ to increase voltage gain (V = Iphoto × R1).

Possible improvements and extensions

Hysteresis (Schmitt Trigger): Modify the Op-Amp circuit to include positive feedback. This creates two distinct threshold voltages, making the system immune to noise around the switching point.
Reflective Sensor Mode: Instead of placing the light source opposite the sensor (transmissive), place them side-by-side. Paint the propeller blades black (non-reflective) and white (reflective). This allows measuring RPM on motors where you cannot access both sides of the blades.

More Practical Cases on Prometeo.blog

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Practical case: Zener Diode as a Voltage Regulator

Zener Diode as a Voltage Regulator prototype (Maker Style)

Level: Medium. Design and verify a voltage stabilizer circuit using a Zener diode under load variations.

Objective and use case

In this session, you will build a shunt voltage regulator using a Zener diode and a series limiting resistor to maintain a fixed 5.1 V output from a 9 V source.

Why it is useful:
- Provides a stable reference voltage for Analog-to-Digital Converters (ADCs).
- Protects sensitive downstream components (like microcontrollers) from over-voltage spikes.
- Regulates voltage for low-power circuits without the complexity of an IC regulator.
Expected outcome:
- The output voltage (VOUT) remains clamped at approximately 5.1 V despite the input being 9 V.
- Connecting a moderate load (470 Ω) decreases Zener current but maintains VOUT at 5.1 V.
- If the load resistance becomes too low, the regulation fails, and VOUT drops below 5.1 V.
Target audience: Electronics students, Level: Medium.

Materials

V1: 9 V DC voltage source, function: main power supply.
R1: 220 Ω resistor, function: series current limiting (RS).
D1: 1N4733 A Zener diode (5.1 V, 1 W), function: shunt voltage regulator.
R2: 470 Ω resistor, function: load simulation (RL).
M1: Multimeter (Voltmeter mode), function: measure output voltage.
M2: Multimeter (Ammeter mode), function: measure Zener current (IZ).

Wiring guide

Construct the circuit using the following connections and SPICE node names (VIN, VOUT, 0):

V1 (9 V Supply): Connect Positive terminal to node VIN and Negative terminal to node 0 (GND).
R1 (Series Resistor): Connect one terminal to VIN and the other terminal to node VOUT.
D1 (Zener Diode): Connect the Cathode (striped end) to node VOUT and the Anode to node 0.
R2 (Load Resistor): Connect one terminal to VOUT and the other terminal to node 0.
Measurements:
- To measure VOUT: Connect the Voltmeter Positive probe to VOUT and Negative probe to 0.
- To measure IZ: Break the connection between D1 Cathode and VOUT, and insert the Ammeter in series (Positive to VOUT, Negative to D1 Cathode).

Conceptual block diagram

Schematic

[ SOURCE ]                 [ LIMITING ]                     [ REGULATION, LOAD & MEASUREMENT ]

                                                                           (Branch 1: Regulation)
                                                                 +---> [ Ammeter M2 ] --> [ D1: Zener 5.1 V ] --> GND
                                                                 |     (Measure Iz)       (Shunt Regulator)
                                                                 |
    [ V1: 9 V DC ] --(VIN)--> [ R1: 220 Ohm ] --(Node VOUT)--> ---+
    (Main Power)             (Series Resistor)                   |         (Branch 2: Load)
                                                                 +---> [ R2: 470 Ohm ] ------------------------> GND
                                                                 |     (Load Simulation)
                                                                 |
                                                                 |         (Branch 3: Monitoring)
                                                                 +---> [ Voltmeter M1 ] -----------------------> GND
                                                                       (Measure Vout)

Schematic (ASCII)

Electrical diagram

Measurements and tests

Follow these steps to validate the regulator design:

Open Circuit Test (No Load):
- Temporarily disconnect R2.
- Measure voltage at VOUT. It should read approximately 5.1 V.
- Calculate the current flowing through the Zener: IZ = (VIN – VZ) / R1. Expect ≈ 17.7 mA.
Load Regulation Test:
- Reconnect R2 (470 Ω) between VOUT and 0.
- Measure VOUT again. It should remain stable at 5.1 V.
- Observe the Zener current. It should decrease because some current is now diverted through the load RL.
- Expected Load Current (IL): 5.1 V / 470 Ω ≈ 10.8 mA.
- Remaining Zener Current: ≈ 17.7 mA – 10.8 mA = 6.9 mA. Since IZ > 0, regulation holds.
Overload Test (Simulation):
- Replace R2 with a 100 Ω resistor (if available) or simulate a short.
- Measure VOUT. The voltage will drop significantly below 5.1 V because the load demands more current than R1 can supply while maintaining the Zener breakdown voltage.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Zener Diode as a Voltage Regulator

* --- Power Supply ---
* V1: 9 V DC voltage source (Main Supply)
V1 VIN 0 DC 9

* --- Components ---
* R1: 220 Ohm Resistor (Series Current Limiting)
* Wiring: Connect one terminal to VIN and the other to VOUT
R1 VIN VOUT 220

* R2: 470 Ohm Resistor (Load Simulation)
* Wiring: Connect one terminal to VOUT and the other to 0 (GND)
R2 VOUT 0 470

* M1: Multimeter (Voltmeter mode)
* Wiring: Positive probe to VOUT, Negative probe to 0
* Implementation: High impedance resistor to simulate voltmeter load
R_M1_Voltmeter VOUT 0 10Meg

* ... (truncated in public view) ...

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* Practical case: Zener Diode as a Voltage Regulator

* --- Power Supply ---
* V1: 9 V DC voltage source (Main Supply)
V1 VIN 0 DC 9

* --- Components ---
* R1: 220 Ohm Resistor (Series Current Limiting)
* Wiring: Connect one terminal to VIN and the other to VOUT
R1 VIN VOUT 220

* R2: 470 Ohm Resistor (Load Simulation)
* Wiring: Connect one terminal to VOUT and the other to 0 (GND)
R2 VOUT 0 470

* M1: Multimeter (Voltmeter mode)
* Wiring: Positive probe to VOUT, Negative probe to 0
* Implementation: High impedance resistor to simulate voltmeter load
R_M1_Voltmeter VOUT 0 10Meg

* M2: Multimeter (Ammeter mode)
* Wiring: Inserted in series between VOUT and D1 Cathode
* Positive to VOUT, Negative to D1 Cathode (Node: VZ_CATHODE)
* Implementation: 0V DC source to measure current
V_M2_Ammeter VOUT VZ_CATHODE DC 0

* D1: 1N4733A Zener Diode (5.1 V, 1 W)
* Wiring: Cathode to VZ_CATHODE, Anode to 0
* Note: Cathode is connected to VOUT through the Ammeter
D1 0 VZ_CATHODE D1N4733A

* --- Models ---
* Model for 1N4733A Zener Diode
* BV=5.1V (Breakdown Voltage), IBV=49mA (Test Current)
.model D1N4733A D(IS=2.5n RS=1 N=1.2 BV=5.1 IBV=49m)

* --- Analysis ---
* Transient analysis (1ms simulation time)
.tran 1u 1ms

* --- Output Directives ---
* Print voltages and Zener current (Iz)
.print tran V(VIN) V(VOUT) I(V_M2_Ammeter)

* Operating Point for initial check
.op

.end

Simulation Results (Transient Analysis)

Show raw data table (1008 rows)

Index   time            v(vin)          v(vout)         v_m2_ammeter#br
0	0.000000e+00	9.000000e+00	5.047821e+00	7.223902e-03
1	1.000000e-08	9.000000e+00	5.047805e+00	7.224007e-03
2	2.000000e-08	9.000000e+00	5.047805e+00	7.224007e-03
3	4.000000e-08	9.000000e+00	5.047805e+00	7.224007e-03
4	8.000000e-08	9.000000e+00	5.047805e+00	7.224007e-03
5	1.600000e-07	9.000000e+00	5.047805e+00	7.224007e-03
6	3.200000e-07	9.000000e+00	5.047805e+00	7.224007e-03
7	6.400000e-07	9.000000e+00	5.047805e+00	7.224007e-03
8	1.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
9	2.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
10	3.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
11	4.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
12	5.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
13	6.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
14	7.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
15	8.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
16	9.280000e-06	9.000000e+00	5.047805e+00	7.224007e-03
17	1.028000e-05	9.000000e+00	5.047805e+00	7.224007e-03
18	1.128000e-05	9.000000e+00	5.047805e+00	7.224007e-03
19	1.228000e-05	9.000000e+00	5.047805e+00	7.224007e-03
20	1.328000e-05	9.000000e+00	5.047805e+00	7.224007e-03
21	1.428000e-05	9.000000e+00	5.047805e+00	7.224007e-03
22	1.528000e-05	9.000000e+00	5.047805e+00	7.224007e-03
23	1.628000e-05	9.000000e+00	5.047805e+00	7.224007e-03
... (984 more rows) ...

Reference SPICE netlist (ngspice)

* Practical case: Zener Diode as a Voltage Regulator

* --- Power Supply ---
* V1: 9 V DC voltage source (Main Supply)
V1 VIN 0 DC 9

* --- Components ---
* R1: 220 Ohm Resistor (Series Current Limiting)
* Wiring: Connect one terminal to VIN and the other to VOUT
R1 VIN VOUT 220

* R2: 470 Ohm Resistor (Load Simulation)
* Wiring: Connect one terminal to VOUT and the other to 0 (GND)
R2 VOUT 0 470

* M1: Multimeter (Voltmeter mode)
* Wiring: Positive probe to VOUT, Negative probe to 0
* Implementation: High impedance resistor to simulate voltmeter load
R_M1_Voltmeter VOUT 0 10Meg

* M2: Multimeter (Ammeter mode)
* Wiring: Inserted in series between VOUT and D1 Cathode
* Positive to VOUT, Negative to D1 Cathode (Node: VZ_CATHODE)
* Implementation: 0V DC source to measure current
V_M2_Ammeter VOUT VZ_CATHODE DC 0

* D1: 1N4733A Zener Diode (5.1 V, 1 W)
* Wiring: Cathode to VZ_CATHODE, Anode to 0
* Note: Cathode is connected to VOUT through the Ammeter
D1 0 VZ_CATHODE D1N4733A

* --- Models ---
* Model for 1N4733A Zener Diode
* BV=5.1V (Breakdown Voltage), IBV=49mA (Test Current)
.model D1N4733A D(IS=2.5n RS=1 N=1.2 BV=5.1 IBV=49m)

* --- Analysis ---
* Transient analysis (1ms simulation time)
.tran 1u 1ms

* --- Output Directives ---
* Print voltages and Zener current (Iz)
.print tran V(VIN) V(VOUT) I(V_M2_Ammeter)

* Operating Point for initial check
.op

.end

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

Reversing the Zener Diode:
- Error: Connecting the Anode to VOUT and Cathode to GND.
- Result: The circuit behaves like a standard diode, clamping the output to ≈ 0.7 V instead of 5.1 V.
- Solution: Ensure the striped end (Cathode) is connected to the positive potential (VOUT).
Using a Series Resistor (R1) with too high resistance:
- Error: Using 10 kΩ instead of 220 Ω for R1.
- Result: When the load (R2) is connected, the voltage drops immediately; the Zener turns off because there isn’t enough current to keep it in breakdown.
- Solution: Calculate R1 such that enough current flows to satisfy both the load and the minimum Zener bias current (IZK).
Exceeding Zener Power Rating:
- Error: Removing the load while using a very small R1.
- Result: All current flows through the Zener, causing it to overheat and potentially burn out.
- Solution: Ensure PZ = VZ × Izmax is less than the diode’s power rating (e.g., 1 W).

Troubleshooting

Symptom: Output voltage is equal to Input voltage (9 V).
- Cause: Zener diode is open (broken) or not connected.
- Fix: Check connections to D1 or replace the diode.
Symptom: Output voltage is ≈ 0.7 V.
- Cause: Zener diode is connected in forward bias (backwards).
- Fix: Reverse the diode orientation.
Symptom: Output is 5.1 V without load, but drops to 3 V (or lower) when load is attached.
- Cause: The load resistance is too low (drawing too much current) or R1 is too high.
- Fix: Increase the load resistance or recalculate R1 for higher current delivery (watching power limits).

Possible improvements and extensions

Series Pass Transistor: Add an NPN transistor (like a 2N2222) with the Zener controlling the base. This creates a Series Voltage Regulator capable of handling much higher load currents.
Filtering: Add a capacitor (e.g., 10 µF) in parallel with the Zener diode to filter out noise and improve the stability of the voltage reference.

More Practical Cases on Prometeo.blog

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Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Who we are

Practical case: Full-wave bridge rectifier

Full-wave bridge rectifier prototype (Maker Style)

Level: Medium – Analyze a Graetz bridge to convert AC to pulsating DC and measure total voltage drop.

Objective and use case

In this practical case, you will build a standard Graetz bridge circuit using four diodes and an AC voltage source to supply a resistive load. This circuit converts an alternating current input (where voltage polarity changes) into a pulsating direct current output (where voltage polarity remains positive).

Why it is useful:
* Power Supplies: It is the fundamental first stage in converting AC mains power to DC for charging laptops, phones, and powering appliances.
* Motor Control: Used in DC motor drives to run motors from an AC supply.
* Polarity Protection: Ensures that a device works correctly regardless of how the input power wires are connected.
* High Efficiency: Utilizes both the positive and negative half-cycles of the AC input, unlike a half-wave rectifier.

Expected outcome:
* Input Signal: A sinusoidal waveform (e.g., 12 V RMS / ~17 V Peak) at 60Hz.
* Output Signal: A series of positive «mounds» (pulsating DC) at 120Hz (double the input frequency).
* Voltage Drop: The peak output voltage will be approximately 1.4 V lower than the peak input voltage due to the forward voltage drop of two diodes in series (2 × 0.7 V).
* Current Flow: Current flows through the load resistor in the same direction during both AC half-cycles.

Target audience and level: Electronics students and hobbyists familiar with basic diode biasing.

Materials

V1: AC Voltage Source (Amplitude: 17 V [12Vrms], Frequency: 60Hz), function: Input supply
D1: 1N4007 Diode, function: Rectifier (Bridge arm 1)
D2: 1N4007 Diode, function: Rectifier (Bridge arm 2)
D3: 1N4007 Diode, function: Rectifier (Bridge arm 3)
D4: 1N4007 Diode, function: Rectifier (Bridge arm 4)
R1: 1 kΩ resistor, function: Output Load

Wiring guide

This guide uses specific node names to represent the connections. Ensure the AC source is floating relative to the DC ground to simulate the isolation provided by a transformer.

V1 (Positive terminal) connects to node AC1.
V1 (Negative terminal) connects to node AC2.
D1 (Anode) connects to node AC1.
D1 (Cathode) connects to node VOUT.
D2 (Anode) connects to node AC2.
D2 (Cathode) connects to node VOUT.
D3 (Anode) connects to node 0 (GND).
D3 (Cathode) connects to node AC1.
D4 (Anode) connects to node 0 (GND).
D4 (Cathode) connects to node AC2.
R1 connects between node VOUT and node 0 (GND).

Conceptual block diagram

Schematic

[ INPUT SOURCE ]               [ PROCESSING / LOGIC ]               [ OUTPUT LOAD ]

[ AC Source V1 ]
(17 V Amp / 60Hz)
       |
       +----(Node AC1)----->+-----------------------------+
                            |    FULL-WAVE BRIDGE         |
                            |                             |
                            |  [ Diodes D1 & D2 ]         |
                            |  (Direct Positive Peaks)    |--(Node VOUT)--> [ Resistor R1 ]
                            |                             |                 (1 kOhm)
                            |                             |                     |
       +----(Node AC2)----->|  [ Diodes D3 & D4 ]         |                     |
       |                    |  (Direct Negative Peaks)    |                     v
       |                    |  (Create Return Path)       |                    GND
(Source Return)             |                             |
                            +-----------------------------+
                                          |
                                          v
                                     (Node 0/GND)

Schematic (ASCII)

Electrical diagram

Measurements and tests

Perform the following steps to validate the circuit operation using an oscilloscope or a multimeter:

Input Verification: Connect channel 1 of the oscilloscope across AC1 and AC2. Verify a full sine wave with a frequency of 60Hz.
Output Visualization: Connect channel 2 of the oscilloscope across R1 (Probe on VOUT, Clip on 0). Observe that the negative portions of the sine wave have been «flipped» up, creating a continuous chain of positive pulses.
Frequency Measurement: Measure the frequency of the signal at VOUT. It should be exactly 120Hz (double the input frequency).
Voltage Drop Analysis: Measure the peak voltage of the Input (Vpeakin) and the peak voltage of the Output (Vpeakout).
- Vpeakout should be approximately Vpeakin – 1.4 V. This accounts for the 0.7 V drop across D1 and 0.7 V drop across D4 (during one cycle) or D2 and D3 (during the other).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Title: Practical case: Full-wave bridge rectifier

* --- Component Instantiation ---

* V1: AC Voltage Source (Amplitude: 17 V, Frequency: 60Hz)
* Wiring: V1 (Positive) -> AC1, V1 (Negative) -> AC2
* Note: Source is floating relative to ground (Node 0), connected only to the bridge.
V1 AC1 AC2 SIN(0 17 60)

* D1: 1N4007 Diode (Bridge arm 1)
* Wiring: Anode -> AC1, Cathode -> VOUT
D1 AC1 VOUT 1N4007

* D2: 1N4007 Diode (Bridge arm 2)
* Wiring: Anode -> AC2, Cathode -> VOUT
D2 AC2 VOUT 1N4007

* D3: 1N4007 Diode (Bridge arm 3)
* Wiring: Anode -> 0 (GND), Cathode -> AC1
D3 0 AC1 1N4007
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Title: Practical case: Full-wave bridge rectifier

* --- Component Instantiation ---

* V1: AC Voltage Source (Amplitude: 17 V, Frequency: 60Hz)
* Wiring: V1 (Positive) -> AC1, V1 (Negative) -> AC2
* Note: Source is floating relative to ground (Node 0), connected only to the bridge.
V1 AC1 AC2 SIN(0 17 60)

* D1: 1N4007 Diode (Bridge arm 1)
* Wiring: Anode -> AC1, Cathode -> VOUT
D1 AC1 VOUT 1N4007

* D2: 1N4007 Diode (Bridge arm 2)
* Wiring: Anode -> AC2, Cathode -> VOUT
D2 AC2 VOUT 1N4007

* D3: 1N4007 Diode (Bridge arm 3)
* Wiring: Anode -> 0 (GND), Cathode -> AC1
D3 0 AC1 1N4007

* D4: 1N4007 Diode (Bridge arm 4)
* Wiring: Anode -> 0 (GND), Cathode -> AC2
D4 0 AC2 1N4007

* R1: 1 kΩ Resistor (Output Load)
* Wiring: VOUT -> 0 (GND)
R1 VOUT 0 1k

* --- Models ---
* Standard model for 1N4007 Rectifier Diode
.model 1N4007 D (IS=7.03n RS=0.034 N=1.81 BV=1000 IBV=0.5u CJO=10p TT=0.1u)

* --- Analysis Commands ---
* Transient analysis: 60Hz period is ~16.6ms.
* Simulating 50ms to capture approximately 3 full cycles.
.tran 50u 50m

* --- Output Directives ---
* Print voltages at AC inputs (relative to GND) and the rectified Output
.print tran V(AC1) V(AC2) V(VOUT)

* Calculate DC operating point
.op

.end

Simulation Results (Transient Analysis)

Show raw data table (1016 rows)

Index   time            v(ac1)          v(ac2)          v(vout)
0	0.000000e+00	3.036573e-18	3.036573e-18	-7.53268e-22
1	5.000000e-07	1.602212e-03	-1.60221e-03	-9.54567e-15
2	1.000000e-06	3.204481e-03	-3.20437e-03	1.126318e-07
3	2.000000e-06	6.409036e-03	-6.40866e-03	3.747988e-07
4	4.000000e-06	1.281816e-02	-1.28172e-02	9.375665e-07
5	8.000000e-06	2.563689e-02	-2.56338e-02	3.056599e-06
6	1.600000e-05	5.127600e-02	-5.12650e-02	1.103556e-05
7	3.200000e-05	1.025657e-01	-1.02513e-01	5.319168e-05
8	6.400000e-05	2.053399e-01	-2.04787e-01	5.532611e-04
9	1.140000e-04	3.725509e-01	-3.57833e-01	1.471794e-02
10	1.640000e-04	5.903791e-01	-4.60003e-01	1.303764e-01
11	2.140000e-04	8.628382e-01	-5.07168e-01	3.556700e-01
12	2.640000e-04	1.155738e+00	-5.33407e-01	6.223310e-01
13	3.140000e-04	1.456815e+00	-5.50867e-01	9.059481e-01
14	3.640000e-04	1.761378e+00	-5.64128e-01	1.197250e+00
15	4.140000e-04	2.068103e+00	-5.74401e-01	1.493702e+00
16	4.640000e-04	2.375673e+00	-5.82891e-01	1.792782e+00
17	5.140000e-04	2.683430e+00	-5.90142e-01	2.093289e+00
18	5.640000e-04	2.990978e+00	-5.96439e-01	2.394538e+00
19	6.140000e-04	3.297988e+00	-6.02000e-01	2.695989e+00
20	6.640000e-04	3.604206e+00	-6.06966e-01	2.997240e+00
21	7.140000e-04	3.909408e+00	-6.11453e-01	3.297955e+00
22	7.640000e-04	4.213406e+00	-6.15537e-01	3.597869e+00
23	8.140000e-04	4.516026e+00	-6.19284e-01	3.896742e+00
... (992 more rows) ...

Reference SPICE netlist (ngspice)

* Title: Practical case: Full-wave bridge rectifier

* --- Component Instantiation ---

* V1: AC Voltage Source (Amplitude: 17 V, Frequency: 60Hz)
* Wiring: V1 (Positive) -> AC1, V1 (Negative) -> AC2
* Note: Source is floating relative to ground (Node 0), connected only to the bridge.
V1 AC1 AC2 SIN(0 17 60)

* D1: 1N4007 Diode (Bridge arm 1)
* Wiring: Anode -> AC1, Cathode -> VOUT
D1 AC1 VOUT 1N4007

* D2: 1N4007 Diode (Bridge arm 2)
* Wiring: Anode -> AC2, Cathode -> VOUT
D2 AC2 VOUT 1N4007

* D3: 1N4007 Diode (Bridge arm 3)
* Wiring: Anode -> 0 (GND), Cathode -> AC1
D3 0 AC1 1N4007

* D4: 1N4007 Diode (Bridge arm 4)
* Wiring: Anode -> 0 (GND), Cathode -> AC2
D4 0 AC2 1N4007

* R1: 1 kΩ Resistor (Output Load)
* Wiring: VOUT -> 0 (GND)
R1 VOUT 0 1k

* --- Models ---
* Standard model for 1N4007 Rectifier Diode
.model 1N4007 D (IS=7.03n RS=0.034 N=1.81 BV=1000 IBV=0.5u CJO=10p TT=0.1u)

* --- Analysis Commands ---
* Transient analysis: 60Hz period is ~16.6ms.
* Simulating 50ms to capture approximately 3 full cycles.
.tran 50u 50m

* --- Output Directives ---
* Print voltages at AC inputs (relative to GND) and the rectified Output
.print tran V(AC1) V(AC2) V(VOUT)

* Calculate DC operating point
.op

.end

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

Ground Loops (Scope): Connecting the oscilloscope ground clip to AC1 or AC2 while the circuit is mains-referenced can cause a short circuit. Solution: Only connect the scope ground to the common circuit ground (0) at the load, or use a differential probe for the input.
Diode Orientation: Inserting a diode backward in the bridge. Solution: Ensure that two diodes point towards the positive DC output node (VOUT) and two diodes point away from the ground node (0).
Ignoring Power Ratings: Using a resistor with low wattage for R1. Solution: Calculate power P = V^2 / R. For 17 V peak, P ≈ 0.3W. Use a 0.5W resistor or greater.

Troubleshooting

Symptom: The output looks like a half-wave rectifier (gaps between pulses).
- Cause: One of the diodes is open (disconnected or blown).
- Fix: Check continuity of all four diodes; replace the faulty one.
Symptom: Zero output voltage.
- Cause: Short circuit in the load or open circuit in the source/wiring.
- Fix: Check connections at AC1 and AC2; ensure R1 is not shorted.
Symptom: Input fuse blows or source current is excessive.
- Cause: One or more diodes are shorted, or a diode is installed in reverse (creating a direct path from AC to Ground).
- Fix: Test diodes for shorts using the diode check mode on a multimeter.

Possible improvements and extensions

Filtering: Add a capacitor (e.g., 470 µF) in parallel with R1 to fill in the gaps between pulses, creating a smooth DC voltage (Ripple reduction).
Regulation: Connect a voltage regulator (like an LM7812 or a Zener diode circuit) after the filter capacitor to produce a constant, stable DC voltage regardless of input fluctuations.

More Practical Cases on Prometeo.blog

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Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Adaptive Screen Brightness Regulator

Adaptive Screen Brightness Regulator prototype (Maker Style)

Level: Medium
Design a circuit that decreases LED backlight intensity as ambient light increases.

Objective and use case

In this practical case, you will build a PWM (Pulse Width Modulation) controller using a 555 timer and a photoresistor (LDR). The circuit will automatically adjust the duty cycle of the output signal based on ambient light levels, driving a power MOSFET to dim an LED strip.

Why it is useful:
* Energy Efficiency: Reduces power consumption in high-brightness environments where backlights might be less visible or needed (depending on display type).
* Automatic Night-Lights: Useful for systems that need to be dim during the day and bright at night (if logic is inverted) or vice-versa.
* Human Vision Comfort: Prevents glare by adjusting light intensity dynamically.
* Instrumentation: Often used in automotive dashboards or control panels.

Expected outcome:
* Signal Generation: A square wave output at pin 3 of the 555 timer.
* Inverse Response: When the LDR is exposed to strong light (Flashlight), the LED brightness decreases.
* Dark Response: When the LDR is covered (Darkness), the LED brightness increases to maximum.
* Target Audience: Intermediate electronics students and hobbyists.

Materials

V1: 9 V DC voltage source, function: Main circuit power.
R1: Photoresistor (LDR), function: Light sensor (Charge path).
R2: 10 kΩ resistor, function: Discharge path timing.
R3: 1 kΩ resistor, function: MOSFET Gate protection.
R4: 330 Ω resistor, function: LED current limiting.
C1: 100 nF capacitor, function: PWM timing capacitor.
C2: 10 nF capacitor, function: Control voltage noise filtering.
D1: 1N4148 diode, function: Steering diode for Charge path.
D2: 1N4148 diode, function: Steering diode for Discharge path.
D3: High-brightness White LED, function: Simulated Backlight.
Q1: 2N7000 (N-Channel MOSFET), function: LED driver switch.
U1: NE555 Precision Timer, function: PWM generator.

Wiring guide

This guide uses specific node names (VCC, 0, V_TRIG, V_GATE, etc.) to help you verify connections.

Power Supply:
Connect V1 positive terminal to node VCC.
Connect V1 negative terminal to node 0 (GND).
555 Timer Power & Reset (U1):
Connect U1 pin 8 (VCC) to node VCC.
Connect U1 pin 1 (GND) to node 0.
Connect U1 pin 4 (Reset) to node VCC.
Timing Network (The PWM Core):
Connect R1 (LDR) between node VCC and node V_CHARGE.
Connect D1 (Anode) to V_CHARGE and D1 (Cathode) to node V_TIMING.
Connect D2 (Anode) to node V_TIMING and D2 (Cathode) to node V_DISCHARGE.
Connect R2 between node V_DISCHARGE and U1 pin 7 (Discharge).
Connect C1 between node V_TIMING and node 0.
Connect U1 pin 2 (Trigger) to node V_TIMING.
Connect U1 pin 6 (Threshold) to node V_TIMING.
Control Voltage:
Connect C2 between U1 pin 5 (CV) and node 0.
Output Stage:
Connect R3 between U1 pin 3 (Output) and node V_GATE.
Connect Q1 Gate to node V_GATE.
Connect Q1 Source to node 0.
Connect Q1 Drain to node V_LED_CATHODE.
Load (Backlight):
Connect R4 between node VCC and node V_LED_ANODE.
Connect D3 Anode to node V_LED_ANODE.
Connect D3 Cathode to node V_LED_CATHODE.

Conceptual block diagram

Schematic

Title: Practical case: Adaptive Screen Brightness Regulator

      [ INPUTS / TIMING NETWORK ]              [ LOGIC / CONTROL ]                 [ OUTPUT STAGE ]

[ V1: 9 V Source ] --(Power VCC)--------->+-----------------------+
                                         |                       |
(Light) -> [ R1: LDR ] --(Charge)------->|                       |
                                         |       U1: NE555       |
[ D1, D2, R2 ] --(Steering/Disch)------->|    (PWM Generator)    |--(Pin 3)--> [ R3: 1k ] --> [ Q1: MOSFET ]
                                         |                       |                                  |
[ C1: 100nF ] --(Timing Ramp)----------->|  Pins 2,6 (Trig/Thr)  |                                  |
                                         |  Pin 7 (Discharge)    |                           (Switches GND)
[ C2: 10nF ] --(Filter)----------------->|  Pin 5 (Ctrl Volt)    |                                  |
                                         |                       |                                  v
                                         +-----------------------+                       [ D3: LED + R4: 330R ]
                                                                                              (Backlight)

Schematic (ASCII)

Electrical diagram

Measurements and tests

Perform these steps to validate the «Inverse» behavior (More light = Less Brightness).

Baseline Check (Ambient Light):
- Power the circuit with 9 V.
- Observe the LED D3. It should be illuminated at a moderate level.
- Measure voltage at V_GATE using an oscilloscope. You should see a square wave.
High Light Test:
- Shine a flashlight directly onto R1 (LDR).
- Observation: The LED D3 should dim significantly or turn off.
- Measurement: Check the duty cycle at V_GATE. Since the LDR resistance drops, the capacitor charges very quickly (short Ton) relative to the fixed discharge time (Toff). The Duty Cycle (Ton / Ttotal) decreases.
Low Light Test:
- Cover R1 (LDR) with your hand or a black cap.
- Observation: The LED D3 should reach maximum brightness.
- Measurement: The LDR resistance increases, making the charge time (Ton) much longer. The Duty Cycle increases towards 100%.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Adaptive Screen Brightness Regulator

* --- Power Supply ---
V1 VCC 0 DC 9

* --- Input Stage (Light Sensor) ---
R1 VCC V_CHARGE 20k

* --- PWM Timing Network ---
D1 V_CHARGE V_TIMING D1N4148
D2 V_TIMING V_DISCHARGE D1N4148
R2 V_DISCHARGE V_DISCH_PIN 10k
C1 V_TIMING 0 100n

* --- Control & Processing ---
* U1: NE555 Precision Timer
XU1 0 V_TIMING V_OUT_PIN VCC V_CV V_TIMING V_DISCH_PIN VCC NE555

* Control Voltage noise filtering
C2 V_CV 0 10n
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔓 See premium access plans

* Practical case: Adaptive Screen Brightness Regulator

* --- Power Supply ---
V1 VCC 0 DC 9

* --- Input Stage (Light Sensor) ---
R1 VCC V_CHARGE 20k

* --- PWM Timing Network ---
D1 V_CHARGE V_TIMING D1N4148
D2 V_TIMING V_DISCHARGE D1N4148
R2 V_DISCHARGE V_DISCH_PIN 10k
C1 V_TIMING 0 100n

* --- Control & Processing ---
* U1: NE555 Precision Timer
XU1 0 V_TIMING V_OUT_PIN VCC V_CV V_TIMING V_DISCH_PIN VCC NE555

* Control Voltage noise filtering
C2 V_CV 0 10n

* --- Output Driver Stage ---
R3 V_OUT_PIN V_GATE 1k

* Q1: N-Channel MOSFET
MQ1 V_LED_CATHODE V_GATE 0 0 2N7000

* --- Load (Backlight) ---
R4 VCC V_LED_ANODE 330
D3 V_LED_ANODE V_LED_CATHODE WHITE_LED

* --- Component Models ---
.model D1N4148 D (IS=2.682n N=1.836 RS=.5664 BV=100 IBV=100p CJO=4p TT=11.54n)
.model 2N7000 NMOS (Level=1 VTO=2.1 KP=0.5 Lambda=0.002 RD=1.5 RS=1.5 CGSO=10p CGDO=10p CGBO=10p)
.model WHITE_LED D (IS=1p N=5 RS=5 BV=5 IBV=10u CJO=50p)

* --- NE555 Behavioral Subcircuit ---
.subckt NE555 GND TRIG OUT RESET CV THRES DISCH VCC
    * Internal Voltage Divider
    R_div1 VCC CV 5k
    R_div2 CV TR 5k
    R_div3 TR GND 5k

    * Comparators (Sigmoid-based for smooth convergence)
    * Set Signal (Active High) when TRIG < 1/3 VCC (V_TR)
    B_set set_node 0 V = 2.5 + 2.5 * tanh(100 * (V(TR) - V(TRIG)))

    * Reset Signal Logic
    * Condition 1: THRES > CV
    B_c1 c1 0 V = 0.5 * (1 + tanh(100 * (V(THRES) - V(CV))))
    * Condition 2: RESET < 1.0V
    B_c2 c2 0 V = 0.5 * (1 + tanh(100 * (1.0 - V(RESET))))
    * Combine (Probabilistic OR logic): V_rst = c1 + c2 - c1*c2, scaled to 5V
    B_rst rst_node 0 V = 5 * (V(c1) + V(c2) - V(c1)*V(c2))

    * RC Delays to prevent algebraic loops in Flip-Flop
    R_sd set_node set_d 1k
    C_sd set_d 0 1p
    R_rd rst_node rst_d 1k
    C_rd rst_d 0 1p

    * SR Latch (Cross-coupled NOR logic with soft thresholds)
    * Q = ~(R | Qb)
    B_q  q_int  0 V = 5 / (1 + exp( 20 * (V(rst_d) + V(qb_int) - 2.5) ))
    * Qb = ~(S | Q)
    B_qb qb_int 0 V = 5 / (1 + exp( 20 * (V(set_d) + V(q_int) - 2.5) ))

    * Output Buffer
    E_out OUT_int 0 q_int 0 1
    R_out_prot OUT_int OUT 1

    * Discharge Transistor (Switch to GND when Qb is High / Output Low)
    S_disch DISCH 0 qb_int 0 SW_DISCH
    .model SW_DISCH SW(Vt=2.5 Ron=10 Roff=100Meg)
.ends

* --- Simulation Directives ---
.tran 10u 20m
.print tran V(V_TIMING) V(V_GATE) V(V_LED_CATHODE) V(V_LED_ANODE)
.op
.end

Simulation Results (Transient Analysis)

Show raw data table (4016 rows)

Index   time            v(v_timing)     v(v_gate)       v(v_led_cathode
0	0.000000e+00	3.183820e+00	9.643749e-22	8.709822e+00
1	1.000000e-07	3.183820e+00	9.643749e-22	8.709822e+00
2	2.000000e-07	3.183820e+00	-2.54330e-17	8.709822e+00
3	4.000000e-07	3.183820e+00	4.759196e-18	8.709822e+00
4	8.000000e-07	3.183820e+00	-5.90561e-18	8.709822e+00
5	1.600000e-06	3.183820e+00	1.843922e-17	8.709822e+00
6	3.200000e-06	3.183820e+00	4.911091e-18	8.709822e+00
7	6.400000e-06	3.183819e+00	9.652751e-18	8.709822e+00
8	1.280000e-05	3.183819e+00	-2.42211e-18	8.709822e+00
9	2.280000e-05	3.183818e+00	-2.25892e-17	8.709822e+00
10	3.280000e-05	3.183818e+00	-5.29878e-18	8.709822e+00
11	4.280000e-05	3.183817e+00	-8.38426e-18	8.709822e+00
12	5.280000e-05	3.183816e+00	-5.24090e-18	8.709822e+00
13	6.280000e-05	3.183815e+00	5.344924e-18	8.709822e+00
14	7.280000e-05	3.183815e+00	-6.20163e-18	8.709822e+00
15	8.280000e-05	3.183814e+00	-2.95146e-18	8.709822e+00
16	9.280000e-05	3.183813e+00	-1.95605e-17	8.709822e+00
17	1.028000e-04	3.183813e+00	5.833300e-18	8.709822e+00
18	1.128000e-04	3.183812e+00	-9.79628e-18	8.709822e+00
19	1.228000e-04	3.183812e+00	1.090495e-18	8.709822e+00
20	1.328000e-04	3.183811e+00	-1.79618e-17	8.709822e+00
21	1.428000e-04	3.183810e+00	6.632650e-18	8.709822e+00
22	1.528000e-04	3.183810e+00	-1.47697e-17	8.709822e+00
23	1.628000e-04	3.183809e+00	6.958764e-18	8.709822e+00
... (3992 more rows) ...

Reference SPICE netlist (ngspice)

* Practical case: Adaptive Screen Brightness Regulator

* --- Power Supply ---
V1 VCC 0 DC 9

* --- Input Stage (Light Sensor) ---
R1 VCC V_CHARGE 20k

* --- PWM Timing Network ---
D1 V_CHARGE V_TIMING D1N4148
D2 V_TIMING V_DISCHARGE D1N4148
R2 V_DISCHARGE V_DISCH_PIN 10k
C1 V_TIMING 0 100n

* --- Control & Processing ---
* U1: NE555 Precision Timer
XU1 0 V_TIMING V_OUT_PIN VCC V_CV V_TIMING V_DISCH_PIN VCC NE555

* Control Voltage noise filtering
C2 V_CV 0 10n

* --- Output Driver Stage ---
R3 V_OUT_PIN V_GATE 1k

* Q1: N-Channel MOSFET
MQ1 V_LED_CATHODE V_GATE 0 0 2N7000

* --- Load (Backlight) ---
R4 VCC V_LED_ANODE 330
D3 V_LED_ANODE V_LED_CATHODE WHITE_LED

* --- Component Models ---
.model D1N4148 D (IS=2.682n N=1.836 RS=.5664 BV=100 IBV=100p CJO=4p TT=11.54n)
.model 2N7000 NMOS (Level=1 VTO=2.1 KP=0.5 Lambda=0.002 RD=1.5 RS=1.5 CGSO=10p CGDO=10p CGBO=10p)
.model WHITE_LED D (IS=1p N=5 RS=5 BV=5 IBV=10u CJO=50p)

* --- NE555 Behavioral Subcircuit ---
.subckt NE555 GND TRIG OUT RESET CV THRES DISCH VCC
    * Internal Voltage Divider
    R_div1 VCC CV 5k
    R_div2 CV TR 5k
    R_div3 TR GND 5k

    * Comparators (Sigmoid-based for smooth convergence)
    * Set Signal (Active High) when TRIG  CV
    B_c1 c1 0 V = 0.5 * (1 + tanh(100 * (V(THRES) - V(CV))))
    * Condition 2: RESET < 1.0V
    B_c2 c2 0 V = 0.5 * (1 + tanh(100 * (1.0 - V(RESET))))
    * Combine (Probabilistic OR logic): V_rst = c1 + c2 - c1*c2, scaled to 5V
    B_rst rst_node 0 V = 5 * (V(c1) + V(c2) - V(c1)*V(c2))

    * RC Delays to prevent algebraic loops in Flip-Flop
    R_sd set_node set_d 1k
    C_sd set_d 0 1p
    R_rd rst_node rst_d 1k
    C_rd rst_d 0 1p

    * SR Latch (Cross-coupled NOR logic with soft thresholds)
    * Q = ~(R | Qb)
    B_q  q_int  0 V = 5 / (1 + exp( 20 * (V(rst_d) + V(qb_int) - 2.5) ))
    * Qb = ~(S | Q)
    B_qb qb_int 0 V = 5 / (1 + exp( 20 * (V(set_d) + V(q_int) - 2.5) ))

    * Output Buffer
    E_out OUT_int 0 q_int 0 1
    R_out_prot OUT_int OUT 1

    * Discharge Transistor (Switch to GND when Qb is High / Output Low)
    S_disch DISCH 0 qb_int 0 SW_DISCH
    .model SW_DISCH SW(Vt=2.5 Ron=10 Roff=100Meg)
.ends

* --- Simulation Directives ---
.tran 10u 20m
.print tran V(V_TIMING) V(V_GATE) V(V_LED_CATHODE) V(V_LED_ANODE)
.op
.end

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

Reversing Steering Diodes (D1, D2):
- Error: Placing D1 or D2 backwards prevents the capacitor from charging or discharging properly.
- Solution: Ensure the black band (cathode) of D1 points towards the capacitor and the black band of D2 points towards Pin 7.
Connecting LDR to Pin 7 directly:
- Error: Connecting the LDR without the steering diodes creates a standard astable oscillator where frequency changes drastically, but duty cycle control is less distinct.
- Solution: Use the diode steering topology described to separate the Charge (LDR) and Discharge (R2) paths.
MOSFET Pinout Confusion:
- Error: Swapping Drain and Source on the 2N7000.
- Solution: Verify the datasheet. For 2N7000 (TO-92), looking at the flat side, pins are usually Source, Gate, Drain (left to right).

Troubleshooting

Symptom: LED is always ON and does not change with light.
- Cause: MOSFET Gate floating or Pin 3 stuck High.
- Fix: Check R1 and C1 connections. Ensure Pin 2 and 6 are tied together.
Symptom: LED is always OFF.
- Cause: LDR resistance is too low (short circuit) or LED connected backwards.
- Fix: Check LED polarity. Measure resistance of LDR in darkness; if it is 0 Ω, it is defective.
Symptom: LED flickers visibly.
- Cause: Frequency is too low.
- Fix: Reduce the value of C1 (e.g., change from 100 nF to 10 nF) to increase the PWM frequency beyond human persistence of vision (> 100 Hz).

Possible improvements and extensions

Minimum Brightness Clamp: Add a fixed resistor in series with the LDR (R1). This ensures that even in extremely bright light (low LDR resistance), there is still a minimum charge time, preventing the LED from turning off completely.
Smoother Transition: Add a large capacitor across the LDR to filter out rapid changes in light (e.g., shadows from passing objects), creating a «fade» effect rather than an instant jump in brightness.

More Practical Cases on Prometeo.blog

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As an Amazon Associate, I earn from qualifying purchases. If you buy through this link, you help keep this project running.

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Practical case: Single-axis solar tracker

Single-axis solar tracker prototype (Maker Style)

Level: Medium. Design a control circuit that compares light levels from two sensors to orient a motor towards the brightest light source.

Objective and use case

This practical case guides you through building an analog control loop that automatically orients a mechanism towards a light source using photoresistors (LDRs) and operational amplifiers. You will construct a «sun seeker» that actively balances two light inputs to drive a motor in the corresponding direction.

Real-world applications:
Solar Energy: Increases photovoltaic panel efficiency by keeping panels perpendicular to the sun throughout the day.
Robotics: Enables light-seeking behaviors (phototaxis) in autonomous robots.
Home Automation: Controls smart blinds to regulate room temperature based on sunlight intensity.
Expected outcome:
When the light source is balanced, the motor remains stationary.
When LDR1 is shaded, the voltage difference triggers the motor to spin Clockwise (CW).
When LDR2 is shaded, the motor spins Counter-Clockwise (CCW).
Target audience: Electronics students familiar with voltage dividers and OpAmps.

Materials

V1: 9 V DC power supply (Power source).
R1: Photoresistor (LDR), function: Left light sensor.
R2: Photoresistor (LDR), function: Right light sensor.
R3: 10 kΩ resistor, function: Voltage divider bottom leg for R1.
R4: 10 kΩ resistor, function: Voltage divider bottom leg for R2.
U1: LM358, function: Dual Operational Amplifier (Comparators).
U2: L293D, function: H-Bridge Motor Driver IC.
M1: 9 V DC Gear Motor, function: Tracking actuator.
C1: 100 nF capacitor, function: Power supply decoupling.

Wiring guide

This circuit uses two parallel voltage dividers compared by two OpAmps to determine motor direction.

Power Supply:
Connect V1 positive terminal to node VCC.
Connect V1 negative terminal to node GND (0).
Connect C1 between VCC and GND.
Sensors (Dual Voltage Divider):
Connect R1 (LDR Left) between VCC and node VA (Sensor Voltage A).
Connect R3 between VA and GND.
Connect R2 (LDR Right) between VCC and node VB (Sensor Voltage B).
Connect R4 between VB and GND.
Comparators (LM358 – U1):
Comparator A (Turn Right/CW Logic):
- Connect U1 Non-inverting input (+) to node VA.
- Connect U1 Inverting input (-) to node VB.
- Connect U1 Output A to node SIG_CW.
Comparator B (Turn Left/CCW Logic):
- Connect U1 Non-inverting input (+) to node VB.
- Connect U1 Inverting input (-) to node VA.
- Connect U1 Output B to node SIG_CCW.
Connect U1 VCC pin to VCC and GND pin to GND.
Motor Driver (L293D – U2):
Connect U2 Input 1 to node SIG_CW.
Connect U2 Input 2 to node SIG_CCW.
Connect U2 Enable 1 pin to VCC.
Connect U2 Output 1 to node M_POS.
Connect U2 Output 2 to node M_NEG.
Connect U2 VCC1 (Logic) and VCC2 (Power) to VCC.
Connect U2 GND pins to GND.
Actuator:
Connect M1 (Motor) between nodes M_POS and M_NEG.

Conceptual block diagram

Schematic

[ INPUTS / SENSORS ]               [ LOGIC / PROCESSING ]                  [ ACTUATOR ]

   [ Power Supply Block ]
   [ Source: V1 (9 V)    ] --(VCC/GND Power)--> (Distributes to all ICs and Sensors)
   [ Filter: C1 (100nF) ]

                                         [ U1: LM358 Dual OpAmp ]
                                         |                      |
   [ Left Light Sensor  ]                | Comparator A (Logic) |
   [ Top: R1 (LDR)      ] --(Signal VA)->| Input: VA > VB ?     |--(SIG_CW)--->+
   [ Bot: R3 (10k Ohm)  ]                | Output: Turn CW      |              |
                                         |                      |              |
                                         |                      |              v
                                         | Comparator B (Logic) |      [ U2: L293D H-Bridge ]
   [ Right Light Sensor ]                | Input: VB > VA ?     |      |                    |
   [ Top: R2 (LDR)      ] --(Signal VB)->| Output: Turn CCW     |      | Input 1: CW Sig    |
   [ Bot: R4 (10k Ohm)  ]                |                      |      | Input 2: CCW Sig   |===(High Current)==> [ M1: Gear Motor ]
                                         +----------+-----------+      | Enable: VCC        |      (9 V DC)
                                                    |                  | VCC1/VCC2: 9 V      |
                                                    +--(SIG_CCW)------>| GND: Common        |
                                                                       +--------------------+

Schematic (ASCII)

Electrical diagram

Measurements and tests

Follow these steps to validate the tracker logic:

Static Equilibrium Test:
- Expose both LDRs to ambient light equally.
- Measure the voltage at node VA and VB. They should be approximately equal.
- Measure SIG_CW and SIG_CCW. Both should be Low (approx. 0 V) or balanced, keeping the motor stopped.
Left Shade Simulation:
- Cover R1 (Left LDR) with your hand.
- Observation: The resistance of R1 increases, causing voltage at VA to drop.
- Logic Check: Since VB > VA, Comparator B (Non-inverting = VB) should go High (SIG_CCW ≈ VCC).
- Actuator: The motor should spin Counter-Clockwise.
Right Shade Simulation:
- Expose R1 to light and cover R2 (Right LDR).
- Observation: The resistance of R2 increases, causing voltage at VB to drop.
- Logic Check: Since VA > VB, Comparator A (Non-inverting = VA) should go High (SIG_CW ≈ VCC).
- Actuator: The motor should spin Clockwise.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Single-axis Solar Tracker Simulation
* Based on Practical Electronics Breadboard Case

* --- Power Supply ---
* V1: 9 V DC power supply
V1 VCC 0 DC 9V
* C1: 100 nF capacitor (Decoupling)
C1 VCC 0 100nF

* --- Dynamic Light Stimulus (Virtual Control) ---
* This source simulates the position of the sun moving from Left to Right.
* 0V = Light on Left Sensor, 5V = Light on Right Sensor.
* Sweeps linearly from 0V to 5V over 100ms.
V_LIGHT LIGHT_POS 0 PWL(0 0 100m 5)

* --- Sensors (LDRs) ---
* Modeled as voltage-dependent resistors controlled by LIGHT_POS.
* R1 (Left LDR): Resistance increases as Light moves Right (LIGHT_POS increases).
* Range: 1k (Bright) to 50k (Dark).
R1 VCC VA R = '1k + 49k * (V(LIGHT_POS)/5)'
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Single-axis Solar Tracker Simulation
* Based on Practical Electronics Breadboard Case

* --- Power Supply ---
* V1: 9 V DC power supply
V1 VCC 0 DC 9V
* C1: 100 nF capacitor (Decoupling)
C1 VCC 0 100nF

* --- Dynamic Light Stimulus (Virtual Control) ---
* This source simulates the position of the sun moving from Left to Right.
* 0V = Light on Left Sensor, 5V = Light on Right Sensor.
* Sweeps linearly from 0V to 5V over 100ms.
V_LIGHT LIGHT_POS 0 PWL(0 0 100m 5)

* --- Sensors (LDRs) ---
* Modeled as voltage-dependent resistors controlled by LIGHT_POS.
* R1 (Left LDR): Resistance increases as Light moves Right (LIGHT_POS increases).
* Range: 1k (Bright) to 50k (Dark).
R1 VCC VA R = '1k + 49k * (V(LIGHT_POS)/5)'

* R2 (Right LDR): Resistance decreases as Light moves Right.
* Range: 50k (Dark) to 1k (Bright).
R2 VCC VB R = '1k + 49k * (1 - V(LIGHT_POS)/5)'

* --- Voltage Divider Bottom Legs ---
* R3: 10 kΩ resistor for R1
R3 VA 0 10k
* R4: 10 kΩ resistor for R2
R4 VB 0 10k

* --- Comparators (U1: LM358) ---
* U1 is a Dual OpAmp. We define a subcircuit matching the 8-pin DIP pinout.
* Pinout: 1=OutA, 2=In-A, 3=In+A, 4=GND, 5=In+B, 6=In-B, 7=OutB, 8=VCC
* Wiring Guide:
* Comparator A (CW): (+) VA, (-) VB -> Out SIG_CW
* Comparator B (CCW): (+) VB, (-) VA -> Out SIG_CCW
XU1 SIG_CW VB VA 0 VB VA SIG_CCW VCC LM358_DIP8

* --- Motor Driver (U2: L293D) ---
* U2 is an H-Bridge Driver. We define a subcircuit for the used pins.
* Pinout used: 1=EN1, 2=IN1, 3=OUT1, 4/5=GND, 6=OUT2, 7=IN2, 8=VCC2, 16=VCC1
* Wiring Guide:
* IN1=SIG_CW, IN2=SIG_CCW, OUT1=M_POS, OUT2=M_NEG, EN1=VCC
XU2 VCC SIG_CW M_POS 0 0 M_NEG SIG_CCW VCC VCC L293D_BRIDGE

* --- Actuator (M1: 9V DC Gear Motor) ---
* Modeled as a resistive/inductive load.
R_M1 M_POS M_INT 20
L_M1 M_INT M_NEG 5mH

* --- Subcircuit Definitions ---

.subckt LM358_DIP8 OUTA INMA INPA GND INPB INMB OUTB VCC
* Comparator A Behavior (Sigmoid for convergence)
* Output swings approx 0V to VCC-1.5V
B_OUTA OUTA 0 V = (V(VCC)-1.5) / (1 + exp(-50*(V(INPA)-V(INMA)))) + 0.05
* Comparator B Behavior
B_OUTB OUTB 0 V = (V(VCC)-1.5) / (1 + exp(-50*(V(INPB)-V(INMB)))) + 0.05
.ends

.subckt L293D_BRIDGE EN1 IN1 OUT1 GND1 GND2 OUT2 IN2 VCC2 VCC1
* Logic Threshold approx 2.0V.
* Output Voltage ~ VCC2 - 1.4V drop.
* Enable Logic
B_EN node_en 0 V = 1 / (1 + exp(-50*(V(EN1)-2.0)))
* Output 1 (M_POS)
B_O1 OUT1 0 V = V(node_en) * (1/(1+exp(-50*(V(IN1)-2.0)))) * (V(VCC2)-1.4)
* Output 2 (M_NEG)
B_O2 OUT2 0 V = V(node_en) * (1/(1+exp(-50*(V(IN2)-2.0)))) * (V(VCC2)-1.4)
.ends

* --- Simulation Directives ---
.op
* Transient analysis: 100ms duration to capture the full light sweep
.tran 100u 100m

* Print signals to verify logic:
* VA/VB: Sensor Voltages
* SIG_CW/CCW: Comparator Logic Outputs
* M_POS/M_NEG: Motor Drive Voltages
.print tran V(VA) V(VB) V(SIG_CW) V(SIG_CCW) V(M_POS) V(M_NEG) V(LIGHT_POS)

.end

Simulation Results (Transient Analysis)

Show raw data table (3024 rows)

Index   time            v(va)           v(vb)           v(sig_cw)
0	0.000000e+00	8.181818e+00	1.500000e+00	7.550000e+00
1	1.000000e-06	8.181454e+00	1.500012e+00	7.550000e+00
2	2.000000e-06	8.181089e+00	1.500025e+00	7.550000e+00
3	4.000000e-06	8.180361e+00	1.500049e+00	7.550000e+00
4	8.000000e-06	8.178903e+00	1.500098e+00	7.550000e+00
5	1.600000e-05	8.175990e+00	1.500196e+00	7.550000e+00
6	3.200000e-05	8.170168e+00	1.500392e+00	7.550000e+00
7	6.400000e-05	8.158542e+00	1.500784e+00	7.550000e+00
8	1.280000e-04	8.135365e+00	1.501569e+00	7.550000e+00
9	2.280000e-04	8.099394e+00	1.502797e+00	7.550000e+00
10	3.280000e-04	8.063833e+00	1.504028e+00	7.550000e+00
11	4.280000e-04	8.028586e+00	1.505260e+00	7.550000e+00
12	5.280000e-04	7.993645e+00	1.506495e+00	7.550000e+00
13	6.280000e-04	7.959008e+00	1.507732e+00	7.550000e+00
14	7.280000e-04	7.924669e+00	1.508970e+00	7.550000e+00
15	8.280000e-04	7.890626e+00	1.510211e+00	7.550000e+00
16	9.280000e-04	7.856873e+00	1.511454e+00	7.550000e+00
17	1.028000e-03	7.823409e+00	1.512699e+00	7.550000e+00
18	1.128000e-03	7.790228e+00	1.513945e+00	7.550000e+00
19	1.228000e-03	7.757327e+00	1.515194e+00	7.550000e+00
20	1.328000e-03	7.724703e+00	1.516445e+00	7.550000e+00
21	1.428000e-03	7.692352e+00	1.517698e+00	7.550000e+00
22	1.528000e-03	7.660271e+00	1.518953e+00	7.550000e+00
23	1.628000e-03	7.628457e+00	1.520211e+00	7.550000e+00
... (3000 more rows) ...

Reference SPICE netlist (ngspice)

* Single-axis Solar Tracker Simulation
* Based on Practical Electronics Breadboard Case

* --- Power Supply ---
* V1: 9 V DC power supply
V1 VCC 0 DC 9V
* C1: 100 nF capacitor (Decoupling)
C1 VCC 0 100nF

* --- Dynamic Light Stimulus (Virtual Control) ---
* This source simulates the position of the sun moving from Left to Right.
* 0V = Light on Left Sensor, 5V = Light on Right Sensor.
* Sweeps linearly from 0V to 5V over 100ms.
V_LIGHT LIGHT_POS 0 PWL(0 0 100m 5)

* --- Sensors (LDRs) ---
* Modeled as voltage-dependent resistors controlled by LIGHT_POS.
* R1 (Left LDR): Resistance increases as Light moves Right (LIGHT_POS increases).
* Range: 1k (Bright) to 50k (Dark).
R1 VCC VA R = '1k + 49k * (V(LIGHT_POS)/5)'

* R2 (Right LDR): Resistance decreases as Light moves Right.
* Range: 50k (Dark) to 1k (Bright).
R2 VCC VB R = '1k + 49k * (1 - V(LIGHT_POS)/5)'

* --- Voltage Divider Bottom Legs ---
* R3: 10 kΩ resistor for R1
R3 VA 0 10k
* R4: 10 kΩ resistor for R2
R4 VB 0 10k

* --- Comparators (U1: LM358) ---
* U1 is a Dual OpAmp. We define a subcircuit matching the 8-pin DIP pinout.
* Pinout: 1=OutA, 2=In-A, 3=In+A, 4=GND, 5=In+B, 6=In-B, 7=OutB, 8=VCC
* Wiring Guide:
* Comparator A (CW): (+) VA, (-) VB -> Out SIG_CW
* Comparator B (CCW): (+) VB, (-) VA -> Out SIG_CCW
XU1 SIG_CW VB VA 0 VB VA SIG_CCW VCC LM358_DIP8

* --- Motor Driver (U2: L293D) ---
* U2 is an H-Bridge Driver. We define a subcircuit for the used pins.
* Pinout used: 1=EN1, 2=IN1, 3=OUT1, 4/5=GND, 6=OUT2, 7=IN2, 8=VCC2, 16=VCC1
* Wiring Guide:
* IN1=SIG_CW, IN2=SIG_CCW, OUT1=M_POS, OUT2=M_NEG, EN1=VCC
XU2 VCC SIG_CW M_POS 0 0 M_NEG SIG_CCW VCC VCC L293D_BRIDGE

* --- Actuator (M1: 9V DC Gear Motor) ---
* Modeled as a resistive/inductive load.
R_M1 M_POS M_INT 20
L_M1 M_INT M_NEG 5mH

* --- Subcircuit Definitions ---

.subckt LM358_DIP8 OUTA INMA INPA GND INPB INMB OUTB VCC
* Comparator A Behavior (Sigmoid for convergence)
* Output swings approx 0V to VCC-1.5V
B_OUTA OUTA 0 V = (V(VCC)-1.5) / (1 + exp(-50*(V(INPA)-V(INMA)))) + 0.05
* Comparator B Behavior
B_OUTB OUTB 0 V = (V(VCC)-1.5) / (1 + exp(-50*(V(INPB)-V(INMB)))) + 0.05
.ends

.subckt L293D_BRIDGE EN1 IN1 OUT1 GND1 GND2 OUT2 IN2 VCC2 VCC1
* Logic Threshold approx 2.0V.
* Output Voltage ~ VCC2 - 1.4V drop.
* Enable Logic
B_EN node_en 0 V = 1 / (1 + exp(-50*(V(EN1)-2.0)))
* Output 1 (M_POS)
B_O1 OUT1 0 V = V(node_en) * (1/(1+exp(-50*(V(IN1)-2.0)))) * (V(VCC2)-1.4)
* Output 2 (M_NEG)
B_O2 OUT2 0 V = V(node_en) * (1/(1+exp(-50*(V(IN2)-2.0)))) * (V(VCC2)-1.4)
.ends

* --- Simulation Directives ---
.op
* Transient analysis: 100ms duration to capture the full light sweep
.tran 100u 100m

* Print signals to verify logic:
* VA/VB: Sensor Voltages
* SIG_CW/CCW: Comparator Logic Outputs
* M_POS/M_NEG: Motor Drive Voltages
.print tran V(VA) V(VB) V(SIG_CW) V(SIG_CCW) V(M_POS) V(M_NEG) V(LIGHT_POS)

.end

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

LDRs placed too close together:
- Symptom: The system is insensitive and requires extreme light angles to react.
- Solution: Mount the LDRs with a physical blinder (a piece of cardboard or plastic) between them so a shadow is cast on one LDR when the light is not perfectly centered.
Driving the motor directly from OpAmps:
- Symptom: The motor hums but doesn’t turn, or the OpAmp overheats and fails.
- Solution: Always use a current driver stage like the L293D or a transistor H-Bridge. OpAmps cannot supply the current required by motors (typically >100 mA).
Lack of Deadband (Jittering):
- Symptom: The motor constantly vibrates back and forth when the light is centered.
- Solution: This basic topology is a «bang-bang» controller. In advanced designs, add hysteresis resistors to the OpAmps to create a small voltage window where the motor remains off.

Troubleshooting

Motor spins in the wrong direction:
- Cause: The motor polarity is reversed relative to the sensor placement.
- Fix: Swap the connections of M1 (M_POS and M_NEG) OR physically swap the positions of R1 and R2.
Motor runs continuously even in equal light:
- Cause: Large tolerance difference between the two LDRs or fixed resistors (R3/R4).
- Fix: Replace one fixed resistor (e.g., R3) with a 10k trim potentiometer to calibrate the bridge balance manually.
Nothing happens when light changes:
- Cause: L293D Enable pin not connected high.
- Fix: Ensure the Enable pin of the driver is connected to VCC.

Possible improvements and extensions

Sensitivity Control: Replace the fixed resistors R3 and R4 with a single multi-turn potentiometer. Connect the wiper to ground and the ends to the LDRs to allow fine-tuning of the center point.
Solar Power Integration: Replace V1 with a small solar panel and a charging circuit to make the tracker self-sustaining.

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Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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