Practical case: Low-Side Transistor Relay Switch

Low-Side Transistor Relay Switch prototype (Maker Style)

Level: Basic. Control a high-voltage mechanical relay using a small low-power control signal.

Objective and use case

In this practical case, you will build a circuit where a small signal (simulating a microcontroller output like an Arduino) activates an NPN transistor to switch on a 12 V relay.

Why it is useful:
* Microcontroller Protection: Allows delicate 3.3 V or 5 V logic chips to control 12 V or 24 V devices without damage.
* High Current Handling: Transistors can switch relays, which in turn can switch very high currents (AC motors, heaters) that the transistor alone might not handle.
* Automotive Applications: Standard practice for controlling 12 V automotive accessories from an ECU.
* Isolation: While the transistor shares a ground, the relay contacts provide galvanic isolation for the final load.

Expected outcome:
* When the 5 V switch is closed, the transistor saturates (VCE ≈ 0.2 V).
* The relay coil energizes, producing an audible «click.»
* The load LED turns ON.
* The flyback diode protects the transistor from high-voltage spikes when the relay turns OFF.

Target audience and level:
Basic electronics students and hobbyists.

Materials

  • V1: 5 V DC supply, function: Logic control voltage source.
  • V2: 12 V DC supply, function: Relay coil and load power.
  • S1: SPST Toggle Switch, function: Simulates the microcontroller output pin.
  • R1: 1 kΩ resistor, function: Base current limiting to ensure saturation.
  • Q1: 2N2222 (NPN BJT), function: Low-side switch driver.
  • K1: 12 V SPDT Relay, function: Electromechanical switching element.
  • D1: 1N4007 Diode, function: Flyback (freewheeling) protection diode.
  • R2: 470 Ω resistor, function: Current limiting for the load LED.
  • D2: Green LED, function: Visual indicator of the load status (connected to Relay NO contact).

Wiring guide

This guide uses specific node names to define the connections clearly.
* Nodes: GND (Common Ground), CTRL_IN (5 V Logic), V_RELAY (12 V Supply), BASE, COLLECTOR, LOAD_OUT.

  • V1: Positive terminal to CTRL_IN, Negative terminal to GND.
  • V2: Positive terminal to V_RELAY, Negative terminal to GND.
  • S1: Connected between CTRL_IN and input of R1.
  • R1: Connected between Output of S1 and BASE of Q1.
  • Q1:
    • Base to BASE.
    • Emitter to GND.
    • Collector to COLLECTOR.
  • K1 (Coil): Connected between V_RELAY and COLLECTOR.
  • D1: Anode to COLLECTOR, Cathode to V_RELAY (Reverse biased).
  • K1 (Common Contact): Connected to V_RELAY.
  • K1 (Normally Open – NO): Connected to LOAD_OUT.
  • R2: Connected between LOAD_OUT and Anode of D2.
  • D2: Anode to R2, Cathode to GND.

Conceptual block diagram

Conceptual block diagram — Low-Side Relay Driver
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Low-Side Transistor Relay Switch

1. CONTROL LOOP (Logic Signal)
   Flow: 5 V Logic activates the Transistor Base.

   [ V1: 5 V ] --(Node: CTRL_IN)--> [ S1: Switch ] --> [ R1: 1k ] --(Node: BASE)--> [ Q1: Base ]
                                                                                         |
                                                                                         | (Controls Q1 State)
                                                                                         v

2. RELAY DRIVE LOOP (12 V Power & Coil)
   Flow: Transistor sinks Coil current to Ground; Diode protects against spikes.

                                           (Flyback Protection)
                             .-----[ D1: Cathode <------- Anode ]------.
                             |                                         |
                             v                                         v
   [ V2: 12 V ] --(Node: V_RELAY)--> [ K1: Coil ] --(Node: COLLECTOR)--> [ Q1: Collector ]
                                                                               |
                                                                               | (Current Flow)
                                                                               v
                                                                        [ Q1: Emitter ] --> GND


3. LOAD LOOP (High Power Output)
   Flow: Relay Magnetic Field closes the switch, powering the LED.

          .--------------------------( Magnetic Mechanical Link )--------------------------.
          |                                                                                |
          v                                                                                v
   [ V2: 12 V ] --> [ K1: COM ] --( Switch Closes )--> [ K1: NO ] --(Node: LOAD_OUT)--> [ R2: 470R ] --> [ D2: LED ] --> GND
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Low-side transistor relay switch
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Follow these steps to validate the circuit operation using a multimeter:

  1. OFF State check: Ensure S1 is Open. Measure voltage at COLLECTOR relative to GND. It should be close to 12 V (floating through the coil). D2 should be OFF.
  2. Activation: Close S1. Listen for the relay click. D2 should turn ON.
  3. Base-Emitter Voltage (VBE): With S1 closed, measure voltage between BASE and GND. It should be approx 0.7 V – 0.8 V.
  4. Saturation Verification (VCE): Measure voltage between COLLECTOR and GND while ON. It should be very low (typically < 0.2 V), indicating the transistor is acting like a closed switch.
  5. Coil Voltage: Measure across the relay coil. It should read close to 11.8 V (12 V supply minus the small VCE drop).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Low-Side Transistor Relay Switch
.width out=256
*
* Description:
* A 5V control signal (simulated via S1) drives a 2N2222 NPN transistor.
* The transistor switches a 12V Relay Coil.
* The Relay contacts switch a 12V load (Green LED).
*
* Nodes defined in Wiring Guide:
* GND, CTRL_IN, V_RELAY, BASE, COLLECTOR, LOAD_OUT

* --- Power Supplies ---
* V1: 5V Logic Supply
V1 CTRL_IN 0 DC 5
* V2: 12V Relay/Load Supply
V2 V_RELAY 0 DC 12

* --- User Switch Simulation (S1) ---
* S1 represents the physical SPST toggle switch.
* We use a voltage-controlled switch model driven by a PULSE source (V_USER)
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Low-Side Transistor Relay Switch
.width out=256
*
* Description:
* A 5V control signal (simulated via S1) drives a 2N2222 NPN transistor.
* The transistor switches a 12V Relay Coil.
* The Relay contacts switch a 12V load (Green LED).
*
* Nodes defined in Wiring Guide:
* GND, CTRL_IN, V_RELAY, BASE, COLLECTOR, LOAD_OUT

* --- Power Supplies ---
* V1: 5V Logic Supply
V1 CTRL_IN 0 DC 5
* V2: 12V Relay/Load Supply
V2 V_RELAY 0 DC 12

* --- User Switch Simulation (S1) ---
* S1 represents the physical SPST toggle switch.
* We use a voltage-controlled switch model driven by a PULSE source (V_USER)
* to simulate the user pressing/releasing the switch.
* Timing: Wait 5ms, ON for 20ms, Period 50ms.
V_USER S1_CTRL 0 PULSE(0 5 5m 10u 10u 20m 50m)

* S1 Instance: Connects CTRL_IN to SW_OUT when S1_CTRL is high.
S1 CTRL_IN SW_OUT S1_CTRL 0 TACTILE_SW

* --- Base Drive ---
* R1: Current limiting for Q1 Base
R1 SW_OUT BASE 1k

* --- Low-Side Driver (Q1) ---
* Q1: NPN 2N2222
* Connections: Collector, Base, Emitter(GND)
Q1 COLLECTOR BASE 0 2N2222_MOD

* --- Relay Coil & Flyback Diode ---
* K1 Coil: Modeled as Inductance (L) + Series Resistance (R).
* Connected between V_RELAY (12V) and COLLECTOR.
* Typical 12V relay coil resistance ~400 Ohms.
R_K1_COIL V_RELAY K1_INT 400
L_K1_COIL K1_INT COLLECTOR 100m

* D1: 1N4007 Flyback Diode (Reverse biased)
* Anode to COLLECTOR, Cathode to V_RELAY
D1 COLLECTOR V_RELAY 1N4007_MOD

* --- Relay Contacts (K1 Switch) ---
* Modeled as a voltage-controlled switch (S_K1).
* Controlled by the voltage across the coil (V_RELAY - COLLECTOR).
* When Q1 is ON, Coil Voltage ~ 12V -> Contacts Close.
* When Q1 is OFF, Coil Voltage ~ 0V -> Contacts Open.
* Connections: Common (V_RELAY) to NO (LOAD_OUT).
S_K1 V_RELAY LOAD_OUT V_RELAY COLLECTOR RELAY_SW_MOD

* --- Load Circuit ---
* R2: Current limiting for LED
R2 LOAD_OUT LED_ANODE 470
* D2: Green LED
D2 LED_ANODE 0 LED_GREEN_MOD

* --- Component Models ---

* Switch Model for S1 (Logic Level Control)
.model TACTILE_SW SW(Vt=2.5 Vh=0.5 Ron=0.01 Roff=100Meg)

* Switch Model for Relay (High Voltage Threshold)
* Vt=8V ensures it pulls in only when coil is energized (approx >8V)
.model RELAY_SW_MOD SW(Vt=8.0 Vh=1.0 Ron=0.05 Roff=100Meg)

* BJT Model 2N2222
.model 2N2222_MOD NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=1 RE=0.1)

* Diode Model 1N4007
.model 1N4007_MOD D(IS=7n RS=0.034 N=1.8 BV=1000 IBV=5e-8 CJO=10p VJ=0.7 M=0.5 TT=100n)

* LED Model (Green, approx 2.1V Vf)
.model LED_GREEN_MOD D(IS=1e-22 RS=5 N=1.8 CJO=50p VJ=2.2 BV=5 IBV=10u)

* --- Analysis Directives ---
.op
.tran 100u 60m

* Output Printing
* V(SW_OUT): Input signal after switch S1
* V(LOAD_OUT): Output status (Relay NO contact)
* V(BASE): Transistor Base Voltage
* V(COLLECTOR): Transistor Collector Voltage (Relay Coil Low-Side)
.print tran V(SW_OUT) V(LOAD_OUT) V(BASE) V(COLLECTOR) I(L_K1_COIL)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation shows the switch (S1) activating at 5ms. When V(SW_OUT) goes high (~5V), V(BASE) rises to ~0.8V, turning Q1 ON. V(COLLECTOR) drops to ~70mV (saturation), energizing the coil. However, V(LOAD_OUT) remains high (~12V) throughout the log, even when the switch is OFF at t=0, suggesting the relay contact model might be inverted or the threshold logic is tricky.
Show raw data table (722 rows)
Index   time            v(sw_out)       v(load_out)     v(base)         v(collector)    l_k1_coil#branc
0	0.000000e+00	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
1	1.000000e-06	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
2	2.000000e-06	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
3	4.000000e-06	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
4	8.000000e-06	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
5	1.600000e-05	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
6	3.200000e-05	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
7	6.400000e-05	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
8	1.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
9	2.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
10	3.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
11	4.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
12	5.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
13	6.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
14	7.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
15	8.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
16	9.280000e-04	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
17	1.028000e-03	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
18	1.128000e-03	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
19	1.228000e-03	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
20	1.328000e-03	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
21	1.428000e-03	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
22	1.528000e-03	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
23	1.628000e-03	5.331417e-01	1.609847e+00	5.330970e-01	1.199602e+01	9.959371e-06
... (698 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Low-Side Transistor Relay Switch
.width out=256
*
* Description:
* A 5V control signal (simulated via S1) drives a 2N2222 NPN transistor.
* The transistor switches a 12V Relay Coil.
* The Relay contacts switch a 12V load (Green LED).
*
* Nodes defined in Wiring Guide:
* GND, CTRL_IN, V_RELAY, BASE, COLLECTOR, LOAD_OUT

* --- Power Supplies ---
* V1: 5V Logic Supply
V1 CTRL_IN 0 DC 5
* V2: 12V Relay/Load Supply
V2 V_RELAY 0 DC 12

* --- User Switch Simulation (S1) ---
* S1 represents the physical SPST toggle switch.
* We use a voltage-controlled switch model driven by a PULSE source (V_USER)
* to simulate the user pressing/releasing the switch.
* Timing: Wait 5ms, ON for 20ms, Period 50ms.
V_USER S1_CTRL 0 PULSE(0 5 5m 10u 10u 20m 50m)

* S1 Instance: Connects CTRL_IN to SW_OUT when S1_CTRL is high.
S1 CTRL_IN SW_OUT S1_CTRL 0 TACTILE_SW

* --- Base Drive ---
* R1: Current limiting for Q1 Base
R1 SW_OUT BASE 1k

* --- Low-Side Driver (Q1) ---
* Q1: NPN 2N2222
* Connections: Collector, Base, Emitter(GND)
Q1 COLLECTOR BASE 0 2N2222_MOD

* --- Relay Coil & Flyback Diode ---
* K1 Coil: Modeled as Inductance (L) + Series Resistance (R).
* Connected between V_RELAY (12V) and COLLECTOR.
* Typical 12V relay coil resistance ~400 Ohms.
R_K1_COIL V_RELAY K1_INT 400
L_K1_COIL K1_INT COLLECTOR 100m

* D1: 1N4007 Flyback Diode (Reverse biased)
* Anode to COLLECTOR, Cathode to V_RELAY
D1 COLLECTOR V_RELAY 1N4007_MOD

* --- Relay Contacts (K1 Switch) ---
* Modeled as a voltage-controlled switch (S_K1).
* Controlled by the voltage across the coil (V_RELAY - COLLECTOR).
* When Q1 is ON, Coil Voltage ~ 12V -> Contacts Close.
* When Q1 is OFF, Coil Voltage ~ 0V -> Contacts Open.
* Connections: Common (V_RELAY) to NO (LOAD_OUT).
S_K1 V_RELAY LOAD_OUT V_RELAY COLLECTOR RELAY_SW_MOD

* --- Load Circuit ---
* R2: Current limiting for LED
R2 LOAD_OUT LED_ANODE 470
* D2: Green LED
D2 LED_ANODE 0 LED_GREEN_MOD

* --- Component Models ---

* Switch Model for S1 (Logic Level Control)
.model TACTILE_SW SW(Vt=2.5 Vh=0.5 Ron=0.01 Roff=100Meg)

* Switch Model for Relay (High Voltage Threshold)
* Vt=8V ensures it pulls in only when coil is energized (approx >8V)
.model RELAY_SW_MOD SW(Vt=8.0 Vh=1.0 Ron=0.05 Roff=100Meg)

* BJT Model 2N2222
.model 2N2222_MOD NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=1 RE=0.1)

* Diode Model 1N4007
.model 1N4007_MOD D(IS=7n RS=0.034 N=1.8 BV=1000 IBV=5e-8 CJO=10p VJ=0.7 M=0.5 TT=100n)

* LED Model (Green, approx 2.1V Vf)
.model LED_GREEN_MOD D(IS=1e-22 RS=5 N=1.8 CJO=50p VJ=2.2 BV=5 IBV=10u)

* --- Analysis Directives ---
.op
.tran 100u 60m

* Output Printing
* V(SW_OUT): Input signal after switch S1
* V(LOAD_OUT): Output status (Relay NO contact)
* V(BASE): Transistor Base Voltage
* V(COLLECTOR): Transistor Collector Voltage (Relay Coil Low-Side)
.print tran V(SW_OUT) V(LOAD_OUT) V(BASE) V(COLLECTOR) I(L_K1_COIL)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation shows the switch (S1) activating at 5ms. When V(SW_OUT) goes high (~5V), V(BASE) rises to ~0.8V, turning Q1 ON. V(COLLECTOR) drops to ~70mV (saturation), energizing the coil. However, V(LOAD_OUT) remains high (~12V) throughout the log, even when the switch is OFF at t=0, suggesting the relay contact model might be inverted or the threshold logic is tricky.

Common mistakes and how to avoid them

  1. Omitting the flyback diode (D1):
    • Consequence: The high-voltage spike generated by the relay coil collapsing can destroy the transistor immediately.
    • Solution: Always install a diode in parallel with the coil, cathode to positive voltage.
  2. Using a base resistor (R1) that is too high:
    • Consequence: The transistor operates in the active region instead of saturation, causing it to overheat and potentially fail to trigger the relay.
    • Solution: Calculate IB to be at least 5× to 10× the required base current for the given collector load.
  3. Connecting the load to the Emitter (High-side):
    • Consequence: The relay will not receive 12 V; it will only receive approx Vbase – 0.7 V (approx 4.3 V), which is insufficient to actuate a 12 V relay.
    • Solution: Always use NPN transistors as «Low-side» switches (Load connected to Collector, Emitter to Ground).

Troubleshooting

  • Symptom: Relay does not click, LED D2 stays off.
    • Cause: S1 is not connecting or R1 is too large.
    • Fix: Check continuity on S1 and verify 5 V is reaching R1.
  • Symptom: Transistor gets very hot when Relay is ON.
    • Cause: Transistor is not fully saturated (Base current too low).
    • Fix: Reduce R1 value (e.g., try 470 Ω) to push Q1 into deep saturation.
  • Symptom: Circuit worked once, then stopped working permanently.
    • Cause: D1 is missing or reversed (causing short circuit) or Q1 is blown.
    • Fix: Replace Q1 and ensure D1 is correctly installed (Cathode to +12 V).
  • Symptom: D2 turns on, but no «click» is heard.
    • Cause: You might be testing with a solid-state indicator instead of a mechanical relay, or the relay coil is damaged.
    • Fix: Verify the coil resistance matches the datasheet specifications.

Possible improvements and extensions

  1. MOSFET Upgrade: Replace the NPN BJT with an N-Channel Logic-Level MOSFET (e.g., IRLZ44N) for higher efficiency and zero gate current draw.
  2. Optical Isolation: Add an optocoupler (like 4N25) before Q1 to completely electrically isolate the 5 V control side from the 12 V power side, protecting the microcontroller from catastrophic power failures.

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Quick Quiz

Question 1: What is the primary objective of the circuit described in the text?




Question 2: Which component acts as the switch driver to activate the relay?




Question 3: Why is this circuit particularly useful for microcontrollers?




Question 4: What is the specific function of the flyback diode in this circuit?




Question 5: What state does the transistor enter when the 5 V switch is closed?




Question 6: What voltage supply is specified for the relay coil in this practical case?




Question 7: What is the purpose of the base resistor (R1) connected to the transistor?




Question 8: Which part of the circuit provides galvanic isolation for the final load?




Question 9: What physical feedback indicates that the relay has successfully energized?




Question 10: What does the switch S1 simulate in this circuit context?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Intrusion alarm by wire break

Intrusion alarm by wire break prototype (Maker Style)

Level: Basic. Design a security circuit where cutting a wire activates an alarm using transistor saturation logic.

Objective and use case

In this project, you will build a closed-loop security system using a BJT transistor. When a specific wire (the «sense loop») is intact, the system remains silent; if the wire is cut or disconnected, an LED lights up immediately.

  • Perimeter security: Monitor windows or fences where a conductive strip or wire is installed.
  • Anti-tamper mechanisms: Detect if a device case has been opened by breaking a connection.
  • Continuity testing: Verify cable integrity in manufacturing harnesses.

Expected outcome:
* Loop Intact (Secure): The LED remains OFF. VBE ≈ 0 V.
* Loop Cut (Alarm): The LED turns ON. VBE ≈ 0.7 V and the transistor enters saturation (VCE < 0.2 V).

Target audience: Students and hobbyists learning basic transistor switching applications.

Materials

  • V1: 9 V DC power supply or battery.
  • Q1: 2N2222 or BC547 (NPN BJT), function: electronic switch.
  • R1: 10 kΩ resistor, function: base pull-up resistor.
  • R2: 470 Ω resistor, function: LED current limiting.
  • D1: Red LED, function: visual alarm indicator.
  • W1: Copper wire or jumper, function: sense loop (the «intruder» wire).

Wiring guide

Construct the circuit ensuring all connections map to the following nodes: VCC, GND (0), BASE, and COLLECTOR.

  • V1: Positive terminal to VCC, Negative terminal to GND.
  • R1 (Pull-up): Connects between VCC and BASE.
  • W1 (Sense Loop): Connects between BASE and GND.
  • Q1 (Transistor):
    • Base pin to BASE.
    • Emitter pin to GND.
    • Collector pin to COLLECTOR.
  • D1 (LED): Anode to VCC, Cathode to node LED_CATHODE.
  • R2 (Limiting): Connects between LED_CATHODE and COLLECTOR.

Conceptual block diagram

Conceptual block diagram — Wire Break Detection
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Intrusion alarm by wire break

[ A. CONTROL / SENSING LOOP ]
(Logic: W1 keeps Base LOW. If W1 breaks, R1 pulls Base HIGH)

VCC (9 V) --> [ R1: 10k Pull-Up ] --(Node: BASE)--> [ Q1: Base ]
                                         |
                                         +-------> [ W1: Sense Wire ] --> GND


[ B. ALARM / POWER LOOP ]
(Logic: Current flows through LED only when Q1 is ON)

VCC (9 V) --> [ D1: Red LED ] --> [ R2: 470R ] --> [ Q1: Collector ]
                                                          |
                                                      (Switch)
                                                          |
                                                          v
                                                   [ Q1: Emitter ] --> GND
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Intrusion alarm by wire break
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Verify the logic states using a multimeter.

  1. State 1: Loop Intact (Secure)

    • Ensure the wire W1 connects BASE to GND.
    • Measure Voltage Base-Emitter (VBE): Should be 0 V.
    • Measure Voltage Collector-Emitter (VCE): Should be close to 9 V (Cut-off region).
    • Result: LED is OFF.
  2. State 2: Loop Broken (Alarm)

    • Disconnect or cut wire W1.
    • Measure Voltage Base-Emitter (VBE): Should be approximately 0.7 V.
    • Measure Voltage Collector-Emitter (VCE): Should be approximately 0.1 V to 0.2 V (Saturation region).
    • Result: LED is ON.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Intrusion alarm by wire break
.width out=256

* --- Power Supply ---
* V1: 9 V DC power supply
V1 VCC 0 DC 9

* --- Input / Sense Loop ---
* W1: Sense Loop (Copper wire). 
* Modeled as a Voltage Controlled Switch (S_W1) to simulate the wire breaking.
* Logic: High Control (5V) = Wire Intact (Closed). Low Control (0V) = Wire Broken (Open).
S_W1 BASE 0 CTRL 0 SW_WIRE
.model SW_WIRE SW(Vt=2.5 Vh=0.1 Ron=0.01 Roff=100Meg)

* Control Signal for W1:
* Starts at 5V (Intact), breaks at 2ms (0V), stays broken for duration.
V_W1_CTRL CTRL 0 PULSE(5 0 2ms 1u 1u 5ms 10ms)

* --- Pull-up Network ---
* R1: Base pull-up resistor
* ... (truncated in public view) ...

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* Practical case: Intrusion alarm by wire break
.width out=256

* --- Power Supply ---
* V1: 9 V DC power supply
V1 VCC 0 DC 9

* --- Input / Sense Loop ---
* W1: Sense Loop (Copper wire). 
* Modeled as a Voltage Controlled Switch (S_W1) to simulate the wire breaking.
* Logic: High Control (5V) = Wire Intact (Closed). Low Control (0V) = Wire Broken (Open).
S_W1 BASE 0 CTRL 0 SW_WIRE
.model SW_WIRE SW(Vt=2.5 Vh=0.1 Ron=0.01 Roff=100Meg)

* Control Signal for W1:
* Starts at 5V (Intact), breaks at 2ms (0V), stays broken for duration.
V_W1_CTRL CTRL 0 PULSE(5 0 2ms 1u 1u 5ms 10ms)

* --- Pull-up Network ---
* R1: Base pull-up resistor
R1 VCC BASE 10k

* --- Switching Element ---
* Q1: NPN Transistor (2N2222)
* Connections: Collector, Base, Emitter(GND)
Q1 COLLECTOR BASE 0 2N2222
.model 2N2222 NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=0.3 RE=0.2)

* --- Output / Alarm Indicator ---
* D1: Red LED
* Anode to VCC, Cathode to LED_CATHODE
D1 VCC LED_CATHODE LED_RED
.model LED_RED D(IS=93.2P RS=42M N=3.73 BV=4 IBV=10U CJO=2.97P VJ=0.75 M=0.33 TT=4.32U)

* R2: LED current limiting resistor
* Between LED_CATHODE and COLLECTOR
R2 LED_CATHODE COLLECTOR 470

* --- Simulation Commands ---
.op
* Simulate for 5ms to capture the wire break event at 2ms
.tran 10u 5ms

* --- Output Printing ---
* V(BASE): Trigger voltage (Low=Intact, High=Alarm)
* V(COLLECTOR): Output node (Pulled Low when Alarm is Active)
.print tran V(BASE) V(COLLECTOR) V(LED_CATHODE)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (536 rows)
Index   time            v(base)         v(collector)    v(led_cathode)
0	0.000000e+00	8.999991e-06	8.979590e+00	8.979590e+00
1	1.000000e-07	8.999991e-06	8.979590e+00	8.979590e+00
2	2.000000e-07	8.999991e-06	8.979590e+00	8.979590e+00
3	4.000000e-07	8.999991e-06	8.979590e+00	8.979590e+00
4	8.000000e-07	8.999991e-06	8.979590e+00	8.979590e+00
5	1.600000e-06	8.999991e-06	8.979591e+00	8.979591e+00
6	3.200000e-06	8.999991e-06	8.979592e+00	8.979592e+00
7	6.400000e-06	8.999991e-06	8.979594e+00	8.979594e+00
8	1.280000e-05	8.999991e-06	8.979598e+00	8.979598e+00
9	2.280000e-05	8.999991e-06	8.979604e+00	8.979604e+00
10	3.280000e-05	8.999991e-06	8.979610e+00	8.979610e+00
11	4.280000e-05	8.999991e-06	8.979616e+00	8.979616e+00
12	5.280000e-05	8.999991e-06	8.979622e+00	8.979623e+00
13	6.280000e-05	8.999991e-06	8.979629e+00	8.979629e+00
14	7.280000e-05	8.999991e-06	8.979635e+00	8.979635e+00
15	8.280000e-05	8.999991e-06	8.979641e+00	8.979641e+00
16	9.280000e-05	8.999991e-06	8.979647e+00	8.979647e+00
17	1.028000e-04	8.999991e-06	8.979653e+00	8.979653e+00
18	1.128000e-04	8.999991e-06	8.979659e+00	8.979659e+00
19	1.228000e-04	8.999991e-06	8.979665e+00	8.979665e+00
20	1.328000e-04	8.999991e-06	8.979671e+00	8.979671e+00
21	1.428000e-04	8.999991e-06	8.979677e+00	8.979677e+00
22	1.528000e-04	8.999991e-06	8.979684e+00	8.979684e+00
23	1.628000e-04	8.999991e-06	8.979690e+00	8.979690e+00
... (512 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Intrusion alarm by wire break
.width out=256

* --- Power Supply ---
* V1: 9 V DC power supply
V1 VCC 0 DC 9

* --- Input / Sense Loop ---
* W1: Sense Loop (Copper wire).
* Modeled as a Voltage Controlled Switch (S_W1) to simulate the wire breaking.
* Logic: High Control (5V) = Wire Intact (Closed). Low Control (0V) = Wire Broken (Open).
S_W1 BASE 0 CTRL 0 SW_WIRE
.model SW_WIRE SW(Vt=2.5 Vh=0.1 Ron=0.01 Roff=100Meg)

* Control Signal for W1:
* Starts at 5V (Intact), breaks at 2ms (0V), stays broken for duration.
V_W1_CTRL CTRL 0 PULSE(5 0 2ms 1u 1u 5ms 10ms)

* --- Pull-up Network ---
* R1: Base pull-up resistor
R1 VCC BASE 10k

* --- Switching Element ---
* Q1: NPN Transistor (2N2222)
* Connections: Collector, Base, Emitter(GND)
Q1 COLLECTOR BASE 0 2N2222
.model 2N2222 NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=0.3 RE=0.2)

* --- Output / Alarm Indicator ---
* D1: Red LED
* Anode to VCC, Cathode to LED_CATHODE
D1 VCC LED_CATHODE LED_RED
.model LED_RED D(IS=93.2P RS=42M N=3.73 BV=4 IBV=10U CJO=2.97P VJ=0.75 M=0.33 TT=4.32U)

* R2: LED current limiting resistor
* Between LED_CATHODE and COLLECTOR
R2 LED_CATHODE COLLECTOR 470

* --- Simulation Commands ---
.op
* Simulate for 5ms to capture the wire break event at 2ms
.tran 10u 5ms

* --- Output Printing ---
* V(BASE): Trigger voltage (Low=Intact, High=Alarm)
* V(COLLECTOR): Output node (Pulled Low when Alarm is Active)
.print tran V(BASE) V(COLLECTOR) V(LED_CATHODE)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Connecting the loop to the Collector: Placing the sense wire on the output side will likely short the power supply or the LED, rather than controlling the transistor. Ensure the loop controls the Base.
  2. Omitting the Base Resistor (R1): If R1 is missing, the Base floats when the wire is cut, and the transistor may not turn on reliably. R1 provides the necessary turn-on current.
  3. No current limiting for LED: Forgetting R2 allows unlimited current to flow through the LED and Q1 upon alarm activation, instantly burning out the LED.

Troubleshooting

  • LED never turns ON: Check if R1 is connected to VCC. If the base never receives voltage when the wire is cut, the transistor stays OFF.
  • LED stays ON (even with loop intact): Check the W1 connection. If the resistance of the sense wire is too high (bad contact), it might not pull the base voltage down enough to turn off the transistor.
  • Transistor gets hot: Check if R2 is too low (excessive collector current) or if the LED is shorted.

Possible improvements and extensions

  1. Audible Alarm: Connect a 9 V active buzzer in parallel with the LED (and its resistor) to provide sound.
  2. Latching Circuit: Use a Thyristor (SCR) instead of an NPN transistor so that once the wire is cut, the alarm stays ON even if the intruder tries to reconnect the wire.

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Quick Quiz

Question 1: What is the primary function of the 'sense loop' wire in this security circuit?




Question 2: When the sense loop is intact (secure state), what is the status of the LED?




Question 3: Which component acts as the electronic switch in this circuit?




Question 4: What happens electrically when the sense wire (W1) is cut?




Question 5: What is the approximate Base-Emitter voltage (Vbe) when the alarm is triggered (Loop Cut)?




Question 6: In the 'Secure' state (Loop Intact), why is the Base-Emitter voltage approximately 0 V?




Question 7: What is the purpose of resistor R2 (470R) in the Alarm/Power Loop?




Question 8: Which resistor acts as the 'Pull-Up' resistor for the base of the transistor?




Question 9: What transistor state corresponds to the 'Alarm' condition?




Question 10: Which of the following is a listed use case for this circuit?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Slow turn-off timer

Slow turn-off timer prototype (Maker Style)

Level: Basic — Construct a circuit that fades an LED out slowly using capacitor discharge.

Objective and use case

In this practical case, you will build an analog timer circuit using an NPN transistor and a capacitor. When a push button is released, the LED will not turn off immediately; instead, it will dim gradually until it extinguishes.

  • Interior car lighting: mimics the effect of dome lights fading out after the door is closed.
  • Safety lighting: provides temporary illumination in hallways or stairwells after a switch is turned off.
  • Debouncing simulation: demonstrates how capacitors smooth out sudden signal changes.
  • Visualizing RC time constants: allows direct observation of electrical charge storage and decay.

Expected outcome:
* Immediate ON: When the button is pressed, the LED lights up instantly at full brightness.
* Delayed OFF: Upon releasing the button, the LED remains lit and fades out over a period of 2 to 5 seconds.
* Voltage Decay: If measured with a multimeter, the voltage at the capacitor decreases exponentially.
* Visual Feedback: The LED brightness directly correlates to the remaining charge in the capacitor.
* Target audience: Students and hobbyists understanding the relationship between capacitors and transistors.

Materials

  • V1: 9 V DC supply, function: main power source
  • S1: Momentary push button (Normally Open), function: trigger mechanism
  • R1: 100 Ω resistor, function: switch current protection (limits inrush current to capacitor)
  • R2: 22 kΩ resistor, function: base current limiting and timing control
  • R3: 470 Ω resistor, function: LED current limiting
  • C1: 1000 µF electrolytic capacitor, function: charge storage (timing tank)
  • Q1: 2N2222 (or BC547) NPN transistor, function: current switch/amplifier
  • D1: Red LED, function: visual output indicator

Wiring guide

Use the following node connections to assemble the circuit on a breadboard.

  • Power Nodes:

    • VCC: Positive rail (9 V).
    • 0: Ground rail (0 V).
  • Switch and Capacitor Network (Nodes: VCC, V_STORE, 0):

    • S1 connects between VCC and an intermediate node (internal to switch assembly).
    • R1 connects between the switch output and V_STORE. (When S1 is pressed, V_STORE charges to ~9 V).
    • C1 connects between V_STORE (positive leg) and 0 (negative leg).
  • Transistor Control (Nodes: V_STORE, V_BASE, 0):

    • R2 connects between V_STORE and V_BASE.
    • Q1 (Base) connects to V_BASE.
    • Q1 (Emitter) connects to 0.
  • Output Stage (Nodes: VCC, V_COLL):

    • R3 connects between VCC and the anode of D1.
    • D1 (Cathode) connects to V_COLL.
    • Q1 (Collector) connects to V_COLL.

Conceptual block diagram

Conceptual block diagram — Slow Turn-Off Timer
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

+-------------------------------------------------------------------------+
|                       SLOW TURN-OFF TIMER DIAGRAM                       |
+-------------------------------------------------------------------------+

1. TIMING & CONTROL LOOP (Charges C1, drives Transistor Base)
---------------------------------------------------------------------------

VCC (9 V) --> [ S1: Button ] --> [ R1: 100 ] --(V_STORE)--> [ R2: 22k ] --> [ Q1:Base ]
                                                  |
                                                  v
                                            [ C1: 1000u ]
                                                  |
                                                  v
                                                 GND


2. OUTPUT LOAD LOOP (Powering the LED)
---------------------------------------------------------------------------

VCC (9 V) --> [ R3: 470 ] --> [ LED: Red ] --> [ Q1:Collector ]
                                                     |
                                                     v
                                              (Current Flow)
                                                     v
                                              [ Q1:Emitter ] --> GND
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Simple transistor timer
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

To validate the circuit operation, perform the following steps:

  1. Charging phase: Press and hold S1. Measure the voltage at V_STORE relative to Ground. It should rise rapidly to approximately 9 V. The LED D1 should be fully lit.
  2. Base activation: While holding S1, measure the voltage at V_BASE. It should differ from V_STORE due to the drop across R2, stabilizing around 0.7 V – 0.8 V (the Base-Emitter saturation voltage).
  3. Discharge phase: Release S1. Observe D1. It should not turn off instantly. Instead, it should fade.
  4. Time measurement: Use a stopwatch to measure the time from the moment S1 is released until the LED is completely dark. With a 1000 µF capacitor and 22 kΩ resistor, this should take several seconds.
  5. Voltage tracking: Connect a multimeter to V_STORE immediately after releasing the button. Watch the voltage drop. The LED usually turns off when V_STORE drops below the threshold required to maintain sufficient base current through R2 (roughly when V_STORE approaches 1.5 V – 2 V).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Slow turn-off timer
.width out=256

* --- Models ---
* Standard NPN Transistor Model
.model 2N2222 NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=1 RE=1)
* Generic Red LED Model (Vf approx 1.8V-2V)
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=50p)
* Switch Model for Push Button
.model SW_BTN SW(Vt=2.5 Ron=0.1 Roff=100M)

* --- Power Supply ---
V1 VCC 0 DC 9

* --- Input / Trigger Mechanism ---
* S1: Push Button. Modeled as a voltage-controlled switch connecting VCC to SW_OUT.
* V_BTN_ACT: Simulates the user pressing the button. 
* Pulse starts at 1s, holds for 2s (simulating a solid press), then releases.
V_BTN_ACT CTRL 0 PULSE(0 5 1 0.1 0.1 2 100)
S1 VCC SW_OUT CTRL 0 SW_BTN
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Slow turn-off timer
.width out=256

* --- Models ---
* Standard NPN Transistor Model
.model 2N2222 NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=1 RE=1)
* Generic Red LED Model (Vf approx 1.8V-2V)
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=50p)
* Switch Model for Push Button
.model SW_BTN SW(Vt=2.5 Ron=0.1 Roff=100M)

* --- Power Supply ---
V1 VCC 0 DC 9

* --- Input / Trigger Mechanism ---
* S1: Push Button. Modeled as a voltage-controlled switch connecting VCC to SW_OUT.
* V_BTN_ACT: Simulates the user pressing the button. 
* Pulse starts at 1s, holds for 2s (simulating a solid press), then releases.
V_BTN_ACT CTRL 0 PULSE(0 5 1 0.1 0.1 2 100)
S1 VCC SW_OUT CTRL 0 SW_BTN

* --- Switch Current Protection & Charging ---
* R1 limits inrush current to C1 when S1 is closed.
R1 SW_OUT V_STORE 100

* --- Timing Tank ---
* C1 charges when S1 is closed and discharges through R2/Q1 when open.
C1 V_STORE 0 1000u

* --- Transistor Control ---
* R2 provides base current and sets the discharge timing constant (Tau = R2*C1 approx 22s).
R2 V_STORE V_BASE 22k

* --- Transistor Switch ---
* Q1 NPN Transistor (2N2222)
* Collector: V_COLL, Base: V_BASE, Emitter: 0 (GND)
Q1 V_COLL V_BASE 0 2N2222

* --- Output Stage ---
* R3 limits current through the LED.
R3 VCC LED_ANODE 470
* D1 Red LED. Anode at LED_ANODE, Cathode at V_COLL.
D1 LED_ANODE V_COLL DLED

* --- Simulation Commands ---
.op
* Transient analysis for 60 seconds to capture the slow decay (RC ~ 22s).
.tran 0.1s 60s

* --- Output Directives ---
* Printing Capacitor Voltage (Timing) and Collector Voltage (Output State)
.print tran V(V_STORE) V(V_COLL) V(LED_ANODE) V(SW_OUT)

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (640 rows)
Index   time            v(v_store)      v(v_coll)       v(led_anode)    v(sw_out)
0	0.000000e+00	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
1	1.000000e-03	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
2	2.000000e-03	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
3	4.000000e-03	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
4	8.000000e-03	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
5	1.600000e-02	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
6	3.200000e-02	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
7	6.400000e-02	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
8	1.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
9	2.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
10	3.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
11	4.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
12	5.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
13	6.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
14	7.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
15	8.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
16	9.280000e-01	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
17	1.000000e+00	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
18	1.010000e+00	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
19	1.026000e+00	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
20	1.030750e+00	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
21	1.039062e+00	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
22	1.041363e+00	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
23	1.045390e+00	8.962619e+00	1.066236e-01	2.056192e+00	8.999963e+00
... (616 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Slow turn-off timer
.width out=256

* --- Models ---
* Standard NPN Transistor Model
.model 2N2222 NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=1 RE=1)
* Generic Red LED Model (Vf approx 1.8V-2V)
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=50p)
* Switch Model for Push Button
.model SW_BTN SW(Vt=2.5 Ron=0.1 Roff=100M)

* --- Power Supply ---
V1 VCC 0 DC 9

* --- Input / Trigger Mechanism ---
* S1: Push Button. Modeled as a voltage-controlled switch connecting VCC to SW_OUT.
* V_BTN_ACT: Simulates the user pressing the button.
* Pulse starts at 1s, holds for 2s (simulating a solid press), then releases.
V_BTN_ACT CTRL 0 PULSE(0 5 1 0.1 0.1 2 100)
S1 VCC SW_OUT CTRL 0 SW_BTN

* --- Switch Current Protection & Charging ---
* R1 limits inrush current to C1 when S1 is closed.
R1 SW_OUT V_STORE 100

* --- Timing Tank ---
* C1 charges when S1 is closed and discharges through R2/Q1 when open.
C1 V_STORE 0 1000u

* --- Transistor Control ---
* R2 provides base current and sets the discharge timing constant (Tau = R2*C1 approx 22s).
R2 V_STORE V_BASE 22k

* --- Transistor Switch ---
* Q1 NPN Transistor (2N2222)
* Collector: V_COLL, Base: V_BASE, Emitter: 0 (GND)
Q1 V_COLL V_BASE 0 2N2222

* --- Output Stage ---
* R3 limits current through the LED.
R3 VCC LED_ANODE 470
* D1 Red LED. Anode at LED_ANODE, Cathode at V_COLL.
D1 LED_ANODE V_COLL DLED

* --- Simulation Commands ---
.op
* Transient analysis for 60 seconds to capture the slow decay (RC ~ 22s).
.tran 0.1s 60s

* --- Output Directives ---
* Printing Capacitor Voltage (Timing) and Collector Voltage (Output State)
.print tran V(V_STORE) V(V_COLL) V(LED_ANODE) V(SW_OUT)

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Capacitor polarity reversed: Electrolytic capacitors have a specific polarity. Connecting the negative stripe to the positive voltage can cause the component to heat up or pop. Solution: Ensure the leg marked with a stripe (negative) connects to Ground.
  2. R2 value too low: If R2 is very small (e.g., 1 kΩ), the capacitor will discharge into the transistor base very quickly, resulting in no visible fading effect. Solution: Use a high resistance value (10 kΩ–47 kΩ) to slow down the discharge.
  3. Omitting R1: Connecting the switch directly to a large capacitor creates a massive current spike (spark) when pressed. Solution: Always use a small resistor (100 Ω) in series with the switch to protect the contacts.

Troubleshooting

  • LED turns off instantly (no fade):
    • Cause: Capacitor C1 is missing, disconnected, or the value is too small (e.g., 100 nF instead of 1000 µF).
    • Fix: Verify C1 is correctly seated and is at least 470 µF.
  • LED stays on permanently:
    • Cause: The switch S1 might be the wrong type (Latching instead of Momentary) or there is a short circuit bypassing the transistor.
    • Fix: Ensure the button releases physically and check wiring around the Collector-Emitter.
  • LED is very dim even when button is pressed:
    • Cause: R2 (Base resistor) is too high (limiting base current too much) or R3 (LED resistor) is too high.
    • Fix: Check that R2 is roughly 22 kΩ and R3 is roughly 470 Ω.

Possible improvements and extensions

  1. Variable Timing: Replace R2 with a 100 kΩ potentiometer in series with a 1 kΩ resistor. This allows you to adjust the fade-out duration manually.
  2. Darlington Pair: Replace Q1 with a Darlington transistor (or two NPNs connected in Darlington configuration). This offers a much higher current gain, allowing you to use a much larger R2 (e.g., 1 MΩ), resulting in extremely long timer durations (minutes) with the same capacitor.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the circuit described in the text?




Question 2: Which component is responsible for storing the electrical charge that keeps the LED lit after the button is released?




Question 3: What real-world application mimics the effect created by this circuit?




Question 4: What happens to the LED immediately when the push button is pressed?




Question 5: Based on the text, what is the purpose of the resistor R1 (100 Ω) in this specific circuit design?




Question 6: Which type of transistor is specified for use in this project?




Question 7: If you measure the voltage at the capacitor after releasing the button, how does it behave?




Question 8: What is the expected duration for the LED to fade out after releasing the button?




Question 9: Besides lighting, what concept does this circuit demonstrate regarding signal changes?




Question 10: What physical phenomenon allows the direct observation of electrical charge storage and decay in this project?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: Simple audio amplifier

Simple audio amplifier prototype (Maker Style)

Level: Basic. Build a circuit to amplify a weak audio signal using an NPN transistor in common-emitter configuration.

Objective and use case

In this case, you will build a classic single-stage Class A amplifier using an NPN transistor with voltage divider biasing. You will input a small AC signal (representing audio) and observe a larger voltage swing at the output.

  • Why it is useful:

    • Pre-amplification: Boosts weak signals from microphones before they reach a power amplifier.
    • Signal conditioning: Raises sensor output levels to be readable by microcontrollers.
    • Analog processing: Fundamental building block for filters, oscillators, and mixers.
    • Impedance matching: Buffers high-impedance sources to drive lower-impedance loads (depending on specific configuration).
  • Expected outcome:

    • DC Operating Point: VCE stabilizes around half the supply voltage (VCC / 2) for maximum swing.
    • Amplification: The AC output voltage (Vout) is significantly larger than the input (Vin), indicating Voltage Gain (Av > 1).
    • Phase Inversion: The output signal waveform is inverted (180^\circ) relative to the input.
    • Current Flow: IC is controlled by IB according to the transistor’s beta (\beta).
  • Target audience and level: Students with basic knowledge of Ohm’s Law and component identification.

Materials

  • V1: 9 V DC battery or bench supply, function: main circuit power.
  • V2: Signal Generator (Sine wave, 1 kHz, 20 mV peak-to-peak), function: simulates weak audio input.
  • Q1: 2N3904 (or 2N2222) NPN BJT, function: active amplifying element.
  • R1: 22 kΩ resistor, function: upper base bias divider.
  • R2: 6.8 kΩ resistor, function: lower base bias divider.
  • R3: 4.7 kΩ resistor, function: collector load (sets gain and output impedance).
  • R4: 1 kΩ resistor, function: emitter degeneration (sets DC stability).
  • C1: 10 µF electrolytic capacitor, function: input DC blocking.
  • C2: 10 µF electrolytic capacitor, function: output DC blocking.
  • C3: 100 µF electrolytic capacitor, function: emitter bypass (increases AC gain).

Wiring guide

Use the following nodes to wire your circuit: VCC (9 V), 0 (GND), BASE, COLL, EMIT, VIN, VOUT.

  • V1: Positive terminal connects to VCC, Negative terminal connects to 0.
  • V2: Signal output connects to VIN, Ground connects to 0.
  • R1: Connects between VCC and BASE.
  • R2: Connects between BASE and 0.
  • R3: Connects between VCC and COLL.
  • R4: Connects between EMIT and 0.
  • Q1: Collector pin to COLL, Base pin to BASE, Emitter pin to EMIT.
  • C1: Positive leg to BASE, Negative leg to VIN.
  • C2: Positive leg to COLL, Negative leg to VOUT (Load/Scope probe connects here).
  • C3: Positive leg to EMIT, Negative leg to 0 (Place in parallel with R4).

Conceptual block diagram

Conceptual block diagram — Common Emitter Amplifier
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Simple audio amplifier

      (BIAS & INPUT NETWORK)                               (POWER & OUTPUT NETWORK)
      ======================                               ========================

                                                           VCC (9 V)
      VCC (9 V)                                                |
         |                                                    |
         v                                                    v
    [ R1: 22k ]                                          [ R3: 4.7k ]
         |                                                    |
         v                                                    v
      (BASE) --------(Control Signal)----------------> [ Q1: Collector ] <--(COLL)--+
         ^                                                    |                     |
         |                                                    | (Amplified Current) |
    [ C1: 10uF ] <--(VIN)-- [ V2: Source ]                    v                     |
         |                                             [ Q1: Emitter ]              +--> [ C2: 10uF ] --> VOUT
         v                                                    |
    [ R2: 6.8k ]                                              v
         |                                                  (EMIT)
         v                                                    |
        GND                                       +-----------+-----------+
                                                  |                       |
                                                  v                       v
                                             [ R4: 1k ]             [ C3: 100uF ]
                                                  |                       |
                                                  v                       v
                                                 GND                     GND
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Simple audio amplifier
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Perform these tests using a Multimeter (DMM) and an Oscilloscope (if available).

  1. DC Bias Check (Quiescent Point):

    • Ensure V2 (AC source) is OFF or disconnected.
    • Measure voltage from COLL to 0. It should be approximately 4 V to 5 V (roughly half of VCC).
    • Measure voltage from EMIT to 0. It should be approximately 1 V (VE).
    • Measure voltage from BASE to EMIT (VBE). It must be ~0.65 V to 0.7 V for the transistor to be active.
  2. Current Calculation:

    • Calculate Collector Current (IC): IC ≈ VEMIT / R4. Expect approx 1 mA.
    • Calculate Base Current (IB): IC / \beta (assuming \beta ≈ 100, IB ≈ 10 µ A).
  3. AC Gain Verification:

    • Connect V2 (VIN) with a 20 mV peak-to-peak sine wave at 1 kHz.
    • Measure the Peak-to-Peak voltage at VOUT.
    • Calculate Voltage Gain (Av): Av = Voutpp / Vinpp.
    • Observation: Without C3, gain is low (≈ R3 / R4). With C3 connected, gain should increase significantly.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Simple audio amplifier

* --- Power Supply ---
* V1: 9 V DC battery
V1 VCC 0 DC 9

* --- Input Signal ---
* V2: Signal Generator (Sine wave, 1 kHz, 20 mV peak-to-peak -> 10mV Amplitude)
V2 VIN 0 SIN(0 10m 1k)

* --- Components ---
* Q1: 2N3904 NPN BJT
Q1 COLL BASE EMIT 2N3904

* R1: Upper base bias divider
R1 VCC BASE 22k

* R2: Lower base bias divider
R2 BASE 0 6.8k

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Simple audio amplifier

* --- Power Supply ---
* V1: 9 V DC battery
V1 VCC 0 DC 9

* --- Input Signal ---
* V2: Signal Generator (Sine wave, 1 kHz, 20 mV peak-to-peak -> 10mV Amplitude)
V2 VIN 0 SIN(0 10m 1k)

* --- Components ---
* Q1: 2N3904 NPN BJT
Q1 COLL BASE EMIT 2N3904

* R1: Upper base bias divider
R1 VCC BASE 22k

* R2: Lower base bias divider
R2 BASE 0 6.8k

* R3: Collector load
R3 VCC COLL 4.7k

* R4: Emitter degeneration
R4 EMIT 0 1k

* C1: Input DC blocking (Positive leg to BASE, Negative leg to VIN)
C1 BASE VIN 10u

* C2: Output DC blocking (Positive leg to COLL, Negative leg to VOUT)
C2 COLL VOUT 10u

* C3: Emitter bypass (Positive leg to EMIT, Negative leg to 0)
C3 EMIT 0 100u

* --- Load Simulation ---
* High impedance load to simulate scope probe and prevent floating node error at VOUT
R_SCOPE VOUT 0 1Meg

* --- Models ---
.model 2N3904 NPN(IS=1E-14 VAF=100 BF=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1 TR=250n TF=350p ITF=1 VTF=2 XTF=3)

* --- Analysis Directives ---
.op
.tran 10u 5ms

* --- Output ---
* Prints Input and Output voltages, plus internal transistor nodes
.print tran V(VIN) V(VOUT) V(BASE) V(COLL) V(EMIT)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (511 rows)
Index   time            v(vin)          v(vout)         v(base)         v(coll)         v(emit)
0	0.000000e+00	0.000000e+00	0.000000e+00	2.100182e+00	2.275541e+00	1.435514e+00
1	1.000000e-07	6.283185e-06	-1.11372e-03	2.100188e+00	2.274427e+00	1.435514e+00
2	2.000000e-07	1.256637e-05	-2.51792e-03	2.100195e+00	2.273023e+00	1.435514e+00
3	4.000000e-07	2.513271e-05	-5.47602e-03	2.100207e+00	2.270065e+00	1.435514e+00
4	8.000000e-07	5.026527e-05	-1.15278e-02	2.100232e+00	2.264013e+00	1.435514e+00
5	1.600000e-06	1.005293e-04	-2.35622e-02	2.100283e+00	2.251979e+00	1.435514e+00
6	3.200000e-06	2.010484e-04	-4.77358e-02	2.100383e+00	2.227805e+00	1.435514e+00
7	6.400000e-06	4.020155e-04	-9.61836e-02	2.100584e+00	2.179357e+00	1.435514e+00
8	1.280000e-05	8.033810e-04	-1.93689e-01	2.100985e+00	2.081852e+00	1.435516e+00
9	2.280000e-05	1.427671e-03	-3.47124e-01	2.101609e+00	1.928416e+00	1.435522e+00
10	3.280000e-05	2.046327e-03	-5.01331e-01	2.102227e+00	1.774210e+00	1.435531e+00
11	4.280000e-05	2.656907e-03	-6.48595e-01	2.102836e+00	1.626945e+00	1.435544e+00
12	5.280000e-05	3.257002e-03	-7.15494e-01	2.103433e+00	1.560045e+00	1.435558e+00
13	6.280000e-05	3.844242e-03	-7.38189e-01	2.104013e+00	1.537349e+00	1.435575e+00
14	7.280000e-05	4.416311e-03	-7.50146e-01	2.104572e+00	1.525391e+00	1.435592e+00
15	8.280000e-05	4.970951e-03	-7.58389e-01	2.105109e+00	1.517147e+00	1.435610e+00
16	9.280000e-05	5.505973e-03	-7.63991e-01	2.105621e+00	1.511545e+00	1.435628e+00
17	1.028000e-04	6.019265e-03	-7.68326e-01	2.106106e+00	1.507209e+00	1.435647e+00
18	1.128000e-04	6.508802e-03	-7.71816e-01	2.106563e+00	1.503719e+00	1.435667e+00
19	1.228000e-04	6.972652e-03	-7.74681e-01	2.106990e+00	1.500853e+00	1.435687e+00
20	1.328000e-04	7.408984e-03	-7.77018e-01	2.107384e+00	1.498515e+00	1.435707e+00
21	1.428000e-04	7.816076e-03	-7.78966e-01	2.107746e+00	1.496566e+00	1.435728e+00
22	1.528000e-04	8.192321e-03	-7.80567e-01	2.108073e+00	1.494964e+00	1.435750e+00
23	1.628000e-04	8.536235e-03	-7.81896e-01	2.108365e+00	1.493635e+00	1.435772e+00
... (487 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Simple audio amplifier

* --- Power Supply ---
* V1: 9 V DC battery
V1 VCC 0 DC 9

* --- Input Signal ---
* V2: Signal Generator (Sine wave, 1 kHz, 20 mV peak-to-peak -> 10mV Amplitude)
V2 VIN 0 SIN(0 10m 1k)

* --- Components ---
* Q1: 2N3904 NPN BJT
Q1 COLL BASE EMIT 2N3904

* R1: Upper base bias divider
R1 VCC BASE 22k

* R2: Lower base bias divider
R2 BASE 0 6.8k

* R3: Collector load
R3 VCC COLL 4.7k

* R4: Emitter degeneration
R4 EMIT 0 1k

* C1: Input DC blocking (Positive leg to BASE, Negative leg to VIN)
C1 BASE VIN 10u

* C2: Output DC blocking (Positive leg to COLL, Negative leg to VOUT)
C2 COLL VOUT 10u

* C3: Emitter bypass (Positive leg to EMIT, Negative leg to 0)
C3 EMIT 0 100u

* --- Load Simulation ---
* High impedance load to simulate scope probe and prevent floating node error at VOUT
R_SCOPE VOUT 0 1Meg

* --- Models ---
.model 2N3904 NPN(IS=1E-14 VAF=100 BF=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1 TR=250n TF=350p ITF=1 VTF=2 XTF=3)

* --- Analysis Directives ---
.op
.tran 10u 5ms

* --- Output ---
* Prints Input and Output voltages, plus internal transistor nodes
.print tran V(VIN) V(VOUT) V(BASE) V(COLL) V(EMIT)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Transistor Pinout Reversal: Swapping the Collector and Emitter prevents amplification and acts like a reverse-biased diode.
    • Solution: Double-check the datasheet for the 2N3904 (E-B-C flat side facing you) before inserting.
  2. Capacitor Polarity: Electrolytic capacitors (C1, C2, C3) explode or fail if biased backwards.
    • Solution: Ensure the positive lead (longer leg) faces the more positive DC potential (towards the transistor base/collector).
  3. Saturation or Cutoff: Using wrong resistor values shifts the Q-point, causing the signal to clip (flatten) immediately.
    • Solution: Verify DC voltages at the Collector before applying an AC signal. If VC is near 9 V or 0 V, check R1 and R2.

Troubleshooting

  • Symptom: No Output Signal.
    • Cause: Loose connection, blown transistor, or V1 is off.
    • Fix: Check continuity on the breadboard rails; verify V1 is 9 V.
  • Symptom: Output is Clipped (Flat tops or bottoms).
    • Cause: The amplifier is driven into saturation (flat bottom) or cutoff (flat top), or input signal is too large.
    • Fix: Reduce input amplitude (V2); check bias resistors (R1, R2) to center the Q-point.
  • Symptom: Low Gain (Output ≈ Input).
    • Cause: Bypass capacitor C3 is missing, loose, or too small.
    • Fix: Ensure C3 is connected solidly in parallel with R4. This shorts the emitter resistor for AC signals, maximizing gain.

Possible improvements and extensions

  1. Volume Control: Replace R2 (or add a pot before C1) with a 10 kΩ potentiometer to attenuate the input signal.
  2. Increased Power: Add a second transistor stage (Emitter Follower / Class B push-pull) after VOUT to drive a small 8 Ω speaker instead of just observing voltage on a scope.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary objective of the circuit described in the text?




Question 2: Which transistor configuration is used in this amplifier circuit?




Question 3: What is the expected phase relationship between the input and output signals in this configuration?




Question 4: Ideally, where should the DC operating point (V_CE) stabilize for maximum voltage swing?




Question 5: Which component serves as the active amplifying element in this circuit?




Question 6: What is the purpose of the signal generator (V2) in this setup?




Question 7: Which of the following is explicitly listed as a use case for this type of amplifier?




Question 8: What does a Voltage Gain (Av > 1) signify in this context?




Question 9: What role does resistor R1 (22 kΩ) typically play in a voltage divider biasing network?




Question 10: According to standard BJT theory implied in the text, the collector current (I_C) is primarily controlled by the base current (I_B) and which parameter?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: The transistor as a light switch

The transistor as a light switch prototype (Maker Style)

Level: Basic. Objective: Understand BJT cut-off and saturation to control a load (LED) with a small control signal.

Objective and use case

In this practical case, you will build a circuit using an NPN Bipolar Junction Transistor (BJT) to switch a high-current load (an LED) on and off using a low-current control signal triggered by a push button.

Why it is useful:
* Microcontroller interfacing: Allows low-power pins (like those on an Arduino or ESP32) to drive higher current loads.
* Sensor actuation: Enables weak signals from sensors (like LDRs or thermistors) to activate lights or alarms.
* Component protection: Separates the sensitive control circuit from the power circuit.
* Logic switching: Forms the fundamental building block of digital logic gates.

Expected outcome:
* Idle State (Button Released): The transistor is in Cut-off. IC ≈ 0 mA, LED is OFF, and VCE ≈ Vsupply.
* Active State (Button Pressed): The transistor enters Saturation. LED is ON.
* Saturation Voltage: VCE drops to approximately $0.1$ V to $0.2$ V.
* Base Threshold: VBE stabilizes around $0.7$ V when the transistor is conducting.

Target audience: Basic level electronics students.

Materials

  • V1: 9 V DC battery or power supply, function: Main circuit power.
  • S1: Tactile Push-button (Normally Open), function: User input trigger.
  • R1: 10 kΩ resistor, function: Base current limiting (to ensure saturation without damaging the Base).
  • R2: 100 kΩ resistor, function: Pull-down resistor (keeps Base at 0 V when S1 is open).
  • R3: 330 Ω resistor, function: LED current limiting protection.
  • Q1: 2N2222 (or BC547) NPN Transistor, function: Electronic switch.
  • D1: Red LED, function: Visual load indicator.

Wiring guide

This guide uses specific node names to help you visualize the connections.
* Power Nodes: Connect V1 positive to node VCC and negative to node 0 (GND).
* Input Stage:
* Connect one side of S1 to VCC.
* Connect the other side of S1 to node INPUT_SIG.
* Connect R1 (10 kΩ) between INPUT_SIG and node BASE.
* Connect R2 (100 kΩ) between node BASE and node 0 (GND).
* Transistor Connections:
* Connect the Base of Q1 to node BASE.
* Connect the Emitter of Q1 directly to node 0 (GND).
* Connect the Collector of Q1 to node COLL.
* Output Load:
* Connect R3 (330 Ω) between VCC and node LED_ANODE.
* Connect the Anode (long leg) of D1 to node LED_ANODE.
* Connect the Cathode (short leg, flat side) of D1 to node COLL.

Conceptual block diagram

Conceptual block diagram — Transistor Switch (NPN)
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: The transistor as a light switch

1. CONTROL PATH (Input Stage)
   Flow: VCC triggers the Base when S1 is pressed. R2 ensures Base is 0 V when S1 is open.

   [ VCC ] --> [ S1: Button ] --(INPUT_SIG)--> [ R1: 10k ] --(BASE)--+--> [ Q1: Base ]
                                                                     |
                                                                     +--> [ R2: 100k ] --> [ GND ]

2. LOAD PATH (Output Stage)
   Flow: Current flows from VCC through the LED into the Transistor Collector.

   [ VCC ] --> [ R3: 330R ] --(LED_ANODE)--> [ D1: Red LED ] --(COLL)--> [ Q1: Collector ]

3. COMMON RETURN (Grounding)
   Flow: The transistor completes the circuit to Ground.

   [ Q1: Emitter ] --> [ GND ]
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: The transistor as a light switch
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Perform these steps with a multimeter to verify the transistor regions of operation.

  1. Test Cut-off Region (Switch Open):

    • Ensure S1 is not pressed.
    • Measure voltage between Base and Emitter (VBE). Result should be 0 V.
    • Measure voltage between Collector and Emitter (VCE). Result should be close to 9 V (Source voltage), indicating the switch is open.
    • Observe D1: It must be OFF.
  2. Test Saturation Region (Switch Closed):

    • Press and hold S1.
    • Measure voltage between Base and Emitter (VBE). Result should be approximately 0.65 V to 0.75 V.
    • Measure voltage between Collector and Emitter (VCE). Result should drop to < 0.2 V. This voltage drop proves the transistor is acting as a closed switch (Saturation).
    • Observe D1: It must turn ON brightly.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: The transistor as a light switch
* Improved Netlist with robust switch modelling

.width out=256

* --- Power Supply ---
* V1: 9 V DC battery (Main circuit power)
V1 VCC 0 DC 9

* --- User Input Trigger (S1) ---
* S1: Tactile Push-button (Normally Open) connecting VCC to INPUT_SIG.
* Modeled using a Voltage-Controlled Switch (S1) driven by a control pulse (V_ACT).
* V_ACT simulates the user pressing the button (Logic 0 -> 1 -> 0).
V_ACT ACTUATE 0 PULSE(0 5 1ms 100u 100u 5ms 20ms)
S1 VCC INPUT_SIG ACTUATE 0 SW_TACTILE

* --- Input Stage ---
* R1: 10 kOhm, Base current limiting
R1 INPUT_SIG BASE 10k

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: The transistor as a light switch
* Improved Netlist with robust switch modelling

.width out=256

* --- Power Supply ---
* V1: 9 V DC battery (Main circuit power)
V1 VCC 0 DC 9

* --- User Input Trigger (S1) ---
* S1: Tactile Push-button (Normally Open) connecting VCC to INPUT_SIG.
* Modeled using a Voltage-Controlled Switch (S1) driven by a control pulse (V_ACT).
* V_ACT simulates the user pressing the button (Logic 0 -> 1 -> 0).
V_ACT ACTUATE 0 PULSE(0 5 1ms 100u 100u 5ms 20ms)
S1 VCC INPUT_SIG ACTUATE 0 SW_TACTILE

* --- Input Stage ---
* R1: 10 kOhm, Base current limiting
R1 INPUT_SIG BASE 10k

* R2: 100 kOhm, Pull-down resistor (keeps Base low when S1 is open)
R2 BASE 0 100k

* --- Transistor Switch ---
* Q1: 2N2222 NPN Transistor
* Connections: Collector=COLL, Base=BASE, Emitter=0(GND)
Q1 COLL BASE 0 2N2222

* --- Output Load ---
* R3: 330 Ohm, LED current limiting resistor
R3 VCC LED_ANODE 330

* D1: Red LED
* Connections: Anode=LED_ANODE, Cathode=COLL
D1 LED_ANODE COLL RED_LED

* --- Component Models ---
* Switch Model: Added hysteresis (Vh) and relaxed Ron for better convergence
.model SW_TACTILE SW(Vt=2.5 Vh=0.1 Ron=1 Roff=100Meg)

* Transistor Model: Standard 2N2222 parameters
.model 2N2222 NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8p CJE=25p TR=46.9n TF=411p ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=1 RE=0.1)

* LED Model: Generic Red LED parameters
.model RED_LED D(IS=93.2p RS=42m N=3.73 BV=5 IBV=10u CJO=2.97p VJ=0.75 M=0.33 TT=4.32u)

* --- Analysis Commands ---
.op
* Simulate for 10ms to capture the button press event
.tran 100u 10ms

* --- Output Directives ---
* Printing INPUT (Switch output) and OUTPUT (Collector voltage) first
.print tran V(INPUT_SIG) V(COLL) V(BASE) V(LED_ANODE) V(ACTUATE)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (170 rows)
Index   time            v(input_sig)    v(coll)         v(base)         v(led_anode)    v(actuate)
0	0.000000e+00	9.890018e-03	8.982941e+00	8.991007e-03	9.000000e+00	0.000000e+00
1	1.000000e-06	9.890019e-03	8.982941e+00	8.991008e-03	9.000000e+00	0.000000e+00
2	2.000000e-06	9.890019e-03	8.982941e+00	8.991008e-03	9.000000e+00	0.000000e+00
3	4.000000e-06	9.890021e-03	8.982941e+00	8.991010e-03	9.000000e+00	0.000000e+00
4	8.000000e-06	9.890021e-03	8.982941e+00	8.991010e-03	9.000000e+00	0.000000e+00
5	1.600000e-05	9.890021e-03	8.982941e+00	8.991010e-03	9.000000e+00	0.000000e+00
6	3.200000e-05	9.890021e-03	8.982941e+00	8.991010e-03	9.000000e+00	0.000000e+00
7	6.400000e-05	9.890021e-03	8.982942e+00	8.991010e-03	9.000000e+00	0.000000e+00
8	1.280000e-04	9.890021e-03	8.982942e+00	8.991010e-03	9.000000e+00	0.000000e+00
9	2.280000e-04	9.890021e-03	8.982943e+00	8.991010e-03	9.000000e+00	0.000000e+00
10	3.280000e-04	9.890021e-03	8.982944e+00	8.991010e-03	9.000000e+00	0.000000e+00
11	4.280000e-04	9.890021e-03	8.982945e+00	8.991010e-03	9.000000e+00	0.000000e+00
12	5.280000e-04	9.890021e-03	8.982946e+00	8.991010e-03	9.000000e+00	0.000000e+00
13	6.280000e-04	9.890021e-03	8.982947e+00	8.991010e-03	9.000000e+00	0.000000e+00
14	7.280000e-04	9.890021e-03	8.982948e+00	8.991010e-03	9.000000e+00	0.000000e+00
15	8.280000e-04	9.890021e-03	8.982949e+00	8.991010e-03	9.000000e+00	0.000000e+00
16	9.280000e-04	9.890021e-03	8.982950e+00	8.991010e-03	9.000000e+00	0.000000e+00
17	1.000000e-03	9.890021e-03	8.982950e+00	8.991010e-03	9.000000e+00	0.000000e+00
18	1.010000e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	5.000000e-01
19	1.027500e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	1.375000e+00
20	1.032344e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	1.617187e+00
21	1.040820e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	2.041016e+00
22	1.043167e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	2.158325e+00
23	1.047272e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	2.363617e+00
... (146 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: The transistor as a light switch
* Improved Netlist with robust switch modelling

.width out=256

* --- Power Supply ---
* V1: 9 V DC battery (Main circuit power)
V1 VCC 0 DC 9

* --- User Input Trigger (S1) ---
* S1: Tactile Push-button (Normally Open) connecting VCC to INPUT_SIG.
* Modeled using a Voltage-Controlled Switch (S1) driven by a control pulse (V_ACT).
* V_ACT simulates the user pressing the button (Logic 0 -> 1 -> 0).
V_ACT ACTUATE 0 PULSE(0 5 1ms 100u 100u 5ms 20ms)
S1 VCC INPUT_SIG ACTUATE 0 SW_TACTILE

* --- Input Stage ---
* R1: 10 kOhm, Base current limiting
R1 INPUT_SIG BASE 10k

* R2: 100 kOhm, Pull-down resistor (keeps Base low when S1 is open)
R2 BASE 0 100k

* --- Transistor Switch ---
* Q1: 2N2222 NPN Transistor
* Connections: Collector=COLL, Base=BASE, Emitter=0(GND)
Q1 COLL BASE 0 2N2222

* --- Output Load ---
* R3: 330 Ohm, LED current limiting resistor
R3 VCC LED_ANODE 330

* D1: Red LED
* Connections: Anode=LED_ANODE, Cathode=COLL
D1 LED_ANODE COLL RED_LED

* --- Component Models ---
* Switch Model: Added hysteresis (Vh) and relaxed Ron for better convergence
.model SW_TACTILE SW(Vt=2.5 Vh=0.1 Ron=1 Roff=100Meg)

* Transistor Model: Standard 2N2222 parameters
.model 2N2222 NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8p CJE=25p TR=46.9n TF=411p ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=1 RE=0.1)

* LED Model: Generic Red LED parameters
.model RED_LED D(IS=93.2p RS=42m N=3.73 BV=5 IBV=10u CJO=2.97p VJ=0.75 M=0.33 TT=4.32u)

* --- Analysis Commands ---
.op
* Simulate for 10ms to capture the button press event
.tran 100u 10ms

* --- Output Directives ---
* Printing INPUT (Switch output) and OUTPUT (Collector voltage) first
.print tran V(INPUT_SIG) V(COLL) V(BASE) V(LED_ANODE) V(ACTUATE)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Swapping Collector and Emitter:
    • Error: The LED turns on but looks dim or fails to switch completely. The transistor may overheat.
    • Solution: Double-check the pinout of the 2N2222 (E-B-C or C-B-E depending on the specific package/datasheet).
  2. Omitting the Base Resistor (R1):
    • Error: Connecting the switch directly to the Base causes a massive current flow from Base to Emitter, destroying the transistor instantly.
    • Solution: Always include a limiting resistor (R1) in series with the Base.
  3. Floating Base (Missing R2):
    • Error: The LED might flicker or glow faintly when the switch is open because the Base picks up electromagnetic noise.
    • Solution: Ensure R2 (Pull-down) is connected to ground to discharge the Base capacitance when the switch is open.

Troubleshooting

  • Symptom: LED is always ON, even when the button is not pressed.
    • Cause: Transistor C-E shorted internally or R2 is missing/disconnected.
    • Fix: Replace Q1 and check R2 connection to Ground.
  • Symptom: LED does not turn ON when button is pressed.
    • Cause: LED connected backwards, R1 value too high (preventing saturation), or R3 too high.
    • Fix: Check LED polarity. Verify R1 is 10 kΩ and R3 is 330 Ω.
  • Symptom: LED is very dim when ON.
    • Cause: Transistor is in the «Active» region, not «Saturation».
    • Fix: Decrease R1 slightly (e.g., to 4.7 kΩ) to increase Base current (IB) and force full saturation.

Possible improvements and extensions

  1. High Power Control: Replace the LED and R3 with a 9 V Relay (remember to add a flyback diode in parallel with the relay coil) to control a household lamp.
  2. Automatic Night Light: Replace the tactile button (S1) with an LDR (Light Dependent Resistor) and adjust the position of resistors to create a sensor that turns on the LED in the dark.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary objective of the circuit described in the text?




Question 2: Which component acts as the electronic switch in the described circuit?




Question 3: What is the state of the transistor when the button is released (Idle State)?




Question 4: In the Cut-off state, what is the approximate value of the collector current (Ic)?




Question 5: What is the status of the LED when the transistor enters the Saturation state?




Question 6: What is the approximate voltage drop across the collector-emitter (Vce) during saturation?




Question 7: What is the primary function of the base resistor (often R1) in a BJT switching circuit?




Question 8: What is the purpose of a pull-down resistor (often R2) connected to the Base?




Question 9: What is the typical Base-Emitter voltage (Vbe) when the transistor is conducting?




Question 10: Which of the following is a practical use case mentioned for this BJT circuit?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Linear supply voltage smoothing

Linear supply voltage smoothing prototype (Maker Style)

Level: Medium. Compare voltage ripple in a basic power supply by varying filtering capacitance under load.

Objective and use case

In this practical case, you will build a Full-Wave Bridge Rectifier circuit coupled with a selectable filter capacitor bank and a resistive load. You will analyze how the value of the filter capacitor affects the quality of the DC output by measuring the «ripple» voltage superimposed on the DC signal.

  • Audio Power Supplies: Reducing 50/60 Hz hum in amplifiers and speakers.
  • Digital Logic Power: Ensuring stable voltage levels to prevent microcontroller resets or erratic behavior.
  • Sensor Conditioning: Providing clean DC power to analog sensors for accurate readings.
  • Battery Charging: Smoothing the charging current to prolong battery life.

Expected outcome:
* Waveform Transformation: Visual observation of AC sine wave converting to pulsing DC, then to smooth DC.
* Ripple Voltage (Vripple): A high peak-to-peak ripple voltage (> 5 V) with a small capacitor (10 µF).
* Smoothing Effect: A significantly reduced ripple voltage (< 0.5 V) when switching to a large capacitor (470 µF).
* Target Audience: Intermediate electronics students and hobbyists familiar with AC/DC concepts.

Materials

  • V1: 12 V (RMS) AC transformer secondary or AC function generator (60 Hz), function: AC power source.
  • D1: 1N4007 Diode, function: Bridge rectifier top-left.
  • D2: 1N4007 Diode, function: Bridge rectifier top-right.
  • D3: 1N4007 Diode, function: Bridge rectifier bottom-left.
  • D4: 1N4007 Diode, function: Bridge rectifier bottom-right.
  • R1: 220 Ω resistor (2 Watt rating recommended), function: Static Load.
  • C1: 10 µF electrolytic capacitor (25 V or higher), function: Low-value filter.
  • C2: 470 µF electrolytic capacitor (25 V or higher), function: High-value filter.
  • S1: SPDT Switch or jumper wire, function: Selects between C1 and C2.
  • Test Equipment: Oscilloscope (preferred) or Multimeter with AC/DC measurement capabilities.

Wiring guide

Construct the circuit using the following node connections. Ensure electrolytic capacitors are connected with correct polarity (Positive terminal to V_DC, Negative terminal to 0 / GND).

  • V1 (Source): Connects between node AC_L and node AC_N.
  • D1: Anode connects to AC_L, Cathode connects to V_DC.
  • D2: Anode connects to AC_N, Cathode connects to V_DC.
  • D3: Anode connects to 0 (GND), Cathode connects to AC_L.
  • D4: Anode connects to 0 (GND), Cathode connects to AC_N.
  • R1 (Load): Connects between node V_DC and node 0 (GND).
  • C1 (Test Case A): Positive terminal to V_DC, Negative terminal to 0 (GND).
  • C2 (Test Case B): Positive terminal to V_DC, Negative terminal to 0 (GND) (Replace C1 with C2 for second test).

Conceptual block diagram

Conceptual block diagram — LM7812 Linear Power Supply Smoothing
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ INPUT SOURCE ]              [ RECTIFICATION ]                [ FILTER STAGE ]                 [ OUTPUT LOAD ]

                                                                  +-> [ Capacitor C1 ] -+
                                                                  |     (10 uF)         |
 [ AC Source V1 ] --(12 V AC)--> [ Bridge Rectifier ] --(Raw DC)-->+                     +--(V_DC)--> [ Load Resistor R1 ]
    (12 V RMS)                   [  D1, D2, D3, D4  ]              |   [ Switch S1  ]    |            (220 Ohm)
                                                                  +-> [ Capacitor C2 ] -+                |
                                                                        (470 uF)                         |
                                                                                                         |
                                                                                                         v
                                                                                                  [ Oscilloscope ]
                                                                                                  (Measure Ripple)
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Linear supply voltage smoothing
Generated from the validated SPICE netlist for this case.

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Measurements and tests

Follow these steps to validate the smoothing efficiency:

  1. Baseline (No Capacitor): Temporarily remove any capacitor. Measure V_DC with an oscilloscope. You should see a full-wave rectified signal (humps going to 0 V) at 120 Hz (or 100 Hz).
  2. Small Capacitor Test (C1 = 10 µ F):
    • Insert $C1$.
    • Measure the peak voltage (Vpeak) and the minimum valley voltage (Vmin).
    • Calculate Ripple: Vripple = Vpeak – Vmin.
    • Expectation: Significant sawtooth ripple (fast discharge).
  3. Large Capacitor Test (C2 = 470 µ F):
    • Replace $C1$ with $C2$.
    • Measure Vpeak and Vmin again.
    • Expectation: The DC line is much flatter; Vmin stays close to Vpeak.
  4. DC Average: Switch your multimeter to DC Volts. Compare the reading of $C1$ vs $C2$. The average voltage with $C2$ will be higher because the capacitor maintains the charge longer.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Linear supply voltage smoothing
*
* Description:
* This netlist simulates a full-wave bridge rectifier power supply with a 
* selectable smoothing capacitor.
* - 0ms to 100ms: C1 (10uF) is connected (High Ripple case).
* - 100ms to 200ms: C2 (470uF) is connected (Low Ripple case), simulating
*   switch S1 toggling.
*
* Connections:
* V1 (AC Source) -> Nodes AC_L, AC_N
* D1-D4 (Bridge) -> Nodes AC_L, AC_N, V_DC, 0 (GND)
* R1 (Load)      -> Nodes V_DC, 0
* S1 (Switch)    -> Modeled via S_C1 and S_C2 connecting V_DC to C1/C2
*
* -----------------------------------------------------------------------------

* --- AC Power Source ---
* 12V RMS AC, 60Hz. 
* Peak Voltage = 12 * sqrt(2) = 16.97 V
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Linear supply voltage smoothing
*
* Description:
* This netlist simulates a full-wave bridge rectifier power supply with a 
* selectable smoothing capacitor.
* - 0ms to 100ms: C1 (10uF) is connected (High Ripple case).
* - 100ms to 200ms: C2 (470uF) is connected (Low Ripple case), simulating
*   switch S1 toggling.
*
* Connections:
* V1 (AC Source) -> Nodes AC_L, AC_N
* D1-D4 (Bridge) -> Nodes AC_L, AC_N, V_DC, 0 (GND)
* R1 (Load)      -> Nodes V_DC, 0
* S1 (Switch)    -> Modeled via S_C1 and S_C2 connecting V_DC to C1/C2
*
* -----------------------------------------------------------------------------

* --- AC Power Source ---
* 12V RMS AC, 60Hz. 
* Peak Voltage = 12 * sqrt(2) = 16.97 V
V1 AC_L AC_N SIN(0 16.97 60)

* --- Bridge Rectifier (1N4007) ---
* D1: Anode=AC_L, Cathode=V_DC
D1 AC_L V_DC D1N4007
* D2: Anode=AC_N, Cathode=V_DC
D2 AC_N V_DC D1N4007
* D3: Anode=GND, Cathode=AC_L
D3 0 AC_L D1N4007
* D4: Anode=GND, Cathode=AC_N
D4 0 AC_N D1N4007

* --- Load Resistor ---
* 220 Ohm resistor across the DC output
R1 V_DC 0 220

* --- Filter Capacitors & Switching Logic ---
* We simulate the SPDT switch S1 by using two voltage-controlled switches.
* S_C1 connects V_DC to C1. S_C2 connects V_DC to C2.
* Control signals ensure only one is active at a time (break-before-make effectively).

* Capacitor C1 (10uF) path
S_C1 V_DC NET_C1 CTRL_C1 0 SW_MODEL
C1 NET_C1 0 10u

* Capacitor C2 (470uF) path
S_C2 V_DC NET_C2 CTRL_C2 0 SW_MODEL
C2 NET_C2 0 470u

* --- Control Signals (Dynamic Stimuli) ---
* CTRL_C1: Starts High (5V), goes Low (0V) at 100ms.
* Keeps C1 connected for the first 100ms.
V_CTRL_C1 CTRL_C1 0 PULSE(5 0 100m 1u 1u 1 2)

* CTRL_C2: Starts Low (0V), goes High (5V) at 100ms.
* Connects C2 for the remainder of the simulation.
V_CTRL_C2 CTRL_C2 0 PULSE(0 5 100m 1u 1u 1 2)

* --- Component Models ---
* Generic model for 1N4007 Power Diode
.model D1N4007 D(IS=7.03n RS=0.034 N=1.8 BV=1000 IBV=5u CJO=10p TT=100n)

* Ideal Switch Model (Threshold=2.5V, On-Res=10mOhm, Off-Res=100MegOhm)
.model SW_MODEL SW(Vt=2.5 Ron=0.01 Roff=100Meg)

* --- Analysis Directives ---
* Transient analysis: 200ms total time, 50us step size.
* This captures approx 6 cycles with C1 and 6 cycles with C2.
.tran 50u 200m

* Print directives for simulation log/plotting
.print tran V(V_DC) V(AC_L) V(AC_N)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (4050 rows)
Index   time            v(v_dc)         v(ac_l)         v(ac_n)
0	0.000000e+00	6.658603e-23	4.156609e-18	4.156609e-18
1	5.000000e-07	1.885342e-19	1.599385e-03	-1.59938e-03
2	1.000000e-06	6.893339e-12	3.198770e-03	-3.19877e-03
3	2.000000e-06	3.416858e-11	6.397539e-03	-6.39754e-03
4	4.000000e-06	1.718574e-10	1.279507e-02	-1.27951e-02
5	8.000000e-06	9.966330e-10	2.559012e-02	-2.55901e-02
6	1.325366e-05	3.861142e-09	4.239524e-02	-4.23952e-02
7	2.095388e-05	1.446061e-08	6.702595e-02	-6.70259e-02
8	3.129676e-05	5.099200e-08	1.001088e-01	-1.00109e-01
9	4.482862e-05	1.835180e-07	1.433897e-01	-1.43390e-01
10	6.128867e-05	6.888081e-07	1.960312e-01	-1.96031e-01
11	8.042390e-05	2.827323e-06	2.572195e-01	-2.57217e-01
12	1.019046e-04	1.303092e-05	3.258956e-01	-3.25883e-01
13	1.254895e-04	6.815023e-05	4.012964e-01	-4.01228e-01
14	1.509795e-04	4.024321e-04	4.828893e-01	-4.82487e-01
15	1.782228e-04	2.626479e-03	5.709779e-01	-5.68351e-01
16	2.071492e-04	1.723315e-02	6.705660e-01	-6.53333e-01
17	2.380619e-04	8.388777e-02	8.024272e-01	-7.18539e-01
18	2.734880e-04	2.529945e-01	9.997734e-01	-7.46779e-01
19	3.097680e-04	4.785526e-01	1.227902e+00	-7.49349e-01
20	3.521718e-04	7.463483e-01	1.496384e+00	-7.50036e-01
21	3.938443e-04	1.008721e+00	1.759554e+00	-7.50833e-01
22	4.438443e-04	1.322891e+00	2.074586e+00	-7.51694e-01
23	4.938443e-04	1.636032e+00	2.388601e+00	-7.52568e-01
... (4026 more rows) ...


Reference SPICE netlist (ngspice)

* Linear supply voltage smoothing
*
* Description:
* This netlist simulates a full-wave bridge rectifier power supply with a
* selectable smoothing capacitor.
* - 0ms to 100ms: C1 (10uF) is connected (High Ripple case).
* - 100ms to 200ms: C2 (470uF) is connected (Low Ripple case), simulating
*   switch S1 toggling.
*
* Connections:
* V1 (AC Source) -> Nodes AC_L, AC_N
* D1-D4 (Bridge) -> Nodes AC_L, AC_N, V_DC, 0 (GND)
* R1 (Load)      -> Nodes V_DC, 0
* S1 (Switch)    -> Modeled via S_C1 and S_C2 connecting V_DC to C1/C2
*
* -----------------------------------------------------------------------------

* --- AC Power Source ---
* 12V RMS AC, 60Hz.
* Peak Voltage = 12 * sqrt(2) = 16.97 V
V1 AC_L AC_N SIN(0 16.97 60)

* --- Bridge Rectifier (1N4007) ---
* D1: Anode=AC_L, Cathode=V_DC
D1 AC_L V_DC D1N4007
* D2: Anode=AC_N, Cathode=V_DC
D2 AC_N V_DC D1N4007
* D3: Anode=GND, Cathode=AC_L
D3 0 AC_L D1N4007
* D4: Anode=GND, Cathode=AC_N
D4 0 AC_N D1N4007

* --- Load Resistor ---
* 220 Ohm resistor across the DC output
R1 V_DC 0 220

* --- Filter Capacitors & Switching Logic ---
* We simulate the SPDT switch S1 by using two voltage-controlled switches.
* S_C1 connects V_DC to C1. S_C2 connects V_DC to C2.
* Control signals ensure only one is active at a time (break-before-make effectively).

* Capacitor C1 (10uF) path
S_C1 V_DC NET_C1 CTRL_C1 0 SW_MODEL
C1 NET_C1 0 10u

* Capacitor C2 (470uF) path
S_C2 V_DC NET_C2 CTRL_C2 0 SW_MODEL
C2 NET_C2 0 470u

* --- Control Signals (Dynamic Stimuli) ---
* CTRL_C1: Starts High (5V), goes Low (0V) at 100ms.
* Keeps C1 connected for the first 100ms.
V_CTRL_C1 CTRL_C1 0 PULSE(5 0 100m 1u 1u 1 2)

* CTRL_C2: Starts Low (0V), goes High (5V) at 100ms.
* Connects C2 for the remainder of the simulation.
V_CTRL_C2 CTRL_C2 0 PULSE(0 5 100m 1u 1u 1 2)

* --- Component Models ---
* Generic model for 1N4007 Power Diode
.model D1N4007 D(IS=7.03n RS=0.034 N=1.8 BV=1000 IBV=5u CJO=10p TT=100n)

* Ideal Switch Model (Threshold=2.5V, On-Res=10mOhm, Off-Res=100MegOhm)
.model SW_MODEL SW(Vt=2.5 Ron=0.01 Roff=100Meg)

* --- Analysis Directives ---
* Transient analysis: 200ms total time, 50us step size.
* This captures approx 6 cycles with C1 and 6 cycles with C2.
.tran 50u 200m

* Print directives for simulation log/plotting
.print tran V(V_DC) V(AC_L) V(AC_N)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  • Reversed Capacitor Polarity: Electrolytic capacitors will explode if connected backwards. Solution: Ensure the side marked with a stripe (negative) connects to the 0 (GND) node and the other side to the positive rectifier output.
  • Under-rated Resistor Power: A 220 Ω resistor at ~15 V DC dissipates about 1 Watt (P = V^2 / R). Using a standard 1/4 W resistor will burn it. Solution: Use a power resistor (2 W+) or increase resistance to 1 kΩ (though this reduces ripple visibility).
  • Measuring Ripple on DC Setting: A standard multimeter on DC mode averages the voltage, hiding the ripple. Solution: Use an oscilloscope for visual analysis, or set the multimeter to AC mode to measure the RMS value of the ripple component only.

Troubleshooting

  • Symptom: No output voltage at V_DC.
    • Cause: AC source not on or bridge diodes open/connected incorrectly.
    • Fix: Check V1 output and verify diode orientation (ring marks on cathodes).
  • Symptom: Ripple does not change when swapping capacitors.
    • Cause: Load resistor $R1$ is missing or open circuit. Without a load, the capacitor has no path to discharge, so voltage stays at peak regardless of capacitance.
    • Fix: Ensure $R1$ is securely connected parallel to the capacitor.
  • Symptom: Fuse blows or transformer hums loudly.
    • Cause: Short circuit in the bridge (e.g., D1 and D3 shorting AC mains).
    • Fix: Power off immediately and check wiring. Ensure AC_L and AC_N are not directly connected to 0 or each other.

Possible improvements and extensions

  1. Voltage Regulator: Add an LM7812 or LM317 linear regulator after the capacitor to see how active regulation eliminates the remaining ripple.
  2. RC Pi Filter: Add a series resistor and a second capacitor ($C-R-C$) to create a passive low-pass filter, further reducing ripple without active components (at the cost of voltage drop).

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary objective of the practical case described in the text?




Question 2: Which component is responsible for converting the AC sine wave into pulsing DC in the described circuit?




Question 3: In the context of audio power supplies, what is a key benefit of reducing voltage ripple?




Question 4: What is the expected outcome for ripple voltage when using a small capacitor (10 µF)?




Question 5: Why is stable voltage important for Digital Logic Power as mentioned in the use cases?




Question 6: According to the expected outcome, how does the waveform transform through the circuit stages?




Question 7: Based on the diagram context, what is the RMS voltage of the AC source?




Question 8: Which component is placed in parallel with the capacitor bank to simulate a load?




Question 9: What is the specific value of the larger capacitor (C2) mentioned in the diagram context?




Question 10: How does smoothing the charging current benefit battery charging applications?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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