Practical case: RC audio low-pass filter

RC audio low-pass filter prototype (Maker Style)

Level: Medium — Design and analyze a circuit that attenuates high frequencies using a capacitor and a resistor to verify the cutoff frequency.

Objective and use case

In this practical case, you will build a passive first-order Low-Pass Filter (LPF) using a resistor and a capacitor connected in series. You will analyze how the capacitor’s reactance changes with frequency, allowing low frequencies to pass while attenuating signals above a calculated cutoff point.

Why it is useful:
* Audio noise reduction: Removes high-frequency hiss or static from audio recordings.
* Subwoofer crossovers: Directs only low-frequency bass notes to the subwoofer driver.
* Signal conditioning: Acts as an anti-aliasing filter before Analog-to-Digital Conversion (ADC) to prevent digital artifacts.
* Power supply smoothing: Filters out high-frequency ripple noise from DC power lines.

Expected outcome:
* Passband: Frequencies below ~1 kHz retain approximately their original amplitude (Vin ≈ Vout).
* Cutoff point: At the calculated cutoff frequency (fc), the output voltage drops to approximately 70.7% of the input voltage (-3 dB).
* Stopband: Frequencies significantly higher than 1 kHz are heavily attenuated.
* Phase shift: Observe a phase lag of -45° at the cutoff frequency.

Target audience and level: Electronics students and audio enthusiasts; Level: Medium.

Materials

  • V1: AC Voltage Source (Sine Wave, 5 Vpk, tunable frequency), function: Input audio signal simulation.
  • R1: 1.6 kΩ resistor, function: Current limiting and voltage division partner.
  • C1: 100 nF capacitor (ceramic or film), function: Frequency-dependent shunt to ground.
  • Measurement Tool: Oscilloscope (Dual channel) or Bode Plotter.

Wiring guide

Construct the circuit using the following connections. Note the explicit node names for analysis.

  • V1 (Source): Connect the positive terminal to node VIN and the negative terminal to node 0 (GND).
  • R1: Connect one leg to node VIN and the other leg to node VOUT.
  • C1: Connect one leg to node VOUT and the other leg to node 0 (GND).
  • Oscilloscope Ch1: Connect probe tip to VIN and ground clip to 0.
  • Oscilloscope Ch2: Connect probe tip to VOUT and ground clip to 0.

Conceptual block diagram

Conceptual block diagram — RC Low Pass Filter
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ SIGNAL SOURCE ]               [ RC FILTER STAGE ]                 [ MEASUREMENT ]

                              +--------------------------------------> [ Scope Ch1 (Input) ]
                              |
[ V1: AC Source ] --(VIN)-->--+--> [ R1: 1.6k Resistor ] --(VOUT)-->--+--> [ Scope Ch2 (Output) ]
      (5 Vpk)                                                         |
                                                                      +--> [ C1: 100nF Cap ] --> GND
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: RC audio low-pass filter
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Follow these steps to validate the filter design (fc ≈ 1 kHz):

  1. Low Frequency Test (Passband):

    • Set V1 to 100 Hz.
    • Measure Vout peak-to-peak. It should be nearly identical to Vin (approx. 5 V).
  2. Cutoff Frequency Verification (fc):

    • Increase V1 frequency to 1 kHz.
    • Measure Vout. It should drop to approximately 0.707 × Vin (approx. 3.53 V).
    • Measure the phase difference between Ch1 and Ch2. Vout should lag Vin by roughly 45°.
  3. High Frequency Test (Stopband):

    • Set V1 to 10 kHz (one decade above cutoff).
    • Measure Vout. The amplitude should be significantly attenuated (approx. 0.5 V or -20 dB relative to input).
  4. Bode Plot Analysis (Optional):

    • If using a simulation or Bode plotter, sweep from 10 Hz to 100 kHz. Observe the «roll-off» slope of -20 dB/decade after the cutoff point.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: RC audio low-pass filter

* --- Components per BOM and Wiring Guide ---
* V1: AC Voltage Source (Sine Wave, 5 Vpk, 1kHz, AC 1V for Bode)
* Connected: Positive -> VIN, Negative -> 0 (GND)
V1 VIN 0 DC 0 AC 1 SIN(0 5 1000)

* R1: 1.6 kOhm resistor
* Connected: VIN -> VOUT
R1 VIN VOUT 1.6k

* C1: 100 nF capacitor
* Connected: VOUT -> 0 (GND)
C1 VOUT 0 100n

* --- Simulation Commands ---
* Using .control block to sequence analyses and printing correctly in ngspice
.control
    * Transient Analysis: 1kHz signal, run for 5ms
    tran 10u 5ms
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

* Practical case: RC audio low-pass filter

* --- Components per BOM and Wiring Guide ---
* V1: AC Voltage Source (Sine Wave, 5 Vpk, 1kHz, AC 1V for Bode)
* Connected: Positive -> VIN, Negative -> 0 (GND)
V1 VIN 0 DC 0 AC 1 SIN(0 5 1000)

* R1: 1.6 kOhm resistor
* Connected: VIN -> VOUT
R1 VIN VOUT 1.6k

* C1: 100 nF capacitor
* Connected: VOUT -> 0 (GND)
C1 VOUT 0 100n

* --- Simulation Commands ---
* Using .control block to sequence analyses and printing correctly in ngspice
.control
    * Transient Analysis: 1kHz signal, run for 5ms
    tran 10u 5ms
    * Print transient results (Oscilloscope)
    print V(VIN) V(VOUT)

    * AC Analysis: Bode Plot, 10 Hz to 100 kHz
    ac dec 10 10 100k
    * Print AC results (Bode Plotter)
    print V(VOUT)

    * Operating Point
    op
.endc

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (512 rows)
Index   time            v(vin)          v(vout)
0	0.000000e+00	0.000000e+00	0.000000e+00
1	1.000000e-07	3.141592e-03	1.962269e-06
2	1.084035e-07	3.405596e-03	2.141025e-06
3	1.252105e-07	3.933604e-03	2.526248e-06
4	1.588245e-07	4.989618e-03	3.462948e-06
5	2.260525e-07	7.101647e-03	6.001184e-06
6	3.605086e-07	1.132570e-02	1.373560e-05
7	6.294206e-07	1.977378e-02	3.982505e-05
8	1.167245e-06	3.666975e-02	1.343969e-04
9	2.242893e-06	7.046023e-02	4.923968e-04
10	4.394190e-06	1.380300e-01	1.878099e-03
11	8.696783e-06	2.730815e-01	7.282571e-03
12	1.730197e-05	5.424874e-01	2.825846e-02
13	2.730197e-05	8.535162e-01	6.884897e-02
14	3.730197e-05	1.161176e+00	1.257276e-01
15	4.730197e-05	1.464254e+00	1.976662e-01
16	5.730197e-05	1.761553e+00	2.834382e-01
17	6.730197e-05	2.051900e+00	3.818193e-01
18	7.730197e-05	2.334149e+00	4.915893e-01
19	8.730197e-05	2.607186e+00	6.115335e-01
20	9.730197e-05	2.869934e+00	7.404442e-01
21	1.073020e-04	3.121356e+00	8.771230e-01
22	1.173020e-04	3.360458e+00	1.020383e+00
23	1.273020e-04	3.586299e+00	1.169049e+00
... (488 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: RC audio low-pass filter

* --- Components per BOM and Wiring Guide ---
* V1: AC Voltage Source (Sine Wave, 5 Vpk, 1kHz, AC 1V for Bode)
* Connected: Positive -> VIN, Negative -> 0 (GND)
V1 VIN 0 DC 0 AC 1 SIN(0 5 1000)

* R1: 1.6 kOhm resistor
* Connected: VIN -> VOUT
R1 VIN VOUT 1.6k

* C1: 100 nF capacitor
* Connected: VOUT -> 0 (GND)
C1 VOUT 0 100n

* --- Simulation Commands ---
* Using .control block to sequence analyses and printing correctly in ngspice
.control
    * Transient Analysis: 1kHz signal, run for 5ms
    tran 10u 5ms
    * Print transient results (Oscilloscope)
    print V(VIN) V(VOUT)

    * AC Analysis: Bode Plot, 10 Hz to 100 kHz
    ac dec 10 10 100k
    * Print AC results (Bode Plotter)
    print V(VOUT)

    * Operating Point
    op
.endc

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Swapping components (High-Pass vs. Low-Pass):
    • Error: Connecting C1 in series and R1 to ground creates a High-Pass filter.
    • Solution: Ensure the Capacitor is the component connected between the output node and Ground.
  2. Ignoring Load Impedance:
    • Error: Connecting a low-impedance load (like an 8 Ω speaker) directly to VOUT.
    • Solution: This passive filter has high output impedance. Use an op-amp buffer if driving a heavy load.
  3. Using Polarized Capacitors Incorrectly:
    • Error: Using an electrolytic capacitor with reverse polarity in an AC circuit without a DC bias.
    • Solution: For pure AC audio signals, use non-polarized capacitors (ceramic, film, or bipolar electrolytic).

Troubleshooting

  • Symptom: Vout is zero at all frequencies.
    • Cause: Short circuit across C1 or open circuit at R1.
    • Fix: Check continuity across C1; if it beeps, the capacitor is shorted or the node is grounded accidentally.
  • Symptom: No attenuation occurs at high frequencies.
    • Cause: C1 is open (broken) or R1 is shorted.
    • Fix: Replace C1. Verify R1 measures 1.6 kΩ.
  • Symptom: Cutoff frequency is totally wrong.
    • Cause: Incorrect component values (e.g., using 100 pF instead of 100 nF).
    • Fix: Double-check color codes on resistors and markings on capacitors (104 code = 100 nF).

Possible improvements and extensions

  1. Second-Order Filter: Cascade two RC stages in series to achieve a steeper roll-off (-40 dB/decade) for better noise rejection.
  2. Active Low-Pass Filter: Add an Operational Amplifier (Op-Amp) to create an active filter, allowing for signal gain and preventing the load from affecting the filter’s frequency response.

More Practical Cases on Prometeo.blog

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Go to Amazon

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Quick Quiz

Question 1: What is the primary function of the passive first-order Low-Pass Filter (LPF) described in the text?




Question 2: Which two components are connected in series to build this specific filter?




Question 3: At the cutoff frequency (fc), what percentage of the input voltage is the output voltage approximately equal to?




Question 4: What is the decibel drop at the cutoff frequency?




Question 5: Which of the following is NOT listed as a use case for this circuit?




Question 6: In the expected outcome, what happens to frequencies in the passband (below ~1 kHz)?




Question 7: Why is this filter useful before Analog-to-Digital Conversion (ADC)?




Question 8: How does the capacitor behave in this circuit to achieve filtering?




Question 9: What is a specific application of this filter in audio systems mentioned in the text?




Question 10: What does this circuit filter out from DC power lines?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Simple Transistor Timer

Simple Transistor Timer prototype (Maker Style)

Level: Basic. Build an off-delay circuit using the slow discharge of a capacitor to control a transistor.

Objective and use case

In this session, you will build an analog timer circuit that keeps an LED illuminated for a specific duration after a push-button is released. This demonstrates how a capacitor stores energy and discharges it over time to control a switching element (the transistor).

Why it is useful:
* Interior car lighting: Lights that fade out slowly after the door is closed.
* Staircase timers: Lighting that remains on long enough for someone to climb the stairs.
* Bathroom fans: Fans that continue running for a few minutes after being switched off to clear humidity.
* Debouncing: Smoothing out short, unwanted signal interruptions.

Expected outcome:
* Button Press: The LED turns ON immediately to full brightness.
* Button Release: The LED remains ON initially.
* Delay Phase: The LED gradually dims and turns OFF after a few seconds as the capacitor voltage drops.
* Target Audience: Students and hobbyists learning about RC time constants and transistor switching.

Materials

  • V1: 9 V DC supply, function: main power source.
  • S1: Push-button (Normally Open), function: charging trigger.
  • C1: 470 µF electrolytic capacitor, function: timing and energy storage.
  • R1: 10 kΩ resistor, function: discharge timing resistor.
  • R2: 470 Ω resistor, function: LED current limiting.
  • Q1: 2N2222 NPN transistor, function: current switch.
  • D1: Red LED, function: visual output indicator.

Wiring guide

Construct the circuit following these connections using the specific node names provided.

  • Power Supply:

    • Connect V1 positive terminal to node VCC.
    • Connect V1 negative terminal to node 0 (GND).
  • Input and Timing Network:

    • Connect S1 between node VCC and node VCAP.
    • Connect C1 positive terminal to node VCAP.
    • Connect C1 negative terminal to node 0.
    • Connect R1 between node VCAP and node BASE.
  • Transistor Switch:

    • Connect Q1 Base to node BASE.
    • Connect Q1 Emitter to node 0.
    • Connect Q1 Collector to node COL.
  • Output Load (LED):

    • Connect R2 between node VCC and node LED_A.
    • Connect D1 Anode to node LED_A.
    • Connect D1 Cathode to node COL.

Conceptual block diagram

Conceptual block diagram — Simple Transistor Timer
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ INPUT & TIMING ]                  [ LOGIC / SWITCH ]                 [ OUTPUT LOAD ]

(VCC 9 V) --+--(Power Path)--------------------------------------------------> [ Resistor R2 ]
           |                                                                        |
           |                                                                        v
     [ Button S1 ]                                                             [ LED D1 ]
           |                                                                        |
           v (Trigger)                                                              |
     [ Node VCAP ] --(Slow Discharge)--> [ Resistor R1 ] --(Base Sig)-->+           |
           |                                                            |           |
           + <--(Stores Charge)-- [ Capacitor C1 ]                      |           |
                                       |                                v           v
                                       v                        +-----------------------+
                                    [ GND ]                     |     TRANSISTOR Q1     |
                                                                | (Base)    (Collector) |
                                                                +-----------------------+
                                                                            |
                                                                            v (Emitter)
                                                                         [ GND ]
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Simple Transistor Timer
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Follow these steps to validate the circuit behavior using a multimeter.

  1. Initial State: Ensure S1 is not pressed. The LED should be OFF.
    • Measure voltage at VCAP. It should be near 0 V.
  2. Charging Phase: Press and hold S1.
    • Check: The LED turns ON immediately.
    • Measurement: The voltage at VCAP should instantly rise to approximately 9 V (VCC).
  3. Discharge Phase: Release S1 and start a stopwatch.
    • Observation: The LED remains lit.
    • Measurement: Monitor the voltage at VCAP. It will slowly decrease.
    • Threshold: When VCAP drops below approximately 1.4 V (V_BE + drop across R1), the LED will dim significantly and turn OFF.
  4. Time Constant: Record the time from release until the LED turns completely off.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Simple Transistor Timer

* --- Power Supply ---
* V1: 9 V DC supply
V1 VCC 0 DC 9

* --- Input and Timing Network ---
* S1: Push-button (Normally Open)
* Modeled as a Voltage Controlled Switch (S1) driven by a control pulse (V_S1_ACT)
* Connects VCC to VCAP when activated
S1 VCC VCAP CTRL 0 SW_MODEL

* Control signal for the button press simulation
* Press button at T=0.5s, hold for 0.5s, then release to allow discharge
V_S1_ACT CTRL 0 PULSE(0 5 0.5 1m 1m 0.5 20)

* C1: 470 µF electrolytic capacitor
C1 VCAP 0 470u

* R1: 10 kΩ resistor (Discharge path to Base)
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Simple Transistor Timer

* --- Power Supply ---
* V1: 9 V DC supply
V1 VCC 0 DC 9

* --- Input and Timing Network ---
* S1: Push-button (Normally Open)
* Modeled as a Voltage Controlled Switch (S1) driven by a control pulse (V_S1_ACT)
* Connects VCC to VCAP when activated
S1 VCC VCAP CTRL 0 SW_MODEL

* Control signal for the button press simulation
* Press button at T=0.5s, hold for 0.5s, then release to allow discharge
V_S1_ACT CTRL 0 PULSE(0 5 0.5 1m 1m 0.5 20)

* C1: 470 µF electrolytic capacitor
C1 VCAP 0 470u

* R1: 10 kΩ resistor (Discharge path to Base)
R1 VCAP BASE 10k

* --- Transistor Switch ---
* Q1: 2N2222 NPN transistor
* Connections: Collector=COL, Base=BASE, Emitter=0(GND)
Q1 COL BASE 0 2N2222MOD

* --- Output Load (LED) ---
* R2: 470 Ω resistor
R2 VCC LED_A 470

* D1: Red LED
* Connections: Anode=LED_A, Cathode=COL
D1 LED_A COL DLED

* --- Models ---
* Switch Model: Threshold 2.5V, Low On-Resistance
.model SW_MODEL SW(Vt=2.5 Ron=0.1 Roff=100Meg)

* NPN Transistor Model (Generic 2N2222)
.model 2N2222MOD NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=0.3 RE=0.2)

* LED Model (Red LED approx)
.model DLED D(IS=1u N=2 RS=10 BV=5 IBV=10u)

* --- Analysis Commands ---
* Transient analysis for 10 seconds to observe the long RC discharge (Tau ~ 4.7s)
.tran 10m 10s

* Output voltage of Capacitor, Base, Collector, and LED Anode
.print tran V(VCAP) V(BASE) V(COL) V(LED_A)

.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (2110 rows)
Index   time            v(vcap)         v(base)         v(col)
0	0.000000e+00	5.504285e-01	5.495835e-01	8.838023e+00
1	1.000000e-04	5.504285e-01	5.495836e-01	8.838088e+00
2	2.000000e-04	5.504285e-01	5.495835e-01	8.838088e+00
3	4.000000e-04	5.504285e-01	5.495835e-01	8.838088e+00
4	8.000000e-04	5.504285e-01	5.495835e-01	8.838088e+00
5	1.600000e-03	5.504285e-01	5.495835e-01	8.838088e+00
6	3.200000e-03	5.504285e-01	5.495835e-01	8.838088e+00
7	6.400000e-03	5.504285e-01	5.495835e-01	8.838088e+00
8	1.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
9	2.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
10	3.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
11	4.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
12	5.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
13	6.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
14	7.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
15	8.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
16	9.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
17	1.028000e-01	5.504285e-01	5.495835e-01	8.838088e+00
18	1.128000e-01	5.504285e-01	5.495835e-01	8.838088e+00
19	1.228000e-01	5.504285e-01	5.495835e-01	8.838088e+00
20	1.328000e-01	5.504285e-01	5.495835e-01	8.838088e+00
21	1.428000e-01	5.504285e-01	5.495835e-01	8.838088e+00
22	1.528000e-01	5.504285e-01	5.495835e-01	8.838088e+00
23	1.628000e-01	5.504285e-01	5.495835e-01	8.838088e+00
... (2086 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Simple Transistor Timer

* --- Power Supply ---
* V1: 9 V DC supply
V1 VCC 0 DC 9

* --- Input and Timing Network ---
* S1: Push-button (Normally Open)
* Modeled as a Voltage Controlled Switch (S1) driven by a control pulse (V_S1_ACT)
* Connects VCC to VCAP when activated
S1 VCC VCAP CTRL 0 SW_MODEL

* Control signal for the button press simulation
* Press button at T=0.5s, hold for 0.5s, then release to allow discharge
V_S1_ACT CTRL 0 PULSE(0 5 0.5 1m 1m 0.5 20)

* C1: 470 µF electrolytic capacitor
C1 VCAP 0 470u

* R1: 10 kΩ resistor (Discharge path to Base)
R1 VCAP BASE 10k

* --- Transistor Switch ---
* Q1: 2N2222 NPN transistor
* Connections: Collector=COL, Base=BASE, Emitter=0(GND)
Q1 COL BASE 0 2N2222MOD

* --- Output Load (LED) ---
* R2: 470 Ω resistor
R2 VCC LED_A 470

* D1: Red LED
* Connections: Anode=LED_A, Cathode=COL
D1 LED_A COL DLED

* --- Models ---
* Switch Model: Threshold 2.5V, Low On-Resistance
.model SW_MODEL SW(Vt=2.5 Ron=0.1 Roff=100Meg)

* NPN Transistor Model (Generic 2N2222)
.model 2N2222MOD NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=0.3 RE=0.2)

* LED Model (Red LED approx)
.model DLED D(IS=1u N=2 RS=10 BV=5 IBV=10u)

* --- Analysis Commands ---
* Transient analysis for 10 seconds to observe the long RC discharge (Tau ~ 4.7s)
.tran 10m 10s

* Output voltage of Capacitor, Base, Collector, and LED Anode
.print tran V(VCAP) V(BASE) V(COL) V(LED_A)

.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Reversed Capacitor Polarity: Electrolytic capacitors can explode or fail if connected backwards. Ensure the negative stripe on C1 connects to 0 (GND).
  2. Incorrect Transistor Pinout: Confusing the Collector and Emitter prevents switching. Verify the 2N2222 datasheet; usually, the tab or flat side indicates the pin orientation.
  3. Capacitor Value Too Small: Using a small capacitor (e.g., 100 nF) results in a delay too short for the human eye to perceive. Use at least 100 µF for visible results.

Troubleshooting

  • Symptom: LED never turns ON.
    • Cause: LED installed backwards or transistor broken.
    • Fix: Check D1 orientation (Anode to resistor, Cathode to Collector) and verify Q1 connections.
  • Symptom: LED turns OFF immediately upon releasing the button.
    • Cause: Capacitor is missing, disconnected, or value is too low.
    • Fix: Ensure C1 is firmly connected between VCAP and 0. Try increasing C1 to 1000 µF.
  • Symptom: Transistor gets very hot.
    • Cause: Missing base resistor or short circuit at the output.
    • Fix: Ensure R1 (10 kΩ) is correctly installed between the capacitor and the base to limit base current.

Possible improvements and extensions

  1. Variable Timer: Replace R1 with a 50 kΩ potentiometer in series with a 1 kΩ resistor to allow the user to adjust the delay duration.
  2. Darlington Pair: Replace Q1 with a Darlington transistor (or two NPNs connected as a Darlington pair) to significantly increase input impedance, allowing for much longer delays with the same capacitor value.

More Practical Cases on Prometeo.blog

Find this product and/or books on this topic on Amazon

Go to Amazon

As an Amazon Associate, I earn from qualifying purchases. If you buy through this link, you help keep this project running.

Quick Quiz

Question 1: What is the primary function of the capacitor (C1) in this circuit?




Question 2: Which component acts as the current switch in this off-delay circuit?




Question 3: What happens to the LED immediately after the push-button is released?




Question 4: Which real-world application is mentioned as a use case for this type of circuit?




Question 5: What is the purpose of the resistor R2 (470 Ω) in a typical LED circuit like this?




Question 6: What is the voltage of the power supply (V1) used in this project?




Question 7: Which component works in conjunction with the capacitor to determine the discharge timing?




Question 8: What type of switch is S1 described as in the expected outcome?




Question 9: During the 'Delay Phase', why does the LED eventually turn off?




Question 10: What is the target audience for this specific project?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: DC blocking

DC blocking prototype (Maker Style)

Level: Basic. Verify that a capacitor allows AC signals to pass while blocking DC components.

Objective and use case

You will build a passive circuit connecting a signal source with a DC offset to a load through a series capacitor. The setup demonstrates how the capacitor filters out the direct current (DC) component while allowing the alternating current (AC) signal to reach the load.

Why it is useful:
* Audio Coupling: Essential for connecting amplifier stages where different DC bias voltages exist but the audio signal must pass through unchanged.
* Sensor Conditioning: Removes constant voltage offsets from sensors (like piezoelectric elements) to focus only on dynamic changes.
* Protection: Prevents dangerous DC currents from flowing into sensitive loads like headphones or speakers.

Expected outcome:
* Input Signal: A sine wave oscillating strictly above 0 V (e.g., between +2 V and +4 V).
* Output Signal: The same sine wave centered around 0 V (oscillating between -1 V and +1 V).
* DC Measurement: The input node measures a steady DC voltage (e.g., +3 V), while the output node measures 0 V DC.

Target audience and level:
Students and hobbyists learning about passive filters and AC coupling.

Materials

  • V1: Function Generator, function: provides 1 kHz sine wave (2 Vpp) with +3 V DC offset.
  • C1: 10 µF electrolytic capacitor, function: DC blocking coupling capacitor.
  • R1: 10 kΩ resistor, function: output load to ground.
  • Measurement Tools: Oscilloscope (DC coupling mode) and Multimeter.

Wiring guide

This circuit uses three specific nodes: VIN (source), VOUT (load), and 0 (GND).

  • V1 (Source): Connect the positive terminal to node VIN and the negative/ground terminal to node 0.
  • C1 (Capacitor): Connect the positive terminal (anode) to node VIN and the negative terminal (cathode) to node VOUT.
  • R1 (Resistor): Connect one leg to node VOUT and the other leg to node 0.

Conceptual block diagram

Conceptual block diagram — DC Blocking (High-Pass)
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ INPUT SOURCE ]                 [ PROCESSING ]                   [ OUTPUT LOAD ]

    [ V1: Function Gen ]             [ C1: Capacitor ]                 [ R1: Resistor ]
    ( 1kHz Sine, 2Vpp  ) --(VIN)--> +[     10 µF     ]- --(VOUT)--> [     10 kΩ      ] --> GND
    (   +3 V DC Offset  )      |      ( Electrolytic  )       |
                              |                              |
                              v                              v
                       [ Measurement ]                [ Measurement ]
                       (Scope/Multi)                  (Scope/Multi)
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: DC blocking
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

To validate the circuit, ensure your oscilloscope is set to DC Coupling on the input channel. If set to AC Coupling, the scope itself will block the DC, hiding the effect of the external capacitor.

  1. Configure Source (V1): Set the function generator to a Sine wave, Frequency = 1 kHz, Amplitude = 2 V peak-to-peak, Offset = +3 V.
  2. Measure Input (VIN):
    • Connect the scope probe to VIN.
    • Observation: The signal should oscillate between +2 V and +4 V. The center line is at +3 V.
    • DC Meter: Should read approximately +3 V.
  3. Measure Output (VOUT):
    • Connect the scope probe to VOUT.
    • Observation: The signal should oscillate between -1 V and +1 V. The center line is at 0 V.
    • DC Meter: Should read approximately 0 V.
  4. Verification: Confirm that the shape and amplitude (2 Vpp) of the AC wave remain largely unchanged, but the vertical position has shifted down by 3 volts.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: DC blocking

* --- Components ---

* V1: Function Generator
* Specs: 1 kHz sine wave, 2 Vpp (Amplitude = 1V), +3 V DC offset
* Connection: Positive to VIN, Negative to 0 (GND)
V1 VIN 0 SIN(3 1 1k)

* C1: 10 uF electrolytic capacitor
* Function: DC blocking coupling capacitor
* Connection: Positive (VIN) to Negative (VOUT)
C1 VIN VOUT 10u

* R1: 10 kOhm resistor
* Function: Output load to ground
* Connection: VOUT to 0 (GND)
R1 VOUT 0 10k

* --- Simulation Commands ---
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: DC blocking

* --- Components ---

* V1: Function Generator
* Specs: 1 kHz sine wave, 2 Vpp (Amplitude = 1V), +3 V DC offset
* Connection: Positive to VIN, Negative to 0 (GND)
V1 VIN 0 SIN(3 1 1k)

* C1: 10 uF electrolytic capacitor
* Function: DC blocking coupling capacitor
* Connection: Positive (VIN) to Negative (VOUT)
C1 VIN VOUT 10u

* R1: 10 kOhm resistor
* Function: Output load to ground
* Connection: VOUT to 0 (GND)
R1 VOUT 0 10k

* --- Simulation Commands ---

* Operating point analysis
.op

* Transient analysis
* Frequency is 1kHz (Period = 1ms). Simulate 5ms to see 5 cycles.
.tran 10u 5m

* --- Output Directives ---
* Print input and output voltages for logging
.print tran V(VIN) V(VOUT)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (508 rows)
Index   time            v(vin)          v(vout)
0	0.000000e+00	3.000000e+00	0.000000e+00
1	1.000000e-07	3.000628e+00	6.283179e-04
2	2.000000e-07	3.001257e+00	1.256635e-03
3	4.000000e-07	3.002513e+00	2.513266e-03
4	8.000000e-07	3.005027e+00	5.026506e-03
5	1.600000e-06	3.010053e+00	1.005285e-02
6	3.200000e-06	3.020105e+00	2.010452e-02
7	6.400000e-06	3.040202e+00	4.020026e-02
8	1.280000e-05	3.080338e+00	8.033296e-02
9	2.280000e-05	3.142767e+00	1.427508e-01
10	3.280000e-05	3.204633e+00	2.045991e-01
11	4.280000e-05	3.265691e+00	2.656336e-01
12	5.280000e-05	3.325700e+00	3.256134e-01
13	6.280000e-05	3.384424e+00	3.843020e-01
14	7.280000e-05	3.441631e+00	4.414676e-01
15	8.280000e-05	3.497095e+00	4.968847e-01
16	9.280000e-05	3.550597e+00	5.503345e-01
17	1.028000e-04	3.601927e+00	6.016061e-01
18	1.128000e-04	3.650880e+00	6.504972e-01
19	1.228000e-04	3.697265e+00	6.968148e-01
20	1.328000e-04	3.740898e+00	7.403761e-01
21	1.428000e-04	3.781608e+00	7.810093e-01
22	1.528000e-04	3.819232e+00	8.185538e-01
23	1.628000e-04	3.853624e+00	8.528617e-01
... (484 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: DC blocking

* --- Components ---

* V1: Function Generator
* Specs: 1 kHz sine wave, 2 Vpp (Amplitude = 1V), +3 V DC offset
* Connection: Positive to VIN, Negative to 0 (GND)
V1 VIN 0 SIN(3 1 1k)

* C1: 10 uF electrolytic capacitor
* Function: DC blocking coupling capacitor
* Connection: Positive (VIN) to Negative (VOUT)
C1 VIN VOUT 10u

* R1: 10 kOhm resistor
* Function: Output load to ground
* Connection: VOUT to 0 (GND)
R1 VOUT 0 10k

* --- Simulation Commands ---

* Operating point analysis
.op

* Transient analysis
* Frequency is 1kHz (Period = 1ms). Simulate 5ms to see 5 cycles.
.tran 10u 5m

* --- Output Directives ---
* Print input and output voltages for logging
.print tran V(VIN) V(VOUT)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Using AC Coupling on the Oscilloscope: This is the most frequent error. It makes the input look exactly like the output because the scope blocks the DC internally. Solution: Always verify the scope channel is set to «DC Coupling».
  2. Reversing Capacitor Polarity: Using a polarized electrolytic capacitor backwards can cause it to leak current or fail. Solution: Ensure the positive side of C1 faces the higher DC potential (the source VIN in this case).
  3. Load Resistance (R1) too Low: If R1 is very small, it creates a High-Pass filter with a cutoff frequency above 1 kHz, attenuating the AC signal. Solution: Ensure R1 × C1 is large enough so fcutoff = (1 / (2\pi R C)) is well below the signal frequency.

Troubleshooting

  • Symptom: VOUT shows a DC voltage significantly higher than 0 V.
    • Cause: The capacitor C1 is leaky or damaged (acting like a resistor).
    • Fix: Replace C1 with a new capacitor.
  • Symptom: No signal at VOUT (0 V AC and 0 V DC).
    • Cause: Open circuit connection or defective breadboard track.
    • Fix: Check continuity between C1 cathode and R1.
  • Symptom: The AC signal at VOUT is much smaller than at VIN.
    • Cause: The source frequency is too low for the selected C1/R1 combination (High-Pass filtering effect).
    • Fix: Increase the frequency of V1 or increase the value of C1.

Possible improvements and extensions

  1. Frequency Sweep: Lower the frequency of V1 from 1 kHz down to 1 Hz to observe how the capacitor eventually blocks the AC signal as well (High-Pass filter demonstration).
  2. Variable Load: Replace R1 with a potentiometer to see how changing load impedance affects the low-frequency cutoff point.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the capacitor in the described circuit?




Question 2: Which component is typically used as the output load to ground in this type of circuit?




Question 3: Why is this circuit essential for 'Audio Coupling'?




Question 4: If the input signal oscillates between +2 V and +4 V, what is the average DC offset at the input?




Question 5: What is the expected behavior of the output signal compared to the input signal?




Question 6: Based on the context, what type of capacitor is likely used for values like 10 µF?




Question 7: Why is this circuit useful for sensor conditioning?




Question 8: What is the expected DC measurement at the output node after the capacitor?




Question 9: In the described setup, which node connects directly to the signal source?




Question 10: What protection benefit does this circuit offer for sensitive loads like headphones?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: Basic rectifier filtering

Basic rectifier filtering prototype (Maker Style)

Level: Basic. Demonstrate how a capacitor smoothes ripple in a half-wave rectified signal.

Objective and use case

In this practical case, you will build a half-wave rectifier circuit and observe the effect of adding a filter capacitor in parallel with the load.
* Why it is useful:
* Essential for converting Alternating Current (AC) from the mains into Direct Current (DC) for powering electronics.
* Used in simple battery chargers.
* Fundamental concept for audio signal demodulation (envelope detectors).
* Demonstrates energy storage properties of capacitors in power supplies.
* Expected outcome:
* Input: A pure AC sine wave (swinging positive and negative).
* Step 1 Output: A pulsing positive-only signal (half-wave rectification).
* Step 2 Output: A steady DC voltage with slight variation (ripple) after connecting the capacitor.
* Target audience and level: Students and hobbyists understanding basic AC/DC conversion.

Materials

  • V1: 10 V (peak), 50 Hz sine wave source, function: AC power input.
  • D1: 1N4007 diode, function: rectifies AC to pulsating DC.
  • R1: 1 kΩ resistor, function: acts as the electrical load.
  • C1: 100 µF electrolytic capacitor, function: filters voltage ripple (stores energy).
  • GND: Ground reference (0 V).

Wiring guide

Construct the circuit following these node connections:

  • V1 (Source): Connect the positive terminal to node VAC and the negative terminal to node 0 (GND).
  • D1 (Rectifier): Connect the Anode to node VAC and the Cathode to node VOUT.
  • R1 (Load): Connect between node VOUT and node 0 (GND).
  • C1 (Filter): Connect the positive terminal to node VOUT and the negative terminal to node 0 (GND). Note: Initially leave C1 disconnected to observe the unfiltered signal, then connect it.

Conceptual block diagram

Conceptual block diagram — LM7805 Half-Wave Rectifier w/ Filter
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ AC SOURCE ]            [ RECTIFICATION ]             [ OUTPUT STAGE ]

                                                          +--> [ C1 Filter ] --> GND
                                                          |    (100 uF)
    [ V1 Source ] --(VAC)--> [ D1 Diode ] --(VOUT Node)-->+
    (10 V, 50Hz)              (1N4007)                     |
                                                          +--> [ R1 Load ]   --> GND
                                                               (1 kOhm)
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Basic rectifier filtering
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

Perform the following steps using an oscilloscope or a multimeter:

  1. Input Verification:
    • Connect the probe to VAC.
    • Verify a sine wave oscillating between +10 V and -10 V.
  2. Unfiltered Rectification (C1 Disconnected):
    • Remove C1 temporarily.
    • Measure VOUT. You should see only the positive half-cycles of the sine wave (approx. 0 V to 9.3 V due to diode drop). The voltage drops to zero between peaks.
  3. Filtered Rectification (C1 Connected):
    • Connect C1 across R1.
    • Measure VOUT. The signal should now be a DC voltage near the peak value (approx. 9 V) that does not drop to zero.
    • Vripple Measurement: Set the oscilloscope to AC coupling to zoom in on the small voltage fluctuation («sawtooth» shape) on top of the DC line.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Basic rectifier filtering

* --- Components ---

* V1: 10 V (peak), 50 Hz sine wave source
* Connected: Positive -> VAC, Negative -> 0 (GND)
V1 VAC 0 SIN(0 10 50)

* D1: 1N4007 diode (Rectifier)
* Connected: Anode -> VAC, Cathode -> VOUT
D1 VAC VOUT 1N4007

* R1: 1 kΩ resistor (Load)
* Connected: Between VOUT and 0 (GND)
R1 VOUT 0 1k

* C1: 100 µF electrolytic capacitor (Filter)
* Connected: Positive -> VOUT, Negative -> 0 (GND)
* Note: Included to demonstrate the filtering effect described in the case.
C1 VOUT 0 100u
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

* Basic rectifier filtering

* --- Components ---

* V1: 10 V (peak), 50 Hz sine wave source
* Connected: Positive -> VAC, Negative -> 0 (GND)
V1 VAC 0 SIN(0 10 50)

* D1: 1N4007 diode (Rectifier)
* Connected: Anode -> VAC, Cathode -> VOUT
D1 VAC VOUT 1N4007

* R1: 1 kΩ resistor (Load)
* Connected: Between VOUT and 0 (GND)
R1 VOUT 0 1k

* C1: 100 µF electrolytic capacitor (Filter)
* Connected: Positive -> VOUT, Negative -> 0 (GND)
* Note: Included to demonstrate the filtering effect described in the case.
C1 VOUT 0 100u

* --- Models ---

* Standard silicon rectifier diode model approximation for 1N4007
.model 1N4007 D(IS=7.03n RS=0.04 N=1.85 CJO=10p VJ=1 M=0.5 BV=1000 IBV=10u TT=5u)

* --- Analysis Directives ---

* Transient analysis: 100ms duration (5 cycles of 50Hz) with 0.1ms step
.tran 0.1ms 100ms

* Operating point analysis
.op

* Print directives for simulation logging
.print tran V(VAC) V(VOUT)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (1017 rows)
Index   time            v(vac)          v(vout)
0	0.000000e+00	0.000000e+00	-2.77024e-22
1	1.000000e-06	3.141593e-03	3.430255e-10
2	2.000000e-06	6.283185e-03	6.932562e-10
3	4.000000e-06	1.256637e-02	1.411758e-09
4	8.000000e-06	2.513271e-02	2.956960e-09
5	1.600000e-05	5.026527e-02	6.646271e-09
6	3.200000e-05	1.005293e-01	1.882015e-08
7	5.304087e-05	1.666251e-01	6.310202e-08
8	7.565486e-05	2.376544e-01	2.484107e-07
9	1.009625e-04	3.171298e-01	1.270798e-06
10	1.280850e-04	4.022822e-01	7.576310e-06
11	1.570209e-04	4.930958e-01	5.140208e-05
12	1.876236e-04	5.890955e-01	3.869871e-04
13	2.197798e-04	6.899101e-01	3.065854e-03
14	2.535671e-04	7.957622e-01	2.015809e-02
15	2.900907e-04	9.100857e-01	7.787813e-02
16	3.269176e-04	1.025237e+00	1.740794e-01
17	3.659101e-04	1.147010e+00	2.922342e-01
18	4.156771e-04	1.302180e+00	4.470469e-01
19	4.731074e-04	1.480844e+00	6.257990e-01
20	5.731074e-04	1.790758e+00	9.360689e-01
21	6.731074e-04	2.098905e+00	1.244455e+00
22	7.731074e-04	2.404980e+00	1.550935e+00
23	8.731074e-04	2.708681e+00	1.855020e+00
... (993 more rows) ...


Reference SPICE netlist (ngspice)

* Basic rectifier filtering

* --- Components ---

* V1: 10 V (peak), 50 Hz sine wave source
* Connected: Positive -> VAC, Negative -> 0 (GND)
V1 VAC 0 SIN(0 10 50)

* D1: 1N4007 diode (Rectifier)
* Connected: Anode -> VAC, Cathode -> VOUT
D1 VAC VOUT 1N4007

* R1: 1 kΩ resistor (Load)
* Connected: Between VOUT and 0 (GND)
R1 VOUT 0 1k

* C1: 100 µF electrolytic capacitor (Filter)
* Connected: Positive -> VOUT, Negative -> 0 (GND)
* Note: Included to demonstrate the filtering effect described in the case.
C1 VOUT 0 100u

* --- Models ---

* Standard silicon rectifier diode model approximation for 1N4007
.model 1N4007 D(IS=7.03n RS=0.04 N=1.85 CJO=10p VJ=1 M=0.5 BV=1000 IBV=10u TT=5u)

* --- Analysis Directives ---

* Transient analysis: 100ms duration (5 cycles of 50Hz) with 0.1ms step
.tran 0.1ms 100ms

* Operating point analysis
.op

* Print directives for simulation logging
.print tran V(VAC) V(VOUT)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Reversing Capacitor Polarity:
    • Error: Connecting the negative leg of an electrolytic capacitor to the positive voltage node.
    • Solution: Always ensure the stripe (negative side) of the capacitor connects to Ground (0). Reverse polarity can cause the capacitor to explode.
  2. Load Resistance Too Low:
    • Error: Using a very small resistor (e.g., 10 Ω) with a small capacitor.
    • Solution: If the load draws too much current, the capacitor discharges too quickly, causing massive ripple. Increase C1 or R1.
  3. Ignoring Diode Voltage Drop:
    • Error: Expecting exactly 10 V DC from a 10 V AC peak source.
    • Solution: Account for the ~0.7 V drop across the silicon diode. Expect around 9.3 V peak.

Troubleshooting

  • Symptom: Output is identical to Input (AC sine wave).
    • Cause: Diode is shorted internally.
    • Fix: Replace D1.
  • Symptom: Output is 0 V.
    • Cause: Diode is open or connected backward (blocking positive cycle).
    • Fix: Check diode orientation (anode to source).
  • Symptom: Ripple is very high (voltage drops deeply between peaks).
    • Cause: Capacitor value is too low for the frequency or load.
    • Fix: Increase C1 to 470 µF or 1000 µF.

Possible improvements and extensions

  1. Full-Wave Rectification: Replace the single diode with a bridge rectifier (4 diodes) to utilize the negative half-cycle, doubling the ripple frequency and improving efficiency.
  2. Voltage Regulator: Add a Zener diode or a linear regulator (like an LM7805) after the capacitor to create a fixed, stable DC output regardless of ripple.

More Practical Cases on Prometeo.blog

Find this product and/or books on this topic on Amazon

Go to Amazon

As an Amazon Associate, I earn from qualifying purchases. If you buy through this link, you help keep this project running.

Quick Quiz

Question 1: What is the primary function of the 1N4007 diode (D1) in this circuit?




Question 2: What is the role of the capacitor C1 in the circuit?




Question 3: Before adding the capacitor, what does the output signal look like after passing through the diode?




Question 4: Which component acts as the electrical load in this specific circuit?




Question 5: What is the expected output after connecting the capacitor to the circuit?




Question 6: To which node should the Anode of the diode D1 be connected in a standard half-wave rectifier configuration?




Question 7: What is the frequency of the AC sine wave source (V1) specified for this experiment?




Question 8: Why is this circuit useful for powering electronics?




Question 9: Where should the negative terminal of the capacitor C1 be connected?




Question 10: Besides power supplies, what is another application mentioned for this fundamental concept?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:


Practical case: Visual Charge and Discharge with LED

Visual Charge and Discharge with LED prototype (Maker Style)

Level: Basic – Observe energy storage in an electrolytic capacitor via LED fading.

Objective and use case

You will build a simple circuit where a capacitor acts as a temporary energy reservoir, keeping an LED illuminated briefly after the power source is disconnected.

  • Why it is useful:

    • Demonstrates how capacitors store and release electrical energy.
    • Simulates the «smoothing» effect used in power supply adapters to maintain steady voltage.
    • Visualizes the RC time constant (the relationship between resistance, capacitance, and time).
    • Introduces the concept of «hold-up time» in power failures.
  • Expected outcome:

    • Switch ON: The LED lights up immediately.
    • Switch OFF: The LED does not turn off instantly; instead, it slowly fades out over several seconds.
    • Visual: A smooth transition from bright light to darkness.
    • Audience: Students and hobbyists interested in basic component behavior.

Materials

  • V1: 9 V DC battery or power supply, function: main energy source.
  • S1: SPST toggle switch or push-button, function: controls the connection to the power source.
  • C1: 2200 µF electrolytic capacitor (16 V or higher), function: energy storage reservoir.
  • R1: 470 Ω resistor, function: LED current limiting and discharge timing control.
  • D1: Red LED, function: visual indicator of current flow and stored charge.

Wiring guide

Use the following explicit node connections to build the circuit. The standard ground reference is node 0.

  • Power and Switch:

    • Connect the Positive terminal of V1 to node VCC.
    • Connect the Negative terminal of V1 to node 0 (GND).
    • Connect one side of switch S1 to node VCC.
    • Connect the other side of switch S1 to node V_CAP.
  • Capacitor (The Tank):

    • Connect the Positive (long leg) of C1 to node V_CAP.
    • Connect the Negative (short leg/stripe) of C1 to node 0.
  • LED and Resistor (The Load):

    • Connect resistor R1 between node V_CAP and node V_LED.
    • Connect the Anode (long leg) of D1 to node V_LED.
    • Connect the Cathode (short leg/flat spot) of D1 to node 0.

Conceptual block diagram

Conceptual block diagram — RC Charge/Discharge Circuit
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Visual Charge and Discharge with LED

      [ INPUT / CONTROL ]               [ STORAGE / BUFFER ]               [ OUTPUT / LOAD ]

                                            (Node V_CAP)
    [ 9 V Battery ] --(+)--> [ Switch S1 ] -------+-------> [ Resistor R1 ] --> [ LED D1 ] --> GND
                                                 |
                                                 |
                                                 v
                                          [ Capacitor C1 ]
                                          (   2200 uF    )
                                                 |
                                                GND
Schematic (ASCII)

Electrical diagram

Electrical diagram for case: Visual Charge and Discharge with LED
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

  1. Initial State: Ensure S1 is Open (Off). The LED should be dark.
  2. Charge Phase: Close S1. Observe that the LED lights up instantly. The capacitor C1 charges to approximately 9 V almost immediately.
  3. Discharge Phase: Open S1.
    • Observe that the LED remains lit but begins to dim.
    • Use a stopwatch to measure the time from opening the switch until the LED is completely dark.
  4. Repeat: Swap C1 for a smaller value (e.g., 100 µF) and observe how the fade time becomes much shorter (almost instant).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Visual Charge and Discharge with LED

* --- Power Supply (V1) ---
* 9V DC Battery connected to VCC and GND (0)
V1 VCC 0 DC 9

* --- Switch (S1) ---
* Modeled as a Voltage-Controlled Switch to simulate a physical push-button.
* Connections: VCC to V_CAP
* The switch is controlled by the voltage at node 'CTRL'.
S1 VCC V_CAP CTRL 0 SW_PUSH

* Switch Control Source (Simulates User Interaction)
* Simulates pressing the button at T=0.1s, holding for 1s, then releasing.
* PULSE(V1 V2 TD TR TF PW PER)
V_USER_S1 CTRL 0 PULSE(0 5 0.1 1m 1m 1 5)

* Switch Model Definition
* Ron=1 ohm represents wiring/contact resistance.
.model SW_PUSH SW(Vt=2.5 Ron=1 Roff=100Meg)
* ... (truncated in public view) ...

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* Practical case: Visual Charge and Discharge with LED

* --- Power Supply (V1) ---
* 9V DC Battery connected to VCC and GND (0)
V1 VCC 0 DC 9

* --- Switch (S1) ---
* Modeled as a Voltage-Controlled Switch to simulate a physical push-button.
* Connections: VCC to V_CAP
* The switch is controlled by the voltage at node 'CTRL'.
S1 VCC V_CAP CTRL 0 SW_PUSH

* Switch Control Source (Simulates User Interaction)
* Simulates pressing the button at T=0.1s, holding for 1s, then releasing.
* PULSE(V1 V2 TD TR TF PW PER)
V_USER_S1 CTRL 0 PULSE(0 5 0.1 1m 1m 1 5)

* Switch Model Definition
* Ron=1 ohm represents wiring/contact resistance.
.model SW_PUSH SW(Vt=2.5 Ron=1 Roff=100Meg)

* --- Capacitor (C1) ---
* 2200uF Energy Storage
* Connections: V_CAP to GND (0)
C1 V_CAP 0 2200u

* --- Resistor (R1) ---
* 470 Ohm Current Limiting Resistor
* Connections: V_CAP to V_LED
R1 V_CAP V_LED 470

* --- LED (D1) ---
* Red LED Indicator
* Connections: Anode (V_LED) to Cathode (0)
D1 V_LED 0 D_LED_RED

* LED Model Definition
* Generic Red LED parameters
.model D_LED_RED D(IS=1e-14 N=2 RS=10 BV=5 IBV=10u)

* --- Analysis Commands ---
* The discharge time constant (Tau) = R * C = 470 * 2200e-6 approx 1.03 seconds.
* Simulation runs for 3 seconds to visualize the charge and discharge cycle.
.tran 10m 3s

* --- Output Directives ---
* Prints the capacitor voltage, LED anode voltage, and switch control signal.
.print tran V(V_CAP) V(V_LED) V(CTRL)

.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (352 rows)
Index   time            v(v_cap)        v(v_led)        v(ctrl)
0	0.000000e+00	8.234122e-01	8.233738e-01	0.000000e+00
1	1.000000e-04	8.234122e-01	8.233738e-01	0.000000e+00
2	2.000000e-04	8.234122e-01	8.233738e-01	0.000000e+00
3	4.000000e-04	8.234122e-01	8.233738e-01	0.000000e+00
4	8.000000e-04	8.234122e-01	8.233738e-01	0.000000e+00
5	1.600000e-03	8.234122e-01	8.233738e-01	0.000000e+00
6	3.200000e-03	8.234122e-01	8.233738e-01	0.000000e+00
7	6.400000e-03	8.234122e-01	8.233738e-01	0.000000e+00
8	1.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
9	2.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
10	3.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
11	4.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
12	5.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
13	6.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
14	7.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
15	8.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
16	9.280000e-02	8.234122e-01	8.233738e-01	0.000000e+00
17	1.000000e-01	8.234122e-01	8.233738e-01	0.000000e+00
18	1.001000e-01	8.234122e-01	8.233738e-01	5.000000e-01
19	1.002600e-01	8.234122e-01	8.233738e-01	1.300000e+00
20	1.003075e-01	8.234122e-01	8.233738e-01	1.537500e+00
21	1.003906e-01	8.234122e-01	8.233738e-01	1.953125e+00
22	1.004136e-01	8.234122e-01	8.233738e-01	2.068164e+00
23	1.004539e-01	8.234122e-01	8.233738e-01	2.269482e+00
... (328 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Visual Charge and Discharge with LED

* --- Power Supply (V1) ---
* 9V DC Battery connected to VCC and GND (0)
V1 VCC 0 DC 9

* --- Switch (S1) ---
* Modeled as a Voltage-Controlled Switch to simulate a physical push-button.
* Connections: VCC to V_CAP
* The switch is controlled by the voltage at node 'CTRL'.
S1 VCC V_CAP CTRL 0 SW_PUSH

* Switch Control Source (Simulates User Interaction)
* Simulates pressing the button at T=0.1s, holding for 1s, then releasing.
* PULSE(V1 V2 TD TR TF PW PER)
V_USER_S1 CTRL 0 PULSE(0 5 0.1 1m 1m 1 5)

* Switch Model Definition
* Ron=1 ohm represents wiring/contact resistance.
.model SW_PUSH SW(Vt=2.5 Ron=1 Roff=100Meg)

* --- Capacitor (C1) ---
* 2200uF Energy Storage
* Connections: V_CAP to GND (0)
C1 V_CAP 0 2200u

* --- Resistor (R1) ---
* 470 Ohm Current Limiting Resistor
* Connections: V_CAP to V_LED
R1 V_CAP V_LED 470

* --- LED (D1) ---
* Red LED Indicator
* Connections: Anode (V_LED) to Cathode (0)
D1 V_LED 0 D_LED_RED

* LED Model Definition
* Generic Red LED parameters
.model D_LED_RED D(IS=1e-14 N=2 RS=10 BV=5 IBV=10u)

* --- Analysis Commands ---
* The discharge time constant (Tau) = R * C = 470 * 2200e-6 approx 1.03 seconds.
* Simulation runs for 3 seconds to visualize the charge and discharge cycle.
.tran 10m 3s

* --- Output Directives ---
* Prints the capacitor voltage, LED anode voltage, and switch control signal.
.print tran V(V_CAP) V(V_LED) V(CTRL)

.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Reversed Capacitor Polarity: Electrolytic capacitors are polarized. Connecting the negative leg to positive voltage can cause the component to overheat or pop. Solution: Always check the stripe on the side of the capacitor; it marks the negative pin.
  2. Omitting the Resistor: Connecting the LED directly to the 9 V source (or charged capacitor) without R1 will burn out the LED instantly. Solution: Ensure R1 is in series with D1.
  3. Using a very small Capacitor: If C1 is too small (e.g., 100 nF), the discharge will happen so fast the human eye cannot see the fade. Solution: Use values ≥ 1000 µF for visual tests.

Troubleshooting

  • LED never lights up:
    • Check if D1 is inserted backward (Anode/Cathode swapped).
    • Verify S1 is actually closing the circuit.
    • Check battery voltage.
  • LED turns off instantly (no fade):
    • C1 might be disconnected or open-circuit.
    • C1 value is too low.
    • R1 value is too high, making the LED too dim to see the tail end of the fade.
  • Capacitor gets hot:
    • Immediately disconnect power! The polarity of C1 is likely reversed.

Possible improvements and extensions

  1. Variable Timing: Replace R1 with a 1 kΩ potentiometer in series with a 100 Ω fixed resistor. Adjusting the pot will change the discharge time and LED brightness.
  2. Dual Switch Logic: Use a SPDT (Single Pole Double Throw) switch. Connect Node VCC to Position 1, Node 0 to Position 2, and the Common pin to the Capacitor/Resistor network. This allows you to actively «dump» the energy to ground or let it fade naturally.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the capacitor in this circuit?




Question 2: What visual effect is expected when the switch is turned OFF?




Question 3: Which component is responsible for limiting the current to the LED?




Question 4: What is the recommended value for the capacitor C1 in this experiment?




Question 5: Why is this circuit useful for understanding power supplies?




Question 6: What happens to the LED immediately after the switch is turned ON?




Question 7: What concept describes the relationship between resistance, capacitance, and time?




Question 8: What is the function of the component labeled V1?




Question 9: What real-world concept related to power failures does this circuit introduce?




Question 10: Who is the intended audience for this specific circuit experiment?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Modulated light audio receiver

Modulated light audio receiver prototype (Maker Style)

Level: Medium – Build a receiver capable of demodulating an audio signal transmitted via an LED light beam using a photodiode.

Objective and use case

In this practical case, you will build an analog optical receiver using a high-speed photodiode configured in photoconductive mode, followed by a Transimpedance Amplifier (TIA) and an audio power amplifier. This circuit detects changes in light intensity modulated by an audio source and converts them back into electrical signals to drive a speaker.

Why it is useful:
* Optical Wireless Communication (OWC): Demonstrates the fundamental physics behind Li-Fi and infrared remote controls.
* Galvanic Isolation: Allows audio transmission between devices without a physical ground connection, preventing ground loops.
* Security: Unlike radio frequency (RF), optical signals are confined to the room and cannot pass through opaque walls.
* Interference Immunity: Immune to electromagnetic interference (EMI) that typically affects copper wire transmission.

Expected outcome:
* Signal Output: A measurable voltage waveform at the TIA output (V_PRE) that mirrors the transmitted audio waveform.
* Audio Output: Clear sound reproduction through the loudspeaker (LS1) when the photodiode receives modulated light.
* Voltage Levels: The TIA output should ride on a DC bias (approx. VCC/2) with an AC signal swing depending on light intensity.
* Volume Control: Adjustment of the audio level via the potentiometer (R_VOL).

Target audience: Electronics students and hobbyists interested in analog signal conditioning.

Materials

  • V1: 9 V DC voltage source, function: Main circuit power supply.
  • D1: BPW34 Photodiode, function: Optical sensor (light to current converter).
  • U1: TL071 Operational Amplifier, function: Transimpedance Amplifier (TIA).
  • U2: LM386N-1 Audio Amplifier IC, function: Power amplification for speaker.
  • R_F: 100 kΩ resistor, function: TIA feedback resistor (sets gain).
  • R_B1: 10 kΩ resistor, function: Voltage divider top for VCC/2 bias.
  • R_B2: 10 kΩ resistor, function: Voltage divider bottom for VCC/2 bias.
  • R_VOL: 10 kΩ potentiometer, function: Audio volume control.
  • C_DEC: 100 nF ceramic capacitor, function: Power supply decoupling.
  • C_BIAS: 10 µF electrolytic capacitor, function: Stabilize VCC/2 bias point.
  • C_COUP: 4.7 µF electrolytic capacitor, function: DC blocking between TIA and Audio Amp.
  • C_OUT: 220 µF electrolytic capacitor, function: Output coupling for speaker.
  • C_GAIN: 10 µF electrolytic capacitor, function: LM386 gain setting (Pins 1-8).
  • LS1: 8 Ω / 0.5W Speaker, function: Audio transducer.

Wiring guide

This guide defines the connections using specific SPICE node names: VCC, 0 (GND), V_BIAS, N_INV (Inverting input), V_PRE (Pre-amp out), V_WIPER (Potentiometer out), and V_SPK (Amp out).

Power and Bias:
* V1: Positive terminal to VCC, Negative terminal to 0.
* R_B1: Connects between VCC and V_BIAS.
* R_B2: Connects between V_BIAS and 0.
* C_BIAS: Positive lead to V_BIAS, Negative lead to 0.
* C_DEC: Connects between VCC and 0 (near U1).

Transimpedance Amplifier (Stage 1):
* U1 (Op-Amp): V+ pin to VCC, V- pin to 0. Non-inverting input (+) to V_BIAS. Inverting input (-) to N_INV. Output pin to V_PRE.
* D1 (Photodiode): Cathode to VCC, Anode to N_INV (Reverse biased).
* R_F: Connects between N_INV and V_PRE.

Signal Coupling:
* C_COUP: Positive lead to V_PRE, Negative lead to NODE_POT_TOP.
* R_VOL: Top terminal to NODE_POT_TOP, Bottom terminal to 0, Wiper to V_WIPER.

Power Amplifier (Stage 2):
* U2 (LM386): Vs (Pin 6) to VCC, GND (Pin 4) to 0. Non-inverting Input (Pin 3) to V_WIPER. Inverting Input (Pin 2) to 0.
* C_GAIN: Connects between Pin 1 and Pin 8 of U2 (Positive to Pin 1).
* C_OUT: Positive lead to U2 Output (Pin 5), Negative lead to V_SPK.
* LS1: Connects between V_SPK and 0.

Conceptual block diagram

Conceptual block diagram — TL071 Optical Audio Receiver
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Modulated light audio receiver

      [ INPUT / SENSOR ]               [ STAGE 1: TIA PRE-AMP ]                  [ INTERSTAGE ]                [ STAGE 2: POWER AMP ]              [ OUTPUT ]

                                     +-----------[ R_F: 100k ]-----------+
                                     |           (Feedback)              |
                                     v                                   |
(Light) ~~~> [ D1: BPW34 ] --(I)--> [ (-) N_INV      U1: TL071      OUT ] --(V_PRE)--> [ C_COUP ] --> [ R_VOL: 10k ] --(V_WIPER)-->+
             (Photodiode)           |                                    |             (4.7uF)        (Volume Pot)                 |
                                    | (+) V_BIAS                         |                                                         |
                                    +----------------^-------------------+                                                         |
                                                     |                                                                             |
      [ POWER & BIAS ]                               |                                                                             v
                                                     |                                                                     [ IN+  U2: LM386  OUT ] --(V_SPK)--> [ C_OUT ] --> [ LS1: Speaker ]
    [ V1: 9 V DC Source ] --(VCC)--> (Powers U1, U2)  |                                                                     |                 |                (220uF)        (8 Ohm)
             |                                       |                                                                     |  Gain Pins 1-8  |                                  |
             +---> [ Bias Divider ] --(VCC/2 Ref)----+                                                                     +--------+--------+                                 GND
                   (R_B1, R_B2,                                                                                                     |
                    C_BIAS)                                                                                                    [ C_GAIN ]
                                                                                                                                (10uF)
Schematic (ASCII)

Electrical diagram

Electrical diagram for modulated light audio receiver
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

  1. Bias Point Check: Use a multimeter to measure the voltage at node V_BIAS. It should be approximately 4.5 V (half of VCC). If not, check R_B1 and R_B2.
  2. Ambient Light Level: Measure the DC voltage at V_PRE without any modulated signal (just ambient light). It should be slightly lower than V_BIAS depending on the ambient brightness hitting D1.
  3. Signal Acquisition:
    • Point a modulated light source (e.g., an LED connected to an audio output or a signal generator) at D1.
    • Use an oscilloscope at V_PRE. You should see an AC waveform superimposed on the DC level.
    • Measure the Vpp (Peak-to-Peak Voltage). It should be in the range of 100 mV to 1 V depending on the distance and light intensity.
  4. Audio Test: Turn R_VOL up slowly. You should hear the transmitted audio clearly from LS1.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Modulated light audio receiver

* --- Component Models ---
* Generic Photodiode Model
.model D_BPW34 D(Is=1n Rs=5 Cjo=10p)

* --- Subcircuits ---

* TL071 Operational Amplifier Macro Model
* Pinout: 1=NonInv 2=Inv 3=V+ 4=V- 5=Out
.SUBCKT TL071 P_NI P_INV P_VCC P_VEE P_OUT
  * Input Impedance
  Rin P_NI P_INV 1T
  * Output Stage (Behavioral with Rail Limiting)
  * Models high open-loop gain and saturation at Rails +/- 1.5V
  B1 P_OUT 0 V=V(P_VEE) + 1.5 + (V(P_VCC)-V(P_VEE)-3) * (1 / (1 + exp(-100000 * (V(P_NI)-V(P_INV)))))
.ENDS TL071

* LM386 Audio Amplifier Macro Model
* Pinout: 1=Gain 2=Inv 3=NonInv 4=GND 5=Out 6=Vs 8=Gain
* ... (truncated in public view) ...

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* Practical case: Modulated light audio receiver

* --- Component Models ---
* Generic Photodiode Model
.model D_BPW34 D(Is=1n Rs=5 Cjo=10p)

* --- Subcircuits ---

* TL071 Operational Amplifier Macro Model
* Pinout: 1=NonInv 2=Inv 3=V+ 4=V- 5=Out
.SUBCKT TL071 P_NI P_INV P_VCC P_VEE P_OUT
  * Input Impedance
  Rin P_NI P_INV 1T
  * Output Stage (Behavioral with Rail Limiting)
  * Models high open-loop gain and saturation at Rails +/- 1.5V
  B1 P_OUT 0 V=V(P_VEE) + 1.5 + (V(P_VCC)-V(P_VEE)-3) * (1 / (1 + exp(-100000 * (V(P_NI)-V(P_INV)))))
.ENDS TL071

* LM386 Audio Amplifier Macro Model
* Pinout: 1=Gain 2=Inv 3=NonInv 4=GND 5=Out 6=Vs 8=Gain
.SUBCKT LM386 P_G1 P_INV P_NI P_GND P_OUT P_VS P_G8
  * Internal Gain Resistor (1.35k) connecting Pins 1 and 8
  R_GAIN_INT P_G1 P_G8 1.35k
  * High resistance to GND to prevent floating node errors for the Gain capacitor
  R_C1 P_G1 0 100Meg
  R_C8 P_G8 0 100Meg
  
  * Audio Amplifier Behavioral Source
  * Self-biasing output to Vs/2
  * Fixed Gain approx 200 (Assuming C_GAIN is present externally)
  B_OUT P_OUT P_GND V=V(P_VS)/2 + 200*(V(P_NI)-V(P_INV))
.ENDS LM386

* --- Main Circuit ---

* Power Supply (9V)
V1 VCC 0 DC 9

* Power Supply Decoupling
C_DEC VCC 0 100n

* Bias Voltage Generator (VCC/2)
R_B1 VCC V_BIAS 10k
R_B2 V_BIAS 0 10k
C_BIAS V_BIAS 0 10u

* --- Stage 1: Transimpedance Amplifier (TIA) ---
* U1 TL071 Op-Amp
* Connections: NI=V_BIAS, INV=N_INV, V+=VCC, V-=0, OUT=V_PRE
XU1 V_BIAS N_INV VCC 0 V_PRE TL071

* Photodiode Sensor (Reverse Biased)
* Cathode to VCC, Anode to N_INV
D1 N_INV VCC D_BPW34

* Optical Signal Simulation
* Current source representing modulated light (1kHz square wave)
* Connected parallel to photodiode (Anode to Cathode current flow)
I_LIGHT N_INV VCC PULSE(0 2u 0 1u 1u 500u 1000u)

* Feedback Resistor
R_F N_INV V_PRE 100k

* --- Signal Coupling ---
* DC Blocking Capacitor
C_COUP V_PRE NODE_POT_TOP 4.7u

* Volume Potentiometer (10k)
* Modeled as voltage divider. Wiper set to 20% to manage gain.
* Top Resistor (8k)
R_VOL_TOP NODE_POT_TOP V_WIPER 8k
* Bottom Resistor (2k)
R_VOL_BOT V_WIPER 0 2k

* --- Stage 2: Power Amplifier ---
* U2 LM386 Audio Amp
* Connections: 1=GAIN_P, 2=0, 3=V_WIPER, 4=0, 5=V_AMP_OUT, 6=VCC, 8=GAIN_N
XU2 GAIN_P 0 V_WIPER 0 V_AMP_OUT VCC GAIN_N LM386

* Gain Setting Capacitor (Pins 1-8)
C_GAIN GAIN_P GAIN_N 10u

* Output Coupling Capacitor
C_OUT V_AMP_OUT V_SPK 220u

* Speaker Load (8 Ohm)
LS1 V_SPK 0 8

* --- Simulation Directives ---
* Transient analysis for 5ms to see 5 cycles of 1kHz audio
.tran 10u 5ms

* Output data for plotting
.print tran V(V_PRE) V(V_WIPER) V(V_SPK)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Show raw data table (623 rows)
Index   time            v(v_pre)        v(v_wiper)      v(v_spk)
0	0.000000e+00	4.499900e+00	0.000000e+00	0.000000e+00
1	1.000000e-08	4.501899e+00	3.998838e-04	7.997676e-02
2	1.083984e-08	4.502067e+00	4.334770e-04	8.669540e-02
3	1.251953e-08	4.502403e+00	5.006638e-04	1.001328e-01
4	1.587889e-08	4.503075e+00	6.350376e-04	1.270075e-01
5	2.259763e-08	4.504418e+00	9.037850e-04	1.807570e-01
6	3.603509e-08	4.507106e+00	1.441280e-03	2.882560e-01
7	6.291003e-08	4.512481e+00	2.516269e-03	5.032538e-01
8	1.166599e-07	4.523231e+00	4.666245e-03	9.332491e-01
9	2.241596e-07	4.544731e+00	8.966191e-03	1.793238e+00
10	4.391591e-07	4.587730e+00	1.756605e-02	3.513210e+00
11	8.691581e-07	4.673729e+00	3.476566e-02	6.953131e+00
12	1.000000e-06	4.699898e+00	3.999919e-02	7.999838e+00
13	1.086000e-06	4.699898e+00	3.999923e-02	7.999847e+00
14	1.257999e-06	4.699898e+00	3.999909e-02	7.999818e+00
15	1.601999e-06	4.699898e+00	3.999879e-02	7.999759e+00
16	2.289997e-06	4.699898e+00	3.999821e-02	7.999642e+00
17	3.665994e-06	4.699898e+00	3.999704e-02	7.999408e+00
18	6.417987e-06	4.699898e+00	3.999470e-02	7.998939e+00
19	1.192197e-05	4.699898e+00	3.999001e-02	7.998002e+00
20	2.192197e-05	4.699898e+00	3.998151e-02	7.996300e+00
21	3.192197e-05	4.699898e+00	3.997300e-02	7.994598e+00
22	4.192197e-05	4.699898e+00	3.996450e-02	7.992895e+00
23	5.192197e-05	4.699898e+00	3.995599e-02	7.991193e+00
... (599 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Modulated light audio receiver

* --- Component Models ---
* Generic Photodiode Model
.model D_BPW34 D(Is=1n Rs=5 Cjo=10p)

* --- Subcircuits ---

* TL071 Operational Amplifier Macro Model
* Pinout: 1=NonInv 2=Inv 3=V+ 4=V- 5=Out
.SUBCKT TL071 P_NI P_INV P_VCC P_VEE P_OUT
  * Input Impedance
  Rin P_NI P_INV 1T
  * Output Stage (Behavioral with Rail Limiting)
  * Models high open-loop gain and saturation at Rails +/- 1.5V
  B1 P_OUT 0 V=V(P_VEE) + 1.5 + (V(P_VCC)-V(P_VEE)-3) * (1 / (1 + exp(-100000 * (V(P_NI)-V(P_INV)))))
.ENDS TL071

* LM386 Audio Amplifier Macro Model
* Pinout: 1=Gain 2=Inv 3=NonInv 4=GND 5=Out 6=Vs 8=Gain
.SUBCKT LM386 P_G1 P_INV P_NI P_GND P_OUT P_VS P_G8
  * Internal Gain Resistor (1.35k) connecting Pins 1 and 8
  R_GAIN_INT P_G1 P_G8 1.35k
  * High resistance to GND to prevent floating node errors for the Gain capacitor
  R_C1 P_G1 0 100Meg
  R_C8 P_G8 0 100Meg

  * Audio Amplifier Behavioral Source
  * Self-biasing output to Vs/2
  * Fixed Gain approx 200 (Assuming C_GAIN is present externally)
  B_OUT P_OUT P_GND V=V(P_VS)/2 + 200*(V(P_NI)-V(P_INV))
.ENDS LM386

* --- Main Circuit ---

* Power Supply (9V)
V1 VCC 0 DC 9

* Power Supply Decoupling
C_DEC VCC 0 100n

* Bias Voltage Generator (VCC/2)
R_B1 VCC V_BIAS 10k
R_B2 V_BIAS 0 10k
C_BIAS V_BIAS 0 10u

* --- Stage 1: Transimpedance Amplifier (TIA) ---
* U1 TL071 Op-Amp
* Connections: NI=V_BIAS, INV=N_INV, V+=VCC, V-=0, OUT=V_PRE
XU1 V_BIAS N_INV VCC 0 V_PRE TL071

* Photodiode Sensor (Reverse Biased)
* Cathode to VCC, Anode to N_INV
D1 N_INV VCC D_BPW34

* Optical Signal Simulation
* Current source representing modulated light (1kHz square wave)
* Connected parallel to photodiode (Anode to Cathode current flow)
I_LIGHT N_INV VCC PULSE(0 2u 0 1u 1u 500u 1000u)

* Feedback Resistor
R_F N_INV V_PRE 100k

* --- Signal Coupling ---
* DC Blocking Capacitor
C_COUP V_PRE NODE_POT_TOP 4.7u

* Volume Potentiometer (10k)
* Modeled as voltage divider. Wiper set to 20% to manage gain.
* Top Resistor (8k)
R_VOL_TOP NODE_POT_TOP V_WIPER 8k
* Bottom Resistor (2k)
R_VOL_BOT V_WIPER 0 2k

* --- Stage 2: Power Amplifier ---
* U2 LM386 Audio Amp
* Connections: 1=GAIN_P, 2=0, 3=V_WIPER, 4=0, 5=V_AMP_OUT, 6=VCC, 8=GAIN_N
XU2 GAIN_P 0 V_WIPER 0 V_AMP_OUT VCC GAIN_N LM386

* Gain Setting Capacitor (Pins 1-8)
C_GAIN GAIN_P GAIN_N 10u

* Output Coupling Capacitor
C_OUT V_AMP_OUT V_SPK 220u

* Speaker Load (8 Ohm)
LS1 V_SPK 0 8

* --- Simulation Directives ---
* Transient analysis for 5ms to see 5 cycles of 1kHz audio
.tran 10u 5ms

* Output data for plotting
.print tran V(V_PRE) V(V_WIPER) V(V_SPK)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

  1. Reversed Photodiode Polarity: Connecting the anode to VCC will forward bias the diode, causing it to conduct fully and saturate the amplifier. Solution: Ensure the Cathode (usually marked with a flat side or shorter lead) goes to VCC.
  2. Omitting DC Blocking Capacitors: Connecting the output of the TIA directly to the LM386 volume pot can upset the biasing of the audio amp. Solution: Always use C_COUP to pass only the audio signal and block the DC offset.
  3. Optical Saturation: Testing under direct sunlight or very strong artificial light saturates the photodiode, flattening the signal. Solution: Use an optical shield (a black tube) around D1 to limit the field of view to the transmitter only.

Troubleshooting

  • Symptom: Constant loud hum or buzzing.
    • Cause: 50Hz/60Hz noise pickup from ambient room lighting (fluorescent/mains).
    • Fix: Turn off room lights or use an optical filter (red/IR plastic) over D1.
  • Symptom: No audio, but V_PRE shows signal.
    • Cause: R_VOL is at minimum or LM386 wiring is incorrect.
    • Fix: Check the wiper connection of the potentiometer and ensure U2 power pins are correct.
  • Symptom: Signal is clipped (squared off) at the TIA.
    • Cause: Gain resistor R_F is too high for the light intensity received.
    • Fix: Reduce R_F to 47 kΩ or move the transmitter further away.

Possible improvements and extensions

  1. Bandpass Filter: Replace R_F with a T-network or add a capacitor in parallel to create a low-pass filter, and add a high-pass filter stage to remove 50/60Hz mains hum.
  2. Schmitt Trigger Output: Feed the output of V_PRE into a comparator or Schmitt trigger (like a 74HC14) to convert the analog audio receiver into a digital data receiver for UART transmission.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the photodiode in this circuit?




Question 2: In which mode is the high-speed photodiode configured for this receiver?




Question 3: What component immediately follows the photodiode in the signal chain?




Question 4: Which of the following is listed as a security benefit of optical communication compared to RF?




Question 5: What is the purpose of Galvanic Isolation mentioned in the text?




Question 6: What is the expected outcome for the TIA output (V_PRE)?




Question 7: Why is this system considered immune to electromagnetic interference (EMI)?




Question 8: What technology is mentioned as sharing fundamental physics with this project?




Question 9: What is the ultimate output device that reproduces the sound in this receiver?




Question 10: What is the difficulty level assigned to this project?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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