Level: Basic. Build a circuit to amplify a weak audio signal using an NPN transistor in common-emitter configuration.

Objective and use case

In this case, you will build a classic single-stage Class A amplifier using an NPN transistor with voltage divider biasing. You will input a small AC signal (representing audio) and observe a larger voltage swing at the output.

• Why it is useful:

  • Pre-amplification: Boosts weak signals from microphones before they reach a power amplifier.
  • Signal conditioning: Raises sensor output levels to be readable by microcontrollers.
  • Analog processing: Fundamental building block for filters, oscillators, and mixers.
  • Impedance matching: Buffers high-impedance sources to drive lower-impedance loads (depending on specific configuration).

• Expected outcome:

  • DC Operating Point: VCE stabilizes around half the supply voltage (VCC / 2) for maximum swing.
  • Amplification: The AC output voltage (Vout) is significantly larger than the input (Vin), indicating Voltage Gain (Av > 1).
  • Phase Inversion: The output signal waveform is inverted (180^\circ) relative to the input.
  • Current Flow: IC is controlled by IB according to the transistor’s beta (\beta).

• Target audience and level: Students with basic knowledge of Ohm’s Law and component identification.

Materials

• V1: 9 V DC battery or bench supply, function: main circuit power.
• V2: Signal Generator (Sine wave, 1 kHz, 20 mV peak-to-peak), function: simulates weak audio input.
• Q1: 2N3904 (or 2N2222) NPN BJT, function: active amplifying element.
• R1: 22 kΩ resistor, function: upper base bias divider.
• R2: 6.8 kΩ resistor, function: lower base bias divider.
• R3: 4.7 kΩ resistor, function: collector load (sets gain and output impedance).
• R4: 1 kΩ resistor, function: emitter degeneration (sets DC stability).
• C1: 10 µF electrolytic capacitor, function: input DC blocking.
• C2: 10 µF electrolytic capacitor, function: output DC blocking.
• C3: 100 µF electrolytic capacitor, function: emitter bypass (increases AC gain).

Wiring guide

Use the following nodes to wire your circuit: VCC (9 V), 0 (GND), BASE, COLL, EMIT, VIN, VOUT.

• V1: Positive terminal connects to VCC, Negative terminal connects to 0.
• V2: Signal output connects to VIN, Ground connects to 0.
• R1: Connects between VCC and BASE.
• R2: Connects between BASE and 0.
• R3: Connects between VCC and COLL.
• R4: Connects between EMIT and 0.
• Q1: Collector pin to COLL, Base pin to BASE, Emitter pin to EMIT.
• C1: Positive leg to BASE, Negative leg to VIN.
• C2: Positive leg to COLL, Negative leg to VOUT (Load/Scope probe connects here).
• C3: Positive leg to EMIT, Negative leg to 0 (Place in parallel with R4).

Conceptual block diagram

Schematic

Title: Practical case: Simple audio amplifier

      (BIAS & INPUT NETWORK)                               (POWER & OUTPUT NETWORK)
      ======================                               ========================

                                                           VCC (9 V)
      VCC (9 V)                                                |
         |                                                    |
         v                                                    v
    [ R1: 22k ]                                          [ R3: 4.7k ]
         |                                                    |
         v                                                    v
      (BASE) --------(Control Signal)----------------> [ Q1: Collector ] <--(COLL)--+
         ^                                                    |                     |
         |                                                    | (Amplified Current) |
    [ C1: 10uF ] <--(VIN)-- [ V2: Source ]                    v                     |
         |                                             [ Q1: Emitter ]              +--> [ C2: 10uF ] --> VOUT
         v                                                    |
    [ R2: 6.8k ]                                              v
         |                                                  (EMIT)
         v                                                    |
        GND                                       +-----------+-----------+
                                                  |                       |
                                                  v                       v
                                             [ R4: 1k ]             [ C3: 100uF ]
                                                  |                       |
                                                  v                       v
                                                 GND                     GND

Measurements and tests

Perform these tests using a Multimeter (DMM) and an Oscilloscope (if available).

1. DC Bias Check (Quiescent Point):

   • Ensure V2 (AC source) is OFF or disconnected.
   • Measure voltage from COLL to 0. It should be approximately 4 V to 5 V (roughly half of VCC).
   • Measure voltage from EMIT to 0. It should be approximately 1 V (VE).
   • Measure voltage from BASE to EMIT (VBE). It must be ~0.65 V to 0.7 V for the transistor to be active.

2. Current Calculation:

   • Calculate Collector Current (IC): IC ≈ VEMIT / R4. Expect approx 1 mA.
   • Calculate Base Current (IB): IC / \beta (assuming \beta ≈ 100, IB ≈ 10 µ A).

3. AC Gain Verification:

   • Connect V2 (VIN) with a 20 mV peak-to-peak sine wave at 1 kHz.
   • Measure the Peak-to-Peak voltage at VOUT.
   • Calculate Voltage Gain (Av): Av = Voutpp / Vinpp.
   • Observation: Without C3, gain is low (≈ R3 / R4). With C3 connected, gain should increase significantly.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Simple audio amplifier

* --- Power Supply ---
* V1: 9 V DC battery
V1 VCC 0 DC 9

* --- Input Signal ---
* V2: Signal Generator (Sine wave, 1 kHz, 20 mV peak-to-peak -> 10mV Amplitude)
V2 VIN 0 SIN(0 10m 1k)

* --- Components ---
* Q1: 2N3904 NPN BJT
Q1 COLL BASE EMIT 2N3904

* R1: Upper base bias divider
R1 VCC BASE 22k

* R2: Lower base bias divider
R2 BASE 0 6.8k

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: Simple audio amplifier

* --- Power Supply ---
* V1: 9 V DC battery
V1 VCC 0 DC 9

* --- Input Signal ---
* V2: Signal Generator (Sine wave, 1 kHz, 20 mV peak-to-peak -> 10mV Amplitude)
V2 VIN 0 SIN(0 10m 1k)

* --- Components ---
* Q1: 2N3904 NPN BJT
Q1 COLL BASE EMIT 2N3904

* R1: Upper base bias divider
R1 VCC BASE 22k

* R2: Lower base bias divider
R2 BASE 0 6.8k

* R3: Collector load
R3 VCC COLL 4.7k

* R4: Emitter degeneration
R4 EMIT 0 1k

* C1: Input DC blocking (Positive leg to BASE, Negative leg to VIN)
C1 BASE VIN 10u

* C2: Output DC blocking (Positive leg to COLL, Negative leg to VOUT)
C2 COLL VOUT 10u

* C3: Emitter bypass (Positive leg to EMIT, Negative leg to 0)
C3 EMIT 0 100u

* --- Load Simulation ---
* High impedance load to simulate scope probe and prevent floating node error at VOUT
R_SCOPE VOUT 0 1Meg

* --- Models ---
.model 2N3904 NPN(IS=1E-14 VAF=100 BF=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1 TR=250n TF=350p ITF=1 VTF=2 XTF=3)

* --- Analysis Directives ---
.op
.tran 10u 5ms

* --- Output ---
* Prints Input and Output voltages, plus internal transistor nodes
.print tran V(VIN) V(VOUT) V(BASE) V(COLL) V(EMIT)

.end

Simulation Results (Transient Analysis)

Show raw data table (511 rows)

Index   time            v(vin)          v(vout)         v(base)         v(coll)         v(emit)
0	0.000000e+00	0.000000e+00	0.000000e+00	2.100182e+00	2.275541e+00	1.435514e+00
1	1.000000e-07	6.283185e-06	-1.11372e-03	2.100188e+00	2.274427e+00	1.435514e+00
2	2.000000e-07	1.256637e-05	-2.51792e-03	2.100195e+00	2.273023e+00	1.435514e+00
3	4.000000e-07	2.513271e-05	-5.47602e-03	2.100207e+00	2.270065e+00	1.435514e+00
4	8.000000e-07	5.026527e-05	-1.15278e-02	2.100232e+00	2.264013e+00	1.435514e+00
5	1.600000e-06	1.005293e-04	-2.35622e-02	2.100283e+00	2.251979e+00	1.435514e+00
6	3.200000e-06	2.010484e-04	-4.77358e-02	2.100383e+00	2.227805e+00	1.435514e+00
7	6.400000e-06	4.020155e-04	-9.61836e-02	2.100584e+00	2.179357e+00	1.435514e+00
8	1.280000e-05	8.033810e-04	-1.93689e-01	2.100985e+00	2.081852e+00	1.435516e+00
9	2.280000e-05	1.427671e-03	-3.47124e-01	2.101609e+00	1.928416e+00	1.435522e+00
10	3.280000e-05	2.046327e-03	-5.01331e-01	2.102227e+00	1.774210e+00	1.435531e+00
11	4.280000e-05	2.656907e-03	-6.48595e-01	2.102836e+00	1.626945e+00	1.435544e+00
12	5.280000e-05	3.257002e-03	-7.15494e-01	2.103433e+00	1.560045e+00	1.435558e+00
13	6.280000e-05	3.844242e-03	-7.38189e-01	2.104013e+00	1.537349e+00	1.435575e+00
14	7.280000e-05	4.416311e-03	-7.50146e-01	2.104572e+00	1.525391e+00	1.435592e+00
15	8.280000e-05	4.970951e-03	-7.58389e-01	2.105109e+00	1.517147e+00	1.435610e+00
16	9.280000e-05	5.505973e-03	-7.63991e-01	2.105621e+00	1.511545e+00	1.435628e+00
17	1.028000e-04	6.019265e-03	-7.68326e-01	2.106106e+00	1.507209e+00	1.435647e+00
18	1.128000e-04	6.508802e-03	-7.71816e-01	2.106563e+00	1.503719e+00	1.435667e+00
19	1.228000e-04	6.972652e-03	-7.74681e-01	2.106990e+00	1.500853e+00	1.435687e+00
20	1.328000e-04	7.408984e-03	-7.77018e-01	2.107384e+00	1.498515e+00	1.435707e+00
21	1.428000e-04	7.816076e-03	-7.78966e-01	2.107746e+00	1.496566e+00	1.435728e+00
22	1.528000e-04	8.192321e-03	-7.80567e-01	2.108073e+00	1.494964e+00	1.435750e+00
23	1.628000e-04	8.536235e-03	-7.81896e-01	2.108365e+00	1.493635e+00	1.435772e+00
... (487 more rows) ...

Common mistakes and how to avoid them

1. Transistor Pinout Reversal: Swapping the Collector and Emitter prevents amplification and acts like a reverse-biased diode.
   • Solution: Double-check the datasheet for the 2N3904 (E-B-C flat side facing you) before inserting.
2. Capacitor Polarity: Electrolytic capacitors (C1, C2, C3) explode or fail if biased backwards.
   • Solution: Ensure the positive lead (longer leg) faces the more positive DC potential (towards the transistor base/collector).
3. Saturation or Cutoff: Using wrong resistor values shifts the Q-point, causing the signal to clip (flatten) immediately.
   • Solution: Verify DC voltages at the Collector before applying an AC signal. If VC is near 9 V or 0 V, check R1 and R2.

Troubleshooting

• Symptom: No Output Signal.
  • Cause: Loose connection, blown transistor, or V1 is off.
  • Fix: Check continuity on the breadboard rails; verify V1 is 9 V.
• Symptom: Output is Clipped (Flat tops or bottoms).
  • Cause: The amplifier is driven into saturation (flat bottom) or cutoff (flat top), or input signal is too large.
  • Fix: Reduce input amplitude (V2); check bias resistors (R1, R2) to center the Q-point.
• Symptom: Low Gain (Output ≈ Input).
  • Cause: Bypass capacitor C3 is missing, loose, or too small.
  • Fix: Ensure C3 is connected solidly in parallel with R4. This shorts the emitter resistor for AC signals, maximizing gain.

Possible improvements and extensions

1. Volume Control: Replace R2 (or add a pot before C1) with a 10 kΩ potentiometer to attenuate the input signal.
2. Increased Power: Add a second transistor stage (Emitter Follower / Class B push-pull) after VOUT to drive a small 8 Ω speaker instead of just observing voltage on a scope.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic. Objective: Understand BJT cut-off and saturation to control a load (LED) with a small control signal.

Objective and use case

In this practical case, you will build a circuit using an NPN Bipolar Junction Transistor (BJT) to switch a high-current load (an LED) on and off using a low-current control signal triggered by a push button.

Why it is useful:
* Microcontroller interfacing: Allows low-power pins (like those on an Arduino or ESP32) to drive higher current loads.
* Sensor actuation: Enables weak signals from sensors (like LDRs or thermistors) to activate lights or alarms.
* Component protection: Separates the sensitive control circuit from the power circuit.
* Logic switching: Forms the fundamental building block of digital logic gates.

Expected outcome:
* Idle State (Button Released): The transistor is in Cut-off. IC ≈ 0 mA, LED is OFF, and VCE ≈ Vsupply.
* Active State (Button Pressed): The transistor enters Saturation. LED is ON.
* Saturation Voltage: VCE drops to approximately $0.1$ V to $0.2$ V.
* Base Threshold: VBE stabilizes around $0.7$ V when the transistor is conducting.

Target audience: Basic level electronics students.

Materials

• V1: 9 V DC battery or power supply, function: Main circuit power.
• S1: Tactile Push-button (Normally Open), function: User input trigger.
• R1: 10 kΩ resistor, function: Base current limiting (to ensure saturation without damaging the Base).
• R2: 100 kΩ resistor, function: Pull-down resistor (keeps Base at 0 V when S1 is open).
• R3: 330 Ω resistor, function: LED current limiting protection.
• Q1: 2N2222 (or BC547) NPN Transistor, function: Electronic switch.
• D1: Red LED, function: Visual load indicator.

Wiring guide

This guide uses specific node names to help you visualize the connections.
* Power Nodes: Connect V1 positive to node VCC and negative to node 0 (GND).
* Input Stage:
* Connect one side of S1 to VCC.
* Connect the other side of S1 to node INPUT_SIG.
* Connect R1 (10 kΩ) between INPUT_SIG and node BASE.
* Connect R2 (100 kΩ) between node BASE and node 0 (GND).
* Transistor Connections:
* Connect the Base of Q1 to node BASE.
* Connect the Emitter of Q1 directly to node 0 (GND).
* Connect the Collector of Q1 to node COLL.
* Output Load:
* Connect R3 (330 Ω) between VCC and node LED_ANODE.
* Connect the Anode (long leg) of D1 to node LED_ANODE.
* Connect the Cathode (short leg, flat side) of D1 to node COLL.

Conceptual block diagram

Schematic

Title: Practical case: The transistor as a light switch

1. CONTROL PATH (Input Stage)
   Flow: VCC triggers the Base when S1 is pressed. R2 ensures Base is 0 V when S1 is open.

   [ VCC ] --> [ S1: Button ] --(INPUT_SIG)--> [ R1: 10k ] --(BASE)--+--> [ Q1: Base ]
                                                                     |
                                                                     +--> [ R2: 100k ] --> [ GND ]

2. LOAD PATH (Output Stage)
   Flow: Current flows from VCC through the LED into the Transistor Collector.

   [ VCC ] --> [ R3: 330R ] --(LED_ANODE)--> [ D1: Red LED ] --(COLL)--> [ Q1: Collector ]

3. COMMON RETURN (Grounding)
   Flow: The transistor completes the circuit to Ground.

   [ Q1: Emitter ] --> [ GND ]

Measurements and tests

Perform these steps with a multimeter to verify the transistor regions of operation.

1. Test Cut-off Region (Switch Open):

   • Ensure S1 is not pressed.
   • Measure voltage between Base and Emitter (VBE). Result should be 0 V.
   • Measure voltage between Collector and Emitter (VCE). Result should be close to 9 V (Source voltage), indicating the switch is open.
   • Observe D1: It must be OFF.

2. Test Saturation Region (Switch Closed):

   • Press and hold S1.
   • Measure voltage between Base and Emitter (VBE). Result should be approximately 0.65 V to 0.75 V.
   • Measure voltage between Collector and Emitter (VCE). Result should drop to < 0.2 V. This voltage drop proves the transistor is acting as a closed switch (Saturation).
   • Observe D1: It must turn ON brightly.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: The transistor as a light switch
* Improved Netlist with robust switch modelling

.width out=256

* --- Power Supply ---
* V1: 9 V DC battery (Main circuit power)
V1 VCC 0 DC 9

* --- User Input Trigger (S1) ---
* S1: Tactile Push-button (Normally Open) connecting VCC to INPUT_SIG.
* Modeled using a Voltage-Controlled Switch (S1) driven by a control pulse (V_ACT).
* V_ACT simulates the user pressing the button (Logic 0 -> 1 -> 0).
V_ACT ACTUATE 0 PULSE(0 5 1ms 100u 100u 5ms 20ms)
S1 VCC INPUT_SIG ACTUATE 0 SW_TACTILE

* --- Input Stage ---
* R1: 10 kOhm, Base current limiting
R1 INPUT_SIG BASE 10k

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: The transistor as a light switch
* Improved Netlist with robust switch modelling

.width out=256

* --- Power Supply ---
* V1: 9 V DC battery (Main circuit power)
V1 VCC 0 DC 9

* --- User Input Trigger (S1) ---
* S1: Tactile Push-button (Normally Open) connecting VCC to INPUT_SIG.
* Modeled using a Voltage-Controlled Switch (S1) driven by a control pulse (V_ACT).
* V_ACT simulates the user pressing the button (Logic 0 -> 1 -> 0).
V_ACT ACTUATE 0 PULSE(0 5 1ms 100u 100u 5ms 20ms)
S1 VCC INPUT_SIG ACTUATE 0 SW_TACTILE

* --- Input Stage ---
* R1: 10 kOhm, Base current limiting
R1 INPUT_SIG BASE 10k

* R2: 100 kOhm, Pull-down resistor (keeps Base low when S1 is open)
R2 BASE 0 100k

* --- Transistor Switch ---
* Q1: 2N2222 NPN Transistor
* Connections: Collector=COLL, Base=BASE, Emitter=0(GND)
Q1 COLL BASE 0 2N2222

* --- Output Load ---
* R3: 330 Ohm, LED current limiting resistor
R3 VCC LED_ANODE 330

* D1: Red LED
* Connections: Anode=LED_ANODE, Cathode=COLL
D1 LED_ANODE COLL RED_LED

* --- Component Models ---
* Switch Model: Added hysteresis (Vh) and relaxed Ron for better convergence
.model SW_TACTILE SW(Vt=2.5 Vh=0.1 Ron=1 Roff=100Meg)

* Transistor Model: Standard 2N2222 parameters
.model 2N2222 NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8p CJE=25p TR=46.9n TF=411p ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=1 RE=0.1)

* LED Model: Generic Red LED parameters
.model RED_LED D(IS=93.2p RS=42m N=3.73 BV=5 IBV=10u CJO=2.97p VJ=0.75 M=0.33 TT=4.32u)

* --- Analysis Commands ---
.op
* Simulate for 10ms to capture the button press event
.tran 100u 10ms

* --- Output Directives ---
* Printing INPUT (Switch output) and OUTPUT (Collector voltage) first
.print tran V(INPUT_SIG) V(COLL) V(BASE) V(LED_ANODE) V(ACTUATE)

.end

Simulation Results (Transient Analysis)

Show raw data table (170 rows)

Index   time            v(input_sig)    v(coll)         v(base)         v(led_anode)    v(actuate)
0	0.000000e+00	9.890018e-03	8.982941e+00	8.991007e-03	9.000000e+00	0.000000e+00
1	1.000000e-06	9.890019e-03	8.982941e+00	8.991008e-03	9.000000e+00	0.000000e+00
2	2.000000e-06	9.890019e-03	8.982941e+00	8.991008e-03	9.000000e+00	0.000000e+00
3	4.000000e-06	9.890021e-03	8.982941e+00	8.991010e-03	9.000000e+00	0.000000e+00
4	8.000000e-06	9.890021e-03	8.982941e+00	8.991010e-03	9.000000e+00	0.000000e+00
5	1.600000e-05	9.890021e-03	8.982941e+00	8.991010e-03	9.000000e+00	0.000000e+00
6	3.200000e-05	9.890021e-03	8.982941e+00	8.991010e-03	9.000000e+00	0.000000e+00
7	6.400000e-05	9.890021e-03	8.982942e+00	8.991010e-03	9.000000e+00	0.000000e+00
8	1.280000e-04	9.890021e-03	8.982942e+00	8.991010e-03	9.000000e+00	0.000000e+00
9	2.280000e-04	9.890021e-03	8.982943e+00	8.991010e-03	9.000000e+00	0.000000e+00
10	3.280000e-04	9.890021e-03	8.982944e+00	8.991010e-03	9.000000e+00	0.000000e+00
11	4.280000e-04	9.890021e-03	8.982945e+00	8.991010e-03	9.000000e+00	0.000000e+00
12	5.280000e-04	9.890021e-03	8.982946e+00	8.991010e-03	9.000000e+00	0.000000e+00
13	6.280000e-04	9.890021e-03	8.982947e+00	8.991010e-03	9.000000e+00	0.000000e+00
14	7.280000e-04	9.890021e-03	8.982948e+00	8.991010e-03	9.000000e+00	0.000000e+00
15	8.280000e-04	9.890021e-03	8.982949e+00	8.991010e-03	9.000000e+00	0.000000e+00
16	9.280000e-04	9.890021e-03	8.982950e+00	8.991010e-03	9.000000e+00	0.000000e+00
17	1.000000e-03	9.890021e-03	8.982950e+00	8.991010e-03	9.000000e+00	0.000000e+00
18	1.010000e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	5.000000e-01
19	1.027500e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	1.375000e+00
20	1.032344e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	1.617187e+00
21	1.040820e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	2.041016e+00
22	1.043167e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	2.158325e+00
23	1.047272e-03	9.890021e-03	8.982951e+00	8.991010e-03	9.000000e+00	2.363617e+00
... (146 more rows) ...

Common mistakes and how to avoid them

1. Swapping Collector and Emitter:
   • Error: The LED turns on but looks dim or fails to switch completely. The transistor may overheat.
   • Solution: Double-check the pinout of the 2N2222 (E-B-C or C-B-E depending on the specific package/datasheet).
2. Omitting the Base Resistor (R1):
   • Error: Connecting the switch directly to the Base causes a massive current flow from Base to Emitter, destroying the transistor instantly.
   • Solution: Always include a limiting resistor (R1) in series with the Base.
3. Floating Base (Missing R2):
   • Error: The LED might flicker or glow faintly when the switch is open because the Base picks up electromagnetic noise.
   • Solution: Ensure R2 (Pull-down) is connected to ground to discharge the Base capacitance when the switch is open.

Troubleshooting

• Symptom: LED is always ON, even when the button is not pressed.
  • Cause: Transistor C-E shorted internally or R2 is missing/disconnected.
  • Fix: Replace Q1 and check R2 connection to Ground.
• Symptom: LED does not turn ON when button is pressed.
  • Cause: LED connected backwards, R1 value too high (preventing saturation), or R3 too high.
  • Fix: Check LED polarity. Verify R1 is 10 kΩ and R3 is 330 Ω.
• Symptom: LED is very dim when ON.
  • Cause: Transistor is in the «Active» region, not «Saturation».
  • Fix: Decrease R1 slightly (e.g., to 4.7 kΩ) to increase Base current (IB) and force full saturation.

Possible improvements and extensions

1. High Power Control: Replace the LED and R3 with a 9 V Relay (remember to add a flyback diode in parallel with the relay coil) to control a household lamp.
2. Automatic Night Light: Replace the tactile button (S1) with an LDR (Light Dependent Resistor) and adjust the position of resistors to create a sensor that turns on the LED in the dark.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium. Compare voltage ripple in a basic power supply by varying filtering capacitance under load.

Objective and use case

In this practical case, you will build a Full-Wave Bridge Rectifier circuit coupled with a selectable filter capacitor bank and a resistive load. You will analyze how the value of the filter capacitor affects the quality of the DC output by measuring the «ripple» voltage superimposed on the DC signal.

• Audio Power Supplies: Reducing 50/60 Hz hum in amplifiers and speakers.
• Digital Logic Power: Ensuring stable voltage levels to prevent microcontroller resets or erratic behavior.
• Sensor Conditioning: Providing clean DC power to analog sensors for accurate readings.
• Battery Charging: Smoothing the charging current to prolong battery life.

Expected outcome:
* Waveform Transformation: Visual observation of AC sine wave converting to pulsing DC, then to smooth DC.
* Ripple Voltage (Vripple): A high peak-to-peak ripple voltage (> 5 V) with a small capacitor (10 µF).
* Smoothing Effect: A significantly reduced ripple voltage (< 0.5 V) when switching to a large capacitor (470 µF).
* Target Audience: Intermediate electronics students and hobbyists familiar with AC/DC concepts.

Materials

• V1: 12 V (RMS) AC transformer secondary or AC function generator (60 Hz), function: AC power source.
• D1: 1N4007 Diode, function: Bridge rectifier top-left.
• D2: 1N4007 Diode, function: Bridge rectifier top-right.
• D3: 1N4007 Diode, function: Bridge rectifier bottom-left.
• D4: 1N4007 Diode, function: Bridge rectifier bottom-right.
• R1: 220 Ω resistor (2 Watt rating recommended), function: Static Load.
• C1: 10 µF electrolytic capacitor (25 V or higher), function: Low-value filter.
• C2: 470 µF electrolytic capacitor (25 V or higher), function: High-value filter.
• S1: SPDT Switch or jumper wire, function: Selects between C1 and C2.
• Test Equipment: Oscilloscope (preferred) or Multimeter with AC/DC measurement capabilities.

Wiring guide

Construct the circuit using the following node connections. Ensure electrolytic capacitors are connected with correct polarity (Positive terminal to V_DC, Negative terminal to 0 / GND).

• V1 (Source): Connects between node AC_L and node AC_N.
• D1: Anode connects to AC_L, Cathode connects to V_DC.
• D2: Anode connects to AC_N, Cathode connects to V_DC.
• D3: Anode connects to 0 (GND), Cathode connects to AC_L.
• D4: Anode connects to 0 (GND), Cathode connects to AC_N.
• R1 (Load): Connects between node V_DC and node 0 (GND).
• C1 (Test Case A): Positive terminal to V_DC, Negative terminal to 0 (GND).
• C2 (Test Case B): Positive terminal to V_DC, Negative terminal to 0 (GND) (Replace C1 with C2 for second test).

Conceptual block diagram

Schematic

[ INPUT SOURCE ]              [ RECTIFICATION ]                [ FILTER STAGE ]                 [ OUTPUT LOAD ]

                                                                  +-> [ Capacitor C1 ] -+
                                                                  |     (10 uF)         |
 [ AC Source V1 ] --(12 V AC)--> [ Bridge Rectifier ] --(Raw DC)-->+                     +--(V_DC)--> [ Load Resistor R1 ]
    (12 V RMS)                   [  D1, D2, D3, D4  ]              |   [ Switch S1  ]    |            (220 Ohm)
                                                                  +-> [ Capacitor C2 ] -+                |
                                                                        (470 uF)                         |
                                                                                                         |
                                                                                                         v
                                                                                                  [ Oscilloscope ]
                                                                                                  (Measure Ripple)

Measurements and tests

Follow these steps to validate the smoothing efficiency:

1. Baseline (No Capacitor): Temporarily remove any capacitor. Measure V_DC with an oscilloscope. You should see a full-wave rectified signal (humps going to 0 V) at 120 Hz (or 100 Hz).
2. Small Capacitor Test (C1 = 10 µ F):
   • Insert $C1$.
   • Measure the peak voltage (Vpeak) and the minimum valley voltage (Vmin).
   • Calculate Ripple: Vripple = Vpeak – Vmin.
   • Expectation: Significant sawtooth ripple (fast discharge).
3. Large Capacitor Test (C2 = 470 µ F):
   • Replace $C1$ with $C2$.
   • Measure Vpeak and Vmin again.
   • Expectation: The DC line is much flatter; Vmin stays close to Vpeak.
4. DC Average: Switch your multimeter to DC Volts. Compare the reading of $C1$ vs $C2$. The average voltage with $C2$ will be higher because the capacitor maintains the charge longer.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Linear supply voltage smoothing
*
* Description:
* This netlist simulates a full-wave bridge rectifier power supply with a 
* selectable smoothing capacitor.
* - 0ms to 100ms: C1 (10uF) is connected (High Ripple case).
* - 100ms to 200ms: C2 (470uF) is connected (Low Ripple case), simulating
*   switch S1 toggling.
*
* Connections:
* V1 (AC Source) -> Nodes AC_L, AC_N
* D1-D4 (Bridge) -> Nodes AC_L, AC_N, V_DC, 0 (GND)
* R1 (Load)      -> Nodes V_DC, 0
* S1 (Switch)    -> Modeled via S_C1 and S_C2 connecting V_DC to C1/C2
*
* -----------------------------------------------------------------------------

* --- AC Power Source ---
* 12V RMS AC, 60Hz. 
* Peak Voltage = 12 * sqrt(2) = 16.97 V
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Linear supply voltage smoothing
*
* Description:
* This netlist simulates a full-wave bridge rectifier power supply with a 
* selectable smoothing capacitor.
* - 0ms to 100ms: C1 (10uF) is connected (High Ripple case).
* - 100ms to 200ms: C2 (470uF) is connected (Low Ripple case), simulating
*   switch S1 toggling.
*
* Connections:
* V1 (AC Source) -> Nodes AC_L, AC_N
* D1-D4 (Bridge) -> Nodes AC_L, AC_N, V_DC, 0 (GND)
* R1 (Load)      -> Nodes V_DC, 0
* S1 (Switch)    -> Modeled via S_C1 and S_C2 connecting V_DC to C1/C2
*
* -----------------------------------------------------------------------------

* --- AC Power Source ---
* 12V RMS AC, 60Hz. 
* Peak Voltage = 12 * sqrt(2) = 16.97 V
V1 AC_L AC_N SIN(0 16.97 60)

* --- Bridge Rectifier (1N4007) ---
* D1: Anode=AC_L, Cathode=V_DC
D1 AC_L V_DC D1N4007
* D2: Anode=AC_N, Cathode=V_DC
D2 AC_N V_DC D1N4007
* D3: Anode=GND, Cathode=AC_L
D3 0 AC_L D1N4007
* D4: Anode=GND, Cathode=AC_N
D4 0 AC_N D1N4007

* --- Load Resistor ---
* 220 Ohm resistor across the DC output
R1 V_DC 0 220

* --- Filter Capacitors & Switching Logic ---
* We simulate the SPDT switch S1 by using two voltage-controlled switches.
* S_C1 connects V_DC to C1. S_C2 connects V_DC to C2.
* Control signals ensure only one is active at a time (break-before-make effectively).

* Capacitor C1 (10uF) path
S_C1 V_DC NET_C1 CTRL_C1 0 SW_MODEL
C1 NET_C1 0 10u

* Capacitor C2 (470uF) path
S_C2 V_DC NET_C2 CTRL_C2 0 SW_MODEL
C2 NET_C2 0 470u

* --- Control Signals (Dynamic Stimuli) ---
* CTRL_C1: Starts High (5V), goes Low (0V) at 100ms.
* Keeps C1 connected for the first 100ms.
V_CTRL_C1 CTRL_C1 0 PULSE(5 0 100m 1u 1u 1 2)

* CTRL_C2: Starts Low (0V), goes High (5V) at 100ms.
* Connects C2 for the remainder of the simulation.
V_CTRL_C2 CTRL_C2 0 PULSE(0 5 100m 1u 1u 1 2)

* --- Component Models ---
* Generic model for 1N4007 Power Diode
.model D1N4007 D(IS=7.03n RS=0.034 N=1.8 BV=1000 IBV=5u CJO=10p TT=100n)

* Ideal Switch Model (Threshold=2.5V, On-Res=10mOhm, Off-Res=100MegOhm)
.model SW_MODEL SW(Vt=2.5 Ron=0.01 Roff=100Meg)

* --- Analysis Directives ---
* Transient analysis: 200ms total time, 50us step size.
* This captures approx 6 cycles with C1 and 6 cycles with C2.
.tran 50u 200m

* Print directives for simulation log/plotting
.print tran V(V_DC) V(AC_L) V(AC_N)

.end

Simulation Results (Transient Analysis)

Show raw data table (4050 rows)

Index   time            v(v_dc)         v(ac_l)         v(ac_n)
0	0.000000e+00	6.658603e-23	4.156609e-18	4.156609e-18
1	5.000000e-07	1.885342e-19	1.599385e-03	-1.59938e-03
2	1.000000e-06	6.893339e-12	3.198770e-03	-3.19877e-03
3	2.000000e-06	3.416858e-11	6.397539e-03	-6.39754e-03
4	4.000000e-06	1.718574e-10	1.279507e-02	-1.27951e-02
5	8.000000e-06	9.966330e-10	2.559012e-02	-2.55901e-02
6	1.325366e-05	3.861142e-09	4.239524e-02	-4.23952e-02
7	2.095388e-05	1.446061e-08	6.702595e-02	-6.70259e-02
8	3.129676e-05	5.099200e-08	1.001088e-01	-1.00109e-01
9	4.482862e-05	1.835180e-07	1.433897e-01	-1.43390e-01
10	6.128867e-05	6.888081e-07	1.960312e-01	-1.96031e-01
11	8.042390e-05	2.827323e-06	2.572195e-01	-2.57217e-01
12	1.019046e-04	1.303092e-05	3.258956e-01	-3.25883e-01
13	1.254895e-04	6.815023e-05	4.012964e-01	-4.01228e-01
14	1.509795e-04	4.024321e-04	4.828893e-01	-4.82487e-01
15	1.782228e-04	2.626479e-03	5.709779e-01	-5.68351e-01
16	2.071492e-04	1.723315e-02	6.705660e-01	-6.53333e-01
17	2.380619e-04	8.388777e-02	8.024272e-01	-7.18539e-01
18	2.734880e-04	2.529945e-01	9.997734e-01	-7.46779e-01
19	3.097680e-04	4.785526e-01	1.227902e+00	-7.49349e-01
20	3.521718e-04	7.463483e-01	1.496384e+00	-7.50036e-01
21	3.938443e-04	1.008721e+00	1.759554e+00	-7.50833e-01
22	4.438443e-04	1.322891e+00	2.074586e+00	-7.51694e-01
23	4.938443e-04	1.636032e+00	2.388601e+00	-7.52568e-01
... (4026 more rows) ...

Common mistakes and how to avoid them

• Reversed Capacitor Polarity: Electrolytic capacitors will explode if connected backwards. Solution: Ensure the side marked with a stripe (negative) connects to the 0 (GND) node and the other side to the positive rectifier output.
• Under-rated Resistor Power: A 220 Ω resistor at ~15 V DC dissipates about 1 Watt (P = V^2 / R). Using a standard 1/4 W resistor will burn it. Solution: Use a power resistor (2 W+) or increase resistance to 1 kΩ (though this reduces ripple visibility).
• Measuring Ripple on DC Setting: A standard multimeter on DC mode averages the voltage, hiding the ripple. Solution: Use an oscilloscope for visual analysis, or set the multimeter to AC mode to measure the RMS value of the ripple component only.

Troubleshooting

• Symptom: No output voltage at V_DC.
  • Cause: AC source not on or bridge diodes open/connected incorrectly.
  • Fix: Check V1 output and verify diode orientation (ring marks on cathodes).
• Symptom: Ripple does not change when swapping capacitors.
  • Cause: Load resistor $R1$ is missing or open circuit. Without a load, the capacitor has no path to discharge, so voltage stays at peak regardless of capacitance.
  • Fix: Ensure $R1$ is securely connected parallel to the capacitor.
• Symptom: Fuse blows or transformer hums loudly.
  • Cause: Short circuit in the bridge (e.g., D1 and D3 shorting AC mains).
  • Fix: Power off immediately and check wiring. Ensure AC_L and AC_N are not directly connected to 0 or each other.

Possible improvements and extensions

1. Voltage Regulator: Add an LM7812 or LM317 linear regulator after the capacitor to see how active regulation eliminates the remaining ripple.
2. RC Pi Filter: Add a series resistor and a second capacitor ($C-R-C$) to create a passive low-pass filter, further reducing ripple without active components (at the cost of voltage drop).

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium — Design and analyze a circuit that attenuates high frequencies using a capacitor and a resistor to verify the cutoff frequency.

Objective and use case

In this practical case, you will build a passive first-order Low-Pass Filter (LPF) using a resistor and a capacitor connected in series. You will analyze how the capacitor’s reactance changes with frequency, allowing low frequencies to pass while attenuating signals above a calculated cutoff point.

Why it is useful:
* Audio noise reduction: Removes high-frequency hiss or static from audio recordings.
* Subwoofer crossovers: Directs only low-frequency bass notes to the subwoofer driver.
* Signal conditioning: Acts as an anti-aliasing filter before Analog-to-Digital Conversion (ADC) to prevent digital artifacts.
* Power supply smoothing: Filters out high-frequency ripple noise from DC power lines.

Expected outcome:
* Passband: Frequencies below ~1 kHz retain approximately their original amplitude (Vin ≈ Vout).
* Cutoff point: At the calculated cutoff frequency (fc), the output voltage drops to approximately 70.7% of the input voltage (-3 dB).
* Stopband: Frequencies significantly higher than 1 kHz are heavily attenuated.
* Phase shift: Observe a phase lag of -45° at the cutoff frequency.

Target audience and level: Electronics students and audio enthusiasts; Level: Medium.

Materials

• V1: AC Voltage Source (Sine Wave, 5 Vpk, tunable frequency), function: Input audio signal simulation.
• R1: 1.6 kΩ resistor, function: Current limiting and voltage division partner.
• C1: 100 nF capacitor (ceramic or film), function: Frequency-dependent shunt to ground.
• Measurement Tool: Oscilloscope (Dual channel) or Bode Plotter.

Wiring guide

Construct the circuit using the following connections. Note the explicit node names for analysis.

• V1 (Source): Connect the positive terminal to node VIN and the negative terminal to node 0 (GND).
• R1: Connect one leg to node VIN and the other leg to node VOUT.
• C1: Connect one leg to node VOUT and the other leg to node 0 (GND).
• Oscilloscope Ch1: Connect probe tip to VIN and ground clip to 0.
• Oscilloscope Ch2: Connect probe tip to VOUT and ground clip to 0.

Conceptual block diagram

Schematic

[ SIGNAL SOURCE ]               [ RC FILTER STAGE ]                 [ MEASUREMENT ]

                              +--------------------------------------> [ Scope Ch1 (Input) ]
                              |
[ V1: AC Source ] --(VIN)-->--+--> [ R1: 1.6k Resistor ] --(VOUT)-->--+--> [ Scope Ch2 (Output) ]
      (5 Vpk)                                                         |
                                                                      +--> [ C1: 100nF Cap ] --> GND

Measurements and tests

Follow these steps to validate the filter design (fc ≈ 1 kHz):

1. Low Frequency Test (Passband):

   • Set V1 to 100 Hz.
   • Measure Vout peak-to-peak. It should be nearly identical to Vin (approx. 5 V).

2. Cutoff Frequency Verification (fc):

   • Increase V1 frequency to 1 kHz.
   • Measure Vout. It should drop to approximately 0.707 × Vin (approx. 3.53 V).
   • Measure the phase difference between Ch1 and Ch2. Vout should lag Vin by roughly 45°.

3. High Frequency Test (Stopband):

   • Set V1 to 10 kHz (one decade above cutoff).
   • Measure Vout. The amplitude should be significantly attenuated (approx. 0.5 V or -20 dB relative to input).

4. Bode Plot Analysis (Optional):

   • If using a simulation or Bode plotter, sweep from 10 Hz to 100 kHz. Observe the «roll-off» slope of -20 dB/decade after the cutoff point.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: RC audio low-pass filter

* --- Components per BOM and Wiring Guide ---
* V1: AC Voltage Source (Sine Wave, 5 Vpk, 1kHz, AC 1V for Bode)
* Connected: Positive -> VIN, Negative -> 0 (GND)
V1 VIN 0 DC 0 AC 1 SIN(0 5 1000)

* R1: 1.6 kOhm resistor
* Connected: VIN -> VOUT
R1 VIN VOUT 1.6k

* C1: 100 nF capacitor
* Connected: VOUT -> 0 (GND)
C1 VOUT 0 100n

* --- Simulation Commands ---
* Using .control block to sequence analyses and printing correctly in ngspice
.control
    * Transient Analysis: 1kHz signal, run for 5ms
    tran 10u 5ms
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: RC audio low-pass filter

* --- Components per BOM and Wiring Guide ---
* V1: AC Voltage Source (Sine Wave, 5 Vpk, 1kHz, AC 1V for Bode)
* Connected: Positive -> VIN, Negative -> 0 (GND)
V1 VIN 0 DC 0 AC 1 SIN(0 5 1000)

* R1: 1.6 kOhm resistor
* Connected: VIN -> VOUT
R1 VIN VOUT 1.6k

* C1: 100 nF capacitor
* Connected: VOUT -> 0 (GND)
C1 VOUT 0 100n

* --- Simulation Commands ---
* Using .control block to sequence analyses and printing correctly in ngspice
.control
    * Transient Analysis: 1kHz signal, run for 5ms
    tran 10u 5ms
    * Print transient results (Oscilloscope)
    print V(VIN) V(VOUT)

    * AC Analysis: Bode Plot, 10 Hz to 100 kHz
    ac dec 10 10 100k
    * Print AC results (Bode Plotter)
    print V(VOUT)

    * Operating Point
    op
.endc

.end

Simulation Results (Transient Analysis)

Show raw data table (512 rows)

Index   time            v(vin)          v(vout)
0	0.000000e+00	0.000000e+00	0.000000e+00
1	1.000000e-07	3.141592e-03	1.962269e-06
2	1.084035e-07	3.405596e-03	2.141025e-06
3	1.252105e-07	3.933604e-03	2.526248e-06
4	1.588245e-07	4.989618e-03	3.462948e-06
5	2.260525e-07	7.101647e-03	6.001184e-06
6	3.605086e-07	1.132570e-02	1.373560e-05
7	6.294206e-07	1.977378e-02	3.982505e-05
8	1.167245e-06	3.666975e-02	1.343969e-04
9	2.242893e-06	7.046023e-02	4.923968e-04
10	4.394190e-06	1.380300e-01	1.878099e-03
11	8.696783e-06	2.730815e-01	7.282571e-03
12	1.730197e-05	5.424874e-01	2.825846e-02
13	2.730197e-05	8.535162e-01	6.884897e-02
14	3.730197e-05	1.161176e+00	1.257276e-01
15	4.730197e-05	1.464254e+00	1.976662e-01
16	5.730197e-05	1.761553e+00	2.834382e-01
17	6.730197e-05	2.051900e+00	3.818193e-01
18	7.730197e-05	2.334149e+00	4.915893e-01
19	8.730197e-05	2.607186e+00	6.115335e-01
20	9.730197e-05	2.869934e+00	7.404442e-01
21	1.073020e-04	3.121356e+00	8.771230e-01
22	1.173020e-04	3.360458e+00	1.020383e+00
23	1.273020e-04	3.586299e+00	1.169049e+00
... (488 more rows) ...

Common mistakes and how to avoid them

1. Swapping components (High-Pass vs. Low-Pass):
   • Error: Connecting C1 in series and R1 to ground creates a High-Pass filter.
   • Solution: Ensure the Capacitor is the component connected between the output node and Ground.
2. Ignoring Load Impedance:
   • Error: Connecting a low-impedance load (like an 8 Ω speaker) directly to VOUT.
   • Solution: This passive filter has high output impedance. Use an op-amp buffer if driving a heavy load.
3. Using Polarized Capacitors Incorrectly:
   • Error: Using an electrolytic capacitor with reverse polarity in an AC circuit without a DC bias.
   • Solution: For pure AC audio signals, use non-polarized capacitors (ceramic, film, or bipolar electrolytic).

Troubleshooting

• Symptom: Vout is zero at all frequencies.
  • Cause: Short circuit across C1 or open circuit at R1.
  • Fix: Check continuity across C1; if it beeps, the capacitor is shorted or the node is grounded accidentally.
• Symptom: No attenuation occurs at high frequencies.
  • Cause: C1 is open (broken) or R1 is shorted.
  • Fix: Replace C1. Verify R1 measures 1.6 kΩ.
• Symptom: Cutoff frequency is totally wrong.
  • Cause: Incorrect component values (e.g., using 100 pF instead of 100 nF).
  • Fix: Double-check color codes on resistors and markings on capacitors (104 code = 100 nF).

Possible improvements and extensions

1. Second-Order Filter: Cascade two RC stages in series to achieve a steeper roll-off (-40 dB/decade) for better noise rejection.
2. Active Low-Pass Filter: Add an Operational Amplifier (Op-Amp) to create an active filter, allowing for signal gain and preventing the load from affecting the filter’s frequency response.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic. Build an off-delay circuit using the slow discharge of a capacitor to control a transistor.

Objective and use case

In this session, you will build an analog timer circuit that keeps an LED illuminated for a specific duration after a push-button is released. This demonstrates how a capacitor stores energy and discharges it over time to control a switching element (the transistor).

Why it is useful:
* Interior car lighting: Lights that fade out slowly after the door is closed.
* Staircase timers: Lighting that remains on long enough for someone to climb the stairs.
* Bathroom fans: Fans that continue running for a few minutes after being switched off to clear humidity.
* Debouncing: Smoothing out short, unwanted signal interruptions.

Expected outcome:
* Button Press: The LED turns ON immediately to full brightness.
* Button Release: The LED remains ON initially.
* Delay Phase: The LED gradually dims and turns OFF after a few seconds as the capacitor voltage drops.
* Target Audience: Students and hobbyists learning about RC time constants and transistor switching.

Materials

• V1: 9 V DC supply, function: main power source.
• S1: Push-button (Normally Open), function: charging trigger.
• C1: 470 µF electrolytic capacitor, function: timing and energy storage.
• R1: 10 kΩ resistor, function: discharge timing resistor.
• R2: 470 Ω resistor, function: LED current limiting.
• Q1: 2N2222 NPN transistor, function: current switch.
• D1: Red LED, function: visual output indicator.

Wiring guide

Construct the circuit following these connections using the specific node names provided.

• Power Supply:

  • Connect V1 positive terminal to node VCC.
  • Connect V1 negative terminal to node 0 (GND).

• Input and Timing Network:

  • Connect S1 between node VCC and node VCAP.
  • Connect C1 positive terminal to node VCAP.
  • Connect C1 negative terminal to node 0.
  • Connect R1 between node VCAP and node BASE.

• Transistor Switch:

  • Connect Q1 Base to node BASE.
  • Connect Q1 Emitter to node 0.
  • Connect Q1 Collector to node COL.

• Output Load (LED):

  • Connect R2 between node VCC and node LED_A.
  • Connect D1 Anode to node LED_A.
  • Connect D1 Cathode to node COL.

Conceptual block diagram

Schematic

[ INPUT & TIMING ]                  [ LOGIC / SWITCH ]                 [ OUTPUT LOAD ]

(VCC 9 V) --+--(Power Path)--------------------------------------------------> [ Resistor R2 ]
           |                                                                        |
           |                                                                        v
     [ Button S1 ]                                                             [ LED D1 ]
           |                                                                        |
           v (Trigger)                                                              |
     [ Node VCAP ] --(Slow Discharge)--> [ Resistor R1 ] --(Base Sig)-->+           |
           |                                                            |           |
           + <--(Stores Charge)-- [ Capacitor C1 ]                      |           |
                                       |                                v           v
                                       v                        +-----------------------+
                                    [ GND ]                     |     TRANSISTOR Q1     |
                                                                | (Base)    (Collector) |
                                                                +-----------------------+
                                                                            |
                                                                            v (Emitter)
                                                                         [ GND ]

Measurements and tests

Follow these steps to validate the circuit behavior using a multimeter.

1. Initial State: Ensure S1 is not pressed. The LED should be OFF.
   • Measure voltage at VCAP. It should be near 0 V.
2. Charging Phase: Press and hold S1.
   • Check: The LED turns ON immediately.
   • Measurement: The voltage at VCAP should instantly rise to approximately 9 V (VCC).
3. Discharge Phase: Release S1 and start a stopwatch.
   • Observation: The LED remains lit.
   • Measurement: Monitor the voltage at VCAP. It will slowly decrease.
   • Threshold: When VCAP drops below approximately 1.4 V (V_BE + drop across R1), the LED will dim significantly and turn OFF.
4. Time Constant: Record the time from release until the LED turns completely off.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Simple Transistor Timer

* --- Power Supply ---
* V1: 9 V DC supply
V1 VCC 0 DC 9

* --- Input and Timing Network ---
* S1: Push-button (Normally Open)
* Modeled as a Voltage Controlled Switch (S1) driven by a control pulse (V_S1_ACT)
* Connects VCC to VCAP when activated
S1 VCC VCAP CTRL 0 SW_MODEL

* Control signal for the button press simulation
* Press button at T=0.5s, hold for 0.5s, then release to allow discharge
V_S1_ACT CTRL 0 PULSE(0 5 0.5 1m 1m 0.5 20)

* C1: 470 µF electrolytic capacitor
C1 VCAP 0 470u

* R1: 10 kΩ resistor (Discharge path to Base)
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: Simple Transistor Timer

* --- Power Supply ---
* V1: 9 V DC supply
V1 VCC 0 DC 9

* --- Input and Timing Network ---
* S1: Push-button (Normally Open)
* Modeled as a Voltage Controlled Switch (S1) driven by a control pulse (V_S1_ACT)
* Connects VCC to VCAP when activated
S1 VCC VCAP CTRL 0 SW_MODEL

* Control signal for the button press simulation
* Press button at T=0.5s, hold for 0.5s, then release to allow discharge
V_S1_ACT CTRL 0 PULSE(0 5 0.5 1m 1m 0.5 20)

* C1: 470 µF electrolytic capacitor
C1 VCAP 0 470u

* R1: 10 kΩ resistor (Discharge path to Base)
R1 VCAP BASE 10k

* --- Transistor Switch ---
* Q1: 2N2222 NPN transistor
* Connections: Collector=COL, Base=BASE, Emitter=0(GND)
Q1 COL BASE 0 2N2222MOD

* --- Output Load (LED) ---
* R2: 470 Ω resistor
R2 VCC LED_A 470

* D1: Red LED
* Connections: Anode=LED_A, Cathode=COL
D1 LED_A COL DLED

* --- Models ---
* Switch Model: Threshold 2.5V, Low On-Resistance
.model SW_MODEL SW(Vt=2.5 Ron=0.1 Roff=100Meg)

* NPN Transistor Model (Generic 2N2222)
.model 2N2222MOD NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=46.91E-9 TF=411.1E-12 ITF=0.6 VTF=1.7 XTF=3 RB=10 RC=0.3 RE=0.2)

* LED Model (Red LED approx)
.model DLED D(IS=1u N=2 RS=10 BV=5 IBV=10u)

* --- Analysis Commands ---
* Transient analysis for 10 seconds to observe the long RC discharge (Tau ~ 4.7s)
.tran 10m 10s

* Output voltage of Capacitor, Base, Collector, and LED Anode
.print tran V(VCAP) V(BASE) V(COL) V(LED_A)

.op
.end

Simulation Results (Transient Analysis)

Show raw data table (2110 rows)

Index   time            v(vcap)         v(base)         v(col)
0	0.000000e+00	5.504285e-01	5.495835e-01	8.838023e+00
1	1.000000e-04	5.504285e-01	5.495836e-01	8.838088e+00
2	2.000000e-04	5.504285e-01	5.495835e-01	8.838088e+00
3	4.000000e-04	5.504285e-01	5.495835e-01	8.838088e+00
4	8.000000e-04	5.504285e-01	5.495835e-01	8.838088e+00
5	1.600000e-03	5.504285e-01	5.495835e-01	8.838088e+00
6	3.200000e-03	5.504285e-01	5.495835e-01	8.838088e+00
7	6.400000e-03	5.504285e-01	5.495835e-01	8.838088e+00
8	1.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
9	2.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
10	3.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
11	4.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
12	5.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
13	6.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
14	7.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
15	8.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
16	9.280000e-02	5.504285e-01	5.495835e-01	8.838088e+00
17	1.028000e-01	5.504285e-01	5.495835e-01	8.838088e+00
18	1.128000e-01	5.504285e-01	5.495835e-01	8.838088e+00
19	1.228000e-01	5.504285e-01	5.495835e-01	8.838088e+00
20	1.328000e-01	5.504285e-01	5.495835e-01	8.838088e+00
21	1.428000e-01	5.504285e-01	5.495835e-01	8.838088e+00
22	1.528000e-01	5.504285e-01	5.495835e-01	8.838088e+00
23	1.628000e-01	5.504285e-01	5.495835e-01	8.838088e+00
... (2086 more rows) ...

Common mistakes and how to avoid them

1. Reversed Capacitor Polarity: Electrolytic capacitors can explode or fail if connected backwards. Ensure the negative stripe on C1 connects to 0 (GND).
2. Incorrect Transistor Pinout: Confusing the Collector and Emitter prevents switching. Verify the 2N2222 datasheet; usually, the tab or flat side indicates the pin orientation.
3. Capacitor Value Too Small: Using a small capacitor (e.g., 100 nF) results in a delay too short for the human eye to perceive. Use at least 100 µF for visible results.

Troubleshooting

• Symptom: LED never turns ON.
  • Cause: LED installed backwards or transistor broken.
  • Fix: Check D1 orientation (Anode to resistor, Cathode to Collector) and verify Q1 connections.
• Symptom: LED turns OFF immediately upon releasing the button.
  • Cause: Capacitor is missing, disconnected, or value is too low.
  • Fix: Ensure C1 is firmly connected between VCAP and 0. Try increasing C1 to 1000 µF.
• Symptom: Transistor gets very hot.
  • Cause: Missing base resistor or short circuit at the output.
  • Fix: Ensure R1 (10 kΩ) is correctly installed between the capacitor and the base to limit base current.

Possible improvements and extensions

1. Variable Timer: Replace R1 with a 50 kΩ potentiometer in series with a 1 kΩ resistor to allow the user to adjust the delay duration.
2. Darlington Pair: Replace Q1 with a Darlington transistor (or two NPNs connected as a Darlington pair) to significantly increase input impedance, allowing for much longer delays with the same capacitor value.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic. Verify that a capacitor allows AC signals to pass while blocking DC components.

Objective and use case

You will build a passive circuit connecting a signal source with a DC offset to a load through a series capacitor. The setup demonstrates how the capacitor filters out the direct current (DC) component while allowing the alternating current (AC) signal to reach the load.

Why it is useful:
* Audio Coupling: Essential for connecting amplifier stages where different DC bias voltages exist but the audio signal must pass through unchanged.
* Sensor Conditioning: Removes constant voltage offsets from sensors (like piezoelectric elements) to focus only on dynamic changes.
* Protection: Prevents dangerous DC currents from flowing into sensitive loads like headphones or speakers.

Expected outcome:
* Input Signal: A sine wave oscillating strictly above 0 V (e.g., between +2 V and +4 V).
* Output Signal: The same sine wave centered around 0 V (oscillating between -1 V and +1 V).
* DC Measurement: The input node measures a steady DC voltage (e.g., +3 V), while the output node measures 0 V DC.

Target audience and level:
Students and hobbyists learning about passive filters and AC coupling.

Materials

• V1: Function Generator, function: provides 1 kHz sine wave (2 Vpp) with +3 V DC offset.
• C1: 10 µF electrolytic capacitor, function: DC blocking coupling capacitor.
• R1: 10 kΩ resistor, function: output load to ground.
• Measurement Tools: Oscilloscope (DC coupling mode) and Multimeter.

Wiring guide

This circuit uses three specific nodes: VIN (source), VOUT (load), and 0 (GND).

• V1 (Source): Connect the positive terminal to node VIN and the negative/ground terminal to node 0.
• C1 (Capacitor): Connect the positive terminal (anode) to node VIN and the negative terminal (cathode) to node VOUT.
• R1 (Resistor): Connect one leg to node VOUT and the other leg to node 0.

Conceptual block diagram

Schematic

[ INPUT SOURCE ]                 [ PROCESSING ]                   [ OUTPUT LOAD ]

    [ V1: Function Gen ]             [ C1: Capacitor ]                 [ R1: Resistor ]
    ( 1kHz Sine, 2Vpp  ) --(VIN)--> +[     10 µF     ]- --(VOUT)--> [     10 kΩ      ] --> GND
    (   +3 V DC Offset  )      |      ( Electrolytic  )       |
                              |                              |
                              v                              v
                       [ Measurement ]                [ Measurement ]
                       (Scope/Multi)                  (Scope/Multi)

Measurements and tests

To validate the circuit, ensure your oscilloscope is set to DC Coupling on the input channel. If set to AC Coupling, the scope itself will block the DC, hiding the effect of the external capacitor.

1. Configure Source (V1): Set the function generator to a Sine wave, Frequency = 1 kHz, Amplitude = 2 V peak-to-peak, Offset = +3 V.
2. Measure Input (VIN):
   • Connect the scope probe to VIN.
   • Observation: The signal should oscillate between +2 V and +4 V. The center line is at +3 V.
   • DC Meter: Should read approximately +3 V.
3. Measure Output (VOUT):
   • Connect the scope probe to VOUT.
   • Observation: The signal should oscillate between -1 V and +1 V. The center line is at 0 V.
   • DC Meter: Should read approximately 0 V.
4. Verification: Confirm that the shape and amplitude (2 Vpp) of the AC wave remain largely unchanged, but the vertical position has shifted down by 3 volts.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: DC blocking

* --- Components ---

* V1: Function Generator
* Specs: 1 kHz sine wave, 2 Vpp (Amplitude = 1V), +3 V DC offset
* Connection: Positive to VIN, Negative to 0 (GND)
V1 VIN 0 SIN(3 1 1k)

* C1: 10 uF electrolytic capacitor
* Function: DC blocking coupling capacitor
* Connection: Positive (VIN) to Negative (VOUT)
C1 VIN VOUT 10u

* R1: 10 kOhm resistor
* Function: Output load to ground
* Connection: VOUT to 0 (GND)
R1 VOUT 0 10k

* --- Simulation Commands ---
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: DC blocking

* --- Components ---

* V1: Function Generator
* Specs: 1 kHz sine wave, 2 Vpp (Amplitude = 1V), +3 V DC offset
* Connection: Positive to VIN, Negative to 0 (GND)
V1 VIN 0 SIN(3 1 1k)

* C1: 10 uF electrolytic capacitor
* Function: DC blocking coupling capacitor
* Connection: Positive (VIN) to Negative (VOUT)
C1 VIN VOUT 10u

* R1: 10 kOhm resistor
* Function: Output load to ground
* Connection: VOUT to 0 (GND)
R1 VOUT 0 10k

* --- Simulation Commands ---

* Operating point analysis
.op

* Transient analysis
* Frequency is 1kHz (Period = 1ms). Simulate 5ms to see 5 cycles.
.tran 10u 5m

* --- Output Directives ---
* Print input and output voltages for logging
.print tran V(VIN) V(VOUT)

.end

Simulation Results (Transient Analysis)

Show raw data table (508 rows)

Index   time            v(vin)          v(vout)
0	0.000000e+00	3.000000e+00	0.000000e+00
1	1.000000e-07	3.000628e+00	6.283179e-04
2	2.000000e-07	3.001257e+00	1.256635e-03
3	4.000000e-07	3.002513e+00	2.513266e-03
4	8.000000e-07	3.005027e+00	5.026506e-03
5	1.600000e-06	3.010053e+00	1.005285e-02
6	3.200000e-06	3.020105e+00	2.010452e-02
7	6.400000e-06	3.040202e+00	4.020026e-02
8	1.280000e-05	3.080338e+00	8.033296e-02
9	2.280000e-05	3.142767e+00	1.427508e-01
10	3.280000e-05	3.204633e+00	2.045991e-01
11	4.280000e-05	3.265691e+00	2.656336e-01
12	5.280000e-05	3.325700e+00	3.256134e-01
13	6.280000e-05	3.384424e+00	3.843020e-01
14	7.280000e-05	3.441631e+00	4.414676e-01
15	8.280000e-05	3.497095e+00	4.968847e-01
16	9.280000e-05	3.550597e+00	5.503345e-01
17	1.028000e-04	3.601927e+00	6.016061e-01
18	1.128000e-04	3.650880e+00	6.504972e-01
19	1.228000e-04	3.697265e+00	6.968148e-01
20	1.328000e-04	3.740898e+00	7.403761e-01
21	1.428000e-04	3.781608e+00	7.810093e-01
22	1.528000e-04	3.819232e+00	8.185538e-01
23	1.628000e-04	3.853624e+00	8.528617e-01
... (484 more rows) ...

Common mistakes and how to avoid them

1. Using AC Coupling on the Oscilloscope: This is the most frequent error. It makes the input look exactly like the output because the scope blocks the DC internally. Solution: Always verify the scope channel is set to «DC Coupling».
2. Reversing Capacitor Polarity: Using a polarized electrolytic capacitor backwards can cause it to leak current or fail. Solution: Ensure the positive side of C1 faces the higher DC potential (the source VIN in this case).
3. Load Resistance (R1) too Low: If R1 is very small, it creates a High-Pass filter with a cutoff frequency above 1 kHz, attenuating the AC signal. Solution: Ensure R1 × C1 is large enough so fcutoff = (1 / (2\pi R C)) is well below the signal frequency.

Troubleshooting

• Symptom: VOUT shows a DC voltage significantly higher than 0 V.
  • Cause: The capacitor C1 is leaky or damaged (acting like a resistor).
  • Fix: Replace C1 with a new capacitor.
• Symptom: No signal at VOUT (0 V AC and 0 V DC).
  • Cause: Open circuit connection or defective breadboard track.
  • Fix: Check continuity between C1 cathode and R1.
• Symptom: The AC signal at VOUT is much smaller than at VIN.
  • Cause: The source frequency is too low for the selected C1/R1 combination (High-Pass filtering effect).
  • Fix: Increase the frequency of V1 or increase the value of C1.

Possible improvements and extensions

1. Frequency Sweep: Lower the frequency of V1 from 1 kHz down to 1 Hz to observe how the capacitor eventually blocks the AC signal as well (High-Pass filter demonstration).
2. Variable Load: Replace R1 with a potentiometer to see how changing load impedance affects the low-frequency cutoff point.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are