Objective and use case

In this practical case, you will build a digital equality detector using a 74HC7266 XNOR logic gate, mechanical switches, and an LED indicator.

This circuit concept is highly useful in real-world digital electronics:
* Digital locks: Comparing an entered bit to a stored security key bit.
* Error detection: Verifying if two redundant sensor signals output the exact same digital state.
* Data routing: Confirming destination addresses in memory mapping or basic communication protocols.
* Automation: Checking if a machine’s actual state matches the commanded state.

Expected outcome:
* The output LED turns ON when both inputs are perfectly equal (both LOW or both HIGH).
* The output LED remains OFF when the inputs differ (one is HIGH and the other is LOW).
* Logic LOW is measured as approximately 0 V, and logic HIGH as approximately 5 V.

Target audience: Beginners learning fundamental digital logic gates and Boolean algebra.

Materials

• V1: 5 V DC power supply, function: circuit power
• SW1: SPST switch, function: input A control
• SW2: SPST switch, function: input B control
• R1: 10 kΩ resistor, function: pull-down for node VA
• R2: 10 kΩ resistor, function: pull-down for node VB
• R3: 330 Ω resistor, function: LED current limiting
• D1: red LED, function: equality indicator
• U1: 74HC7266 IC, function: XNOR logic gate

Wiring guide

• V1: connects between node VCC and node 0 (GND).
• SW1: connects between node VCC and node VA.
• R1: connects between node VA and node 0.
• SW2: connects between node VCC and node VB.
• R2: connects between node VB and node 0.
• U1: VCC pin (14) connects to node VCC.
• U1: GND pin (7) connects to node 0.
• U1: Pin 1 (1 A) connects to node VA.
• U1: Pin 2 (1B) connects to node VB.
• U1: Pin 3 (1Y) connects to node VOUT.
• U1: Pins 5, 6, 8, 9, 12, and 13 connect directly to node 0.
• R3: connects between node VOUT and node D1_ANODE.
• D1: anode connects to node D1_ANODE, cathode connects to node 0.

Conceptual block diagram

Measurements and tests

1. Initial Power Verification: Before actuating any switches, power on the circuit. Measure the voltage between VCC and 0 to ensure it is 5 V.
2. Input State Testing: Set your multimeter to DC Voltage. Measure nodes VA and VB with respect to node 0. Toggle SW1 and SW2 to verify that an open switch yields ~0 V (thanks to the pull-down resistors) and a closed switch yields ~5 V.
3. XNOR Logic Verification: Measure the voltage at VOUT with respect to node 0 for all four combinations of SW1 and SW2.
4. Equality Confirmation: Ensure VOUT is approximately 5 V and the LED is illuminated ONLY when VA and VB are perfectly matched (0 V & 0 V, or 5 V & 5 V).

Common mistakes and how to avoid them

• Confusing 74HC7266 with 74HC266: The 74HC266 has open-drain outputs, which means it cannot source current to turn on an LED without an external pull-up resistor. Ensure you use the 74HC7266 (push-pull) or add a pull-up resistor if using the 74HC266.
• Leaving CMOS inputs floating: Forgetting to ground the unused inputs of the 74HC7266 can cause internal high-frequency oscillation, drawing excessive current and potentially damaging the IC. Always tie unused inputs to GND or VCC.
• Omitting pull-down resistors: If R1 and R2 are forgotten, the inputs will float unpredictably when the switches are open, causing the LED to flicker randomly.

Troubleshooting

• Symptom: LED flickers or behaves erratically when switches are open.
  • Cause: Node VA or VB is floating.
  • Fix: Verify that R1 and R2 are securely connected between the switch inputs and ground.
• Symptom: LED never turns on.
  • Cause: LED D1 is inserted backwards (reversed polarity) or R3 is too large (e.g., 100 kΩ instead of 330 Ω).
  • Fix: Check the orientation of D1 (longer leg to D1_ANODE) and verify the value of R3.
• Symptom: LED is always ON regardless of switch positions.
  • Cause: Output pin (3) is shorted to VCC, or both switches are permanently shorted to the same logic level.
  • Fix: Inspect the wiring around VOUT, VA, and VB. Ensure the switches physically break the connection to VCC when toggled off.

Objective and use case

You will build a digital logic comparator circuit using a 74LS86 XOR (Exclusive-OR) gate to monitor two redundant switches acting as system sensors. The circuit evaluates the inputs continuously and activates a visual LED alarm only when the two sensors report conflicting states, indicating a potential sensor failure.

This circuit is highly useful in practical scenarios such as:
* Industrial automation, for monitoring dual-redundant safety limit switches on heavy machinery.
* Aerospace and aviation control systems, to detect disagreements between redundant flight sensors.
* Basic logic fault-detection training for maintenance and electronics technicians.

Expected outcome:
* A high output logic level (VOUT > 2.4 V) triggering the LED when the sensor states do not match.
* A low output logic level (VOUT < 0.4 V) keeping the LED turned off when both sensors agree (both HIGH or both LOW).
* A clear, immediate visual indication of logic discrepancies to the operator.

Target audience: Basic-level students learning digital logic gates, boolean algebra, and redundancy systems.

Materials

• V1: 5 V DC supply, function: primary power source
• SW1: SPST switch, function: redundant sensor A simulator
• SW2: SPST switch, function: redundant sensor B simulator
• R1: 10 kΩ resistor, function: pull-down for VA
• R2: 10 kΩ resistor, function: pull-down for VB
• R3: 330 Ω resistor, function: LED current limiting
• U1: 74LS86 Quad 2-Input Exclusive-OR Gate, function: fault detection logic
• D1: red LED, function: visual fault alarm indicator

Wiring guide

• V1: connects between VCC and 0.
• SW1: connects between VCC and VA.
• SW2: connects between VCC and VB.
• R1: connects between VA and 0.
• R2: connects between VB and 0.
• U1: connects Pin 14 to VCC, Pin 7 to 0, Pin 1 to VA, Pin 2 to VB, and Pin 3 to VOUT.
• R3: connects between VOUT and VLED.
• D1: connects its anode to VLED and its cathode to 0.

Conceptual block diagram

Measurements and tests

1. System Normal (Low): Leave both SW1 and SW2 open. Measure the voltage at nodes VA and VB with a multimeter; both should read 0 V. Measure VOUT; it should be < 0.4 V. The LED D1 must be OFF.
2. Sensor A Fault: Close SW1 (applying 5 V to VA) while leaving SW2 open (0 V at VB). Measure VOUT; it should read > 2.4 V. The LED D1 must turn ON.
3. Sensor B Fault: Open SW1 (0 V at VA) and close SW2 (applying 5 V to VB). Measure VOUT; it should read > 2.4 V. The LED D1 must turn ON.
4. System Normal (High): Close both SW1 and SW2 so that both VA and VB read 5 V. Measure VOUT; it should drop back to < 0.4 V. The LED D1 must be OFF.

Common mistakes and how to avoid them

• Forgetting pull-down resistors: Connecting the switches directly to the IC without R1 and R2 leaves the inputs floating when the switches are open, causing unpredictable behavior and false alarms. Always use pull-down resistors.
• LED polarity reversal: Putting the LED in backward (cathode to VLED, anode to 0) will prevent it from lighting up even when a fault is detected. Verify the flat edge or shorter leg is connected to ground.
• Leaving unused inputs floating: The 74LS86 contains four XOR gates. Leaving the inputs of the unused gates disconnected can cause internal oscillation and increase power consumption. Tie unused inputs to ground (0).

Troubleshooting

• Symptom: The LED never turns on under any switch combination.
  • Cause: Faulty LED, backward LED polarity, broken R3 connection, or missing VCC/GND to the chip.
  • Fix: Check D1 orientation. Verify 5 V at Pin 14 and 0 V at Pin 7 of U1.
• Symptom: The LED is always on, even when both switches are open or both are closed.
  • Cause: One of the inputs is floating (missing pull-down resistor R1 or R2), or a switch is wired incorrectly.
  • Fix: Check continuity on R1 and R2 to ground. Verify the voltages at VA and VB correspond strictly to the truth table.
• Symptom: The LED lights up correctly but is very dim.
  • Cause: The 74LS series has weak current sourcing capabilities compared to modern CMOS chips, or the value of R3 is too high.
  • Fix: Reduce R3 slightly (e.g., to 220 Ω), or see the extensions below for a better way to drive the LED.

Objective and use case

We will build a simple security alarm simulator using a 74HC02 NOR gate. In this system, the alarm (an LED) will illuminate only when all connected monitoring sensors (represented by switches) indicate a safe, undisturbed state (Logic 0).

Why it is useful:
* Demonstrates negative logic applications where the absence of inputs is required to trigger an action.
* Provides practical experience with CMOS logic gate behavior and logic-level thresholds.
* Mimics real-world safety interlocks, such as machine guards, where multiple conditions must be false for the system to operate.
* Introduces the essential use of pull-down resistors to ensure stable, predictable logic states.

Expected outcome:
* The output LED will illuminate only when both sensor switches are open (Logic 0, 0 V).
* The output LED will turn off immediately if either or both switches are closed (Logic 1, 5 V).
* Input voltages will measure close to 0 V when switches are open, and near 5 V when closed.
* The output voltage will strictly follow the theoretical truth table of a NOR logic gate.

Target audience: Beginners in digital electronics learning fundamental logic gates and basic control circuits.

Materials

• V1: 5 V DC power supply
• U1: 74HC02 Quad 2-Input NOR Gate
• SW1: SPST switch, function: sensor A input
• SW2: SPST switch, function: sensor B input
• R1: 10 kΩ resistor, function: pull-down for VA
• R2: 10 kΩ resistor, function: pull-down for VB
• R3: 330 Ω resistor, function: LED current limiting
• D1: Red LED, function: alarm active indicator

Wiring guide

• V1: Connects between VCC and 0.
• U1 (Pin 14): Connects to VCC.
• U1 (Pin 7): Connects to 0.
• SW1: Connects between VCC and VA.
• SW2: Connects between VCC and VB.
• R1: Connects between VA and 0.
• R2: Connects between VB and 0.
• U1 (Pin 2): Connects to VA.
• U1 (Pin 3): Connects to VB.
• U1 (Pin 1): Connects to VOUT.
• R3: Connects between VOUT and D1_A.
• D1: Connects between D1_A (anode) and 0 (cathode).

Conceptual block diagram

Measurements and tests

1. Power verification: With the power supply connected, use a multimeter to measure the voltage between nodes VCC and 0. Ensure it is strictly 5 V.
2. Idle state test (0, 0): Leave both SW1 and SW2 open. Measure nodes VA and VB with respect to ground; they should be 0 V. Measure VOUT; it should read near 5 V, and the LED should be ON.
3. Single sensor test (1, 0 / 0, 1): Close SW1 (leaving SW2 open). Measure VA; it should be 5 V. Measure VOUT; it should immediately drop to 0 V, and the LED should turn OFF. Repeat by opening SW1 and closing SW2.
4. Dual sensor test (1, 1): Close both SW1 and SW2. Confirm both VA and VB measure 5 V. Measure VOUT to verify it remains 0 V (LED OFF).

Common mistakes and how to avoid them

1. Misinterpreting the 74HC02 pinout: Unlike standard AND/OR gates (where pins 1 and 2 are inputs and 3 is the output), the 74HC02 has its output on Pin 1, and inputs on Pins 2 and 3. Wiring it like a 74HC08 will result in short circuits and component failure.
2. Floating inputs (Missing pull-down resistors): Omitting R1 or R2 leaves the CMOS inputs floating when the switches are open. This causes the output to oscillate or randomly toggle based on environmental electromagnetic noise. Always ensure your inputs have a defined path to ground.
3. Reversing LED polarity: Connecting the LED backwards (anode to ground) will prevent it from lighting up, even if the gate outputs a correct 5 V Logic 1 state.

Troubleshooting

• Symptom: LED is always OFF, even when both switches are open.
• Cause: Floating inputs acting as logic HIGH, or an incorrect wiring to Pin 1 (Output).
• Fix: Verify R1 and R2 are properly connected between the input nodes (VA, VB) and ground (0). Double-check that the LED is connected to Pin 1, not Pin 3.
• Symptom: IC becomes excessively hot to the touch.
• Cause: Power pins (VCC and 0) are reversed, or an output pin is directly shorted to ground or VCC.
• Fix: Instantly disconnect power. Verify Pin 14 goes strictly to VCC and Pin 7 goes strictly to 0.
• Symptom: The alarm triggers (LED turns ON) when any switch is closed, rather than when they are open.
• Cause: Using an OR gate (74HC32) instead of a NOR gate (74HC02), or using pull-up resistors instead of pull-downs.
• Fix: Check the markings on the IC package to ensure it is a 74HC02, and verify R1 and R2 are wired to ground (0).

Objective and use case

You will construct a binary ripple counter circuit utilizing the 74HC393 integrated circuit to process a high-speed input clock. By dividing the frequency by factors of 2, 4, 8, and 16, a physical jumper acts as a selector to route a specific down-scaled output to a visual LED indicator.

This topology is highly useful in practical electronics for several reasons:
* Generating precise, slow timebases for digital clocks from high-frequency crystal oscillators.
* Stepping down high-frequency PWM signals for specific motor control applications.
* Creating multiple synchronized sub-harmonic frequencies for audio synthesizers.
* Converting a rapidly blinking indicator into a manageable, visually observable pulse.

Expected outcomes:
* The CLK input will receive a constant square wave.
* The outputs QA, QB, QC, and QD will cleanly toggle at exactly 1/2, 1/4, 1/8, and 1/16 of the clock frequency, respectively.
* Selecting different outputs via the jumper will visibly change the LED blink rate without altering the main clock source.

Target audience and level: Electronics students and hobbyists wanting hands-on experience with asynchronous logic and frequency scaling.

Materials

• V1: 5 V DC power supply, function: logic power source
• VCLK: 5 V square wave clock source (e.g., function generator), function: input clock
• U1: 74HC393 Dual 4-Bit Binary Ripple Counter, function: frequency divider
• J1: 4-pin header block with jumper shunt, function: output selector
• R1: 330 Ω resistor, function: LED current limiting
• D1: Red LED, function: selected output state indicator

Wiring guide

• V1: connects between node VCC and node 0.
• VCLK: connects between node CLK and node 0.
• U1 Pin 14 (VCC): connects to node VCC.
• U1 Pin 7 (GND): connects to node 0.
• U1 Pin 1 (1CP): connects to node CLK.
• U1 Pin 2 (1MR): connects to node 0.
• U1 Pin 3 (1Q0): connects to node QA and selector terminal 1 of J1.
• U1 Pin 4 (1Q1): connects to node QB and selector terminal 2 of J1.
• U1 Pin 5 (1Q2): connects to node QC and selector terminal 3 of J1.
• U1 Pin 6 (1Q3): connects to node QD and selector terminal 4 of J1.
• J1 common terminal: connects to node VOUT.
• R1: connects between node VOUT and node N_LED.
• D1: connects between node N_LED (Anode) and node 0 (Cathode).

Conceptual block diagram

Measurements and tests

1. Clock Setup: Configure VCLK to output a 16 Hz square wave (0 to 5 V). Verify this signal by connecting an oscilloscope channel to node CLK.
2. Divide-by-2 Validation: Place the jumper J1 to connect node QA to VOUT. The LED D1 should blink at 8 Hz. Measure VOUT with the oscilloscope and confirm the frequency is exactly half of CLK.
3. Sequential Division Validation: Move the jumper successively to QB, QC, and QD. Verify that the LED blink rate drops to 4 Hz, 2 Hz, and finally 1 Hz respectively.
4. Ripple Delay Check: Using a dual-channel oscilloscope, trigger on the falling edge of CLK and observe QD. Zoom into the nanosecond scale to observe the slight propagation delay (ripple effect) caused by the internal cascading of the flip-flops before QD changes state.

Common mistakes and how to avoid them

• Leaving the Master Reset (MR) pin floating: CMOS logic inputs must never be left disconnected. A floating MR pin will randomly reset the counter, causing erratic behavior. Always tie it directly to Ground (0) if not used.
• Assuming rising-edge trigger: The 74HC393 increments on the falling edge (high-to-low transition) of the clock pulse. Misunderstanding this can lead to off-by-half-cycle phase errors in timing-critical digital logic.
• Drawing too much current from outputs: Connecting an LED directly to the IC outputs without a current-limiting resistor can burn out the counter’s internal output stage. Always ensure R1 is in place.

Troubleshooting

• Symptom: Counter does not advance, LED stays off or statically on.
  • Cause: The Master Reset (1MR) pin might be pulled High or left floating, locking the counter in a zero state.
  • Fix: Ensure Pin 2 is firmly connected to 0 (GND).
• Symptom: Output frequencies are erratic or much faster than expected.
  • Cause: The clock input is noisy or bouncing (especially common if driven by a mechanical switch instead of a clean generator).
  • Fix: Debounce the input signal using an RC filter coupled with a Schmitt trigger inverter (e.g., 74HC14) before feeding it to CLK.
• Symptom: LED appears constantly dim regardless of jumper position.
  • Cause: The clock frequency is set too high (e.g., 1 kHz or more). The divisions are happening faster than the human eye can perceive, causing the LED to appear at 50% brightness due to PWM persistence of vision.
  • Fix: Lower VCLK frequency to below 20 Hz for visual observation.

Objective and use case

In this practical case, you will build a delay-on timer using the versatile NE555 integrated circuit. Upon applying 5 V power, an RC network dictates a waiting period before the timer’s output activates and turns on a «READY» LED.

This timer topology is highly useful in real-world applications:
* Audio amplifiers: Delaying speaker connection until internal voltages stabilize to prevent loud popping noises.
* Power supply sequencing: Ensuring primary rails are fully powered before activating secondary logic circuits.
* Microcontroller resets: Holding a reset line active for a brief period during startup to guarantee clean initialization.

Expected outcome:
* At power-on ($t=0$), the LED will remain OFF.
* The voltage at the timing node (VCAP) will exponentially decay from 5 V down to 1.66 V (which is 1/3 VCC).
* Once VCAP crosses the 1.66 V threshold, the NE555 output (VOUT) will snap from 0 V to 5 V (HIGH), illuminating the LED.
* The delay time will be approximately 5.1 seconds.

Target audience and level: Beginners learning analog-digital timing and RC time constants.

Materials

• U1: NE555 timer IC, function: timing controller
• R1: 100 kΩ resistor, function: timing resistor
• C1: 47 µF electrolytic capacitor, function: timing capacitor
• R2: 330 Ω resistor, function: LED current limiting
• C2: 10 nF ceramic capacitor, function: control voltage stabilization
• D1: green LED, function: READY indicator
• V1: 5 V DC supply

Wiring guide

• V1: connects between VCC (+5 V) and 0 (GND).
• C1: connects between VCC (positive leg) and VCAP (negative leg).
• R1: connects between VCAP and 0.
• U1 connections:
• Pin 1 (GND) connects to 0.
• Pin 2 (TRIG) connects to VCAP.
• Pin 3 (OUT) connects to VOUT.
• Pin 4 (RESET) connects to VCC.
• Pin 5 (CTRL) connects to VCTRL.
• Pin 6 (THR) connects to VCAP.
• Pin 8 (VCC) connects to VCC.
• C2: connects between VCTRL and 0.
• R2: connects between VOUT and VLED.
• D1: connects between VLED (anode) and 0 (cathode).

Conceptual block diagram

Measurements and tests

To validate the transient behavior of this delay-on timer, perform the following steps:

1. Initial State Verification: Ensure power is completely disconnected. Use a multimeter or oscilloscope to confirm that VCAP and VOUT are at 0 V.
2. Apply Power: Turn on the 5 V supply (V1). Start a stopwatch immediately. Verify that VOUT is initially ~0 V and the LED is OFF.
3. Transient Validation of VCAP: Measure the voltage at node VCAP with respect to ground (0). Because the capacitor C1 is tied to VCC, it acts as a short circuit at $t=0$, pulling VCAP to 5 V. As C1 charges through R1, observe VCAP exponentially decaying toward 0 V.
4. Trigger Threshold: Monitor VCAP as it drops. Exactly as it crosses 1.66 V (1/3 of VCC), verify that VOUT instantly jumps to 5 V and the READY LED illuminates.
5. Timing Calculation: Verify the elapsed time. The theoretical delay for this configuration is calculated as T ≈ 1.1 × R × C. With 100 kΩ and 47 µF, T ≈ 5.17 seconds. Check that your measured time aligns with this estimate.

Common mistakes and how to avoid them

• Reversing the R and C positions: Connecting R1 to VCC and C1 to 0 creates a delay-off timer rather than a delay-on timer. Ensure C1 connects strictly to VCC and R1 to 0 to achieve the desired power-on delay.
• Leaving the RESET pin floating: An unconnected Pin 4 can pick up ambient electrical noise, causing the timer to reset randomly and preventing the LED from turning on. Always tie Pin 4 directly to VCC.
• Electrolytic capacitor reverse polarity: In this specific configuration, the positive terminal of C1 must go to VCC and the negative terminal to VCAP. Reversing this will cause high leakage current, drastically altering the delay time or destroying the capacitor.

Troubleshooting

• Symptom: LED turns on instantly without delay.
  • Cause: C1 is internally shorted, or the R1/C1 components were swapped.
  • Fix: Double-check the wiring of nodes VCAP, VCC, and 0. Replace C1 if a short is suspected.
• Symptom: LED never turns on.
  • Cause: VCAP never drops below 1.66 V. This usually happens if C1 has excessive leakage current, essentially forming a voltage divider with R1. It can also occur if the LED (D1) is inserted backwards.
  • Fix: Ensure LED polarity is correct (anode to R2, cathode to 0). Use a higher quality capacitor or decrease R1 (while correspondingly increasing C1 to maintain the same time constant) to overcome leakage.
• Symptom: Delay time is significantly shorter or longer than 5 seconds.
  • Cause: Standard electrolytic capacitors have wide tolerances (often \pm 20\% or worse).
  • Fix: This is normal behavior for basic components. For precision timing, swap the electrolytic capacitor for a tantalum or film capacitor with a tighter tolerance.

Objective and use case

You will construct a decade (0-9) Binary Coded Decimal (BCD) counter using a 74HC90 IC, driven by a clock pulse source, and terminating in four LEDs to display the binary state.

This circuit is highly useful in real-world applications for:
* Building fundamental digital clock circuits (seconds and minutes counters).
* Event counting systems on manufacturing lines.
* Understanding logic state machines and frequency dividers (divide-by-10).
* Creating foundational timing circuits without the need for microcontrollers.

Expected outcome:
* The circuit will automatically count from 0000 (decimal 0) to 1001 (decimal 9) in binary.
* A transient validation will show the CLK signal alongside the state of QA, QB, QC, and QD.
* Pressing the manual reset button will immediately pull the RST node HIGH and force the outputs to 0000.
* The LEDs will visually blink according to their respective binary significance (QA toggling fastest, QD toggling slowest).

Target audience and level: Intermediate electronics students learning sequential logic and counters.

Materials

• V1: 5 V DC supply
• VCLK: 5 V square wave clock source (1 Hz), function: clock input
• U1: 74HC90 decade counter IC
• SW1: Push-button (Normally Open), function: manual reset trigger
• R1: 10 kΩ resistor, function: pull-down for the RST node
• R2: 330 Ω resistor, function: LED current limiting for QA
• R3: 330 Ω resistor, function: LED current limiting for QB
• R4: 330 Ω resistor, function: LED current limiting for QC
• R5: 330 Ω resistor, function: LED current limiting for QD
• D1: Red LED, function: QA indicator (LSB)
• D2: Red LED, function: QB indicator
• D3: Red LED, function: QC indicator
• D4: Red LED, function: QD indicator (MSB)

Conceptual block diagram

Measurements and tests

• Clock validation: Monitor the CLK node on an oscilloscope or transient plot to verify a consistent square wave.
• Counting sequence: Plot QA, QB, QC, and QD simultaneously. Observe that QA toggles on every falling edge of CLK, and that the binary state progresses correctly from 0000 to 1001.
• BCD Wrap-around: Watch the transition after 1001 (decimal 9). The very next clock pulse should automatically return all outputs (QA–QD) back to 0000 (decimal 0) instead of proceeding to 1010 (decimal 10).
• Manual Reset: While the counter is at any non-zero state (e.g., 0101), actuate SW1. Observe that the RST node spikes to 5 V, forcing QA, QB, QC, and QD to 0000 immediately, ignoring the CLK signal until the button is released.

Common mistakes and how to avoid them

• Forgetting to connect QA to CKB: The 74HC90 is internally split into a divide-by-2 and a divide-by-5 section. If you do not bridge pin 12 (QA) to pin 1 (CKB), the IC will only count from 0 to 1 and stop, or will not generate the proper BCD sequence.
• Leaving reset pins floating: CMOS logic inputs (like the 74HC series) must never be left disconnected. Leaving MS1, MS2, or the MR pins floating will cause the counter to randomly reset due to ambient electrical noise. Ensure they are tied firmly to 0 or managed via a pull-down resistor.
• Swapping the output bits: Reading the LEDs in the wrong order is very common. Always remember that QA is the Least Significant Bit (LSB, toggles fastest) and QD is the Most Significant Bit (MSB, toggles slowest).

Troubleshooting

• Symptom: All LEDs remain entirely off, and the counter never advances.
  • Cause: The Master Reset (MR1 and MR2) or Master Set (MS1 and MS2) pins might be receiving a logic HIGH.
  • Fix: Check that SW1 is not stuck closed, ensure R1 (pull-down) is properly connected to ground, and verify MS1/MS2 are wired directly to 0.
• Symptom: The counter counts wildly or skips numbers unexpectedly.
  • Cause: The clock signal (CLK) lacks debouncing, or there is missing power supply decoupling.
  • Fix: If using a mechanical switch for a clock instead of a clean generator, add a hardware debounce circuit (RC + Schmitt trigger). Additionally, place a 100 nF capacitor directly between VCC and GND near the IC.
• Symptom: The count goes up to 5 and resets (0, 1, 2, 3, 4, 0…).
  • Cause: The clock inputs are wired backwards. The clock is entering CKB and cascading into CKA.
  • Fix: Ensure the external clock goes exclusively to CKA (pin 14) and QA bridges to CKB (pin 1).