Level: Basic — Implement a system where a motor runs only when two buttons are pressed simultaneously.

Objective and use case

In this session, you will build a safety logic circuit using a 74HC00 (Quad 2-input NAND gate) to control a DC motor. The motor will only activate when two separate pushbuttons are engaged at the same time, mimicking a «two-hand control» safety device.

Why it is useful:
* Industrial Safety: Prevents operators from reaching into a hydraulic press or cutting machine while it is moving.
* Accident Prevention: Ensures both hands are occupied on the controls during the dangerous phase of operation.
* Logic Composition: Demonstrates how to create an AND function using universal NAND gates.

Expected outcome:
* Idle State: Logic output is LOW (0 V); Motor is OFF.
* Single Press: Logic output remains LOW (0 V); Motor remains OFF.
* Dual Press: Logic output becomes HIGH (5 V); Relay engages; Motor runs.
* Current Handling: The logic gate drives a transistor, which safely switches the high-current relay coil.

Target audience and level:
Basic electronics students and hobbyists interested in digital logic applications.

Materials

• V1: 5 V DC voltage source, function: Logic and relay coil power supply.
• V2: 12 V DC voltage source, function: Motor power supply.
• U1: 74HC00, function: Quad 2-input NAND gate IC.
• S1: Pushbutton (normally open), function: Left-hand safety switch.
• S2: Pushbutton (normally open), function: Right-hand safety switch.
• R1: 10 kΩ resistor, function: Pull-down for S1.
• R2: 10 kΩ resistor, function: Pull-down for S2.
• R3: 1 kΩ resistor, function: Base current limiting for Q1.
• Q1: 2N2222 NPN transistor, function: Relay driver.
• D1: 1N4007 diode, function: Flyback protection for relay coil.
• K1: 5 V SPDT Relay, function: High-power switching interface.
• M1: 12 V DC Motor, function: Actuator (load).

Pin-out of the IC used (74HC00)

Chip: 74HC00 (Quad 2-Input NAND Gate)

Note: Pins 8 through 13 are unused and should ideally be tied to GND or VCC in a permanent installation to prevent noise, though left floating for this basic breadboard exercise.

Wiring guide

Construct the circuit following these node connections. Ensure the power supply is off while building.

Power and Inputs:
* V1 (+): Connects to node VCC.
* V1 (-) / V2 (-): Connects to node 0 (Common Ground).
* S1: Connects between VCC and node BTN_L.
* R1: Connects between node BTN_L and 0.
* S2: Connects between VCC and node BTN_R.
* R2: Connects between node BTN_R and 0.

Logic Processing (Using U1 as AND Gate):
* U1 (Pin 14): Connects to VCC.
* U1 (Pin 7): Connects to 0.
* U1 (Pin 1): Connects to node BTN_L.
* U1 (Pin 2): Connects to node BTN_R.
* U1 (Pin 3): Connects to node NAND_INTER (First stage output).
* U1 (Pin 4 & Pin 5): Both connect to node NAND_INTER (Configures Gate 2 as an inverter).
* U1 (Pin 6): Connects to node LOGIC_OUT.

Output Stage:
* R3: Connects between node LOGIC_OUT and node BASE.
* Q1 (Base): Connects to node BASE.
* Q1 (Emitter): Connects to node 0.
* Q1 (Collector): Connects to node RELAY_COIL_LO.
* K1 (Coil +): Connects to VCC.
* K1 (Coil -): Connects to node RELAY_COIL_LO.
* D1 (Anode): Connects to node RELAY_COIL_LO.
* D1 (Cathode): Connects to VCC (Parallel to coil, reverse biased).

Motor Circuit:
* V2 (+): Connects to K1 Common contact (COM).
* K1 (NO – Normally Open): Connects to node MOTOR_POS.
* M1 (+): Connects to node MOTOR_POS.
* M1 (-): Connects to node 0.

Conceptual block diagram

Schematic

+-----------------------------------------------------------------------------+
|                  DUAL SAFETY MOTOR ACTIVATION BLOCK DIAGRAM                 |
+-----------------------------------------------------------------------------+

1. INPUTS & LOGIC STAGE (5 V Domain)
   (Both buttons must be pressed to activate the output)

   V1(5 V)
     |
     +---> [ S1: Left Button ] ---+--(BTN_L)------\
                                  |                \
                                  v                 \
                               [ R1: 10k ]           +---> [ U1:A (NAND) ] --(NAND_INTER)--> [ U1:B (NOT*) ] --(LOGIC_OUT)-->
                                  |                 /       (Pins 1 & 2)                      (Pins 4 & 5)          |
                                 GND               /                                         *Wired as Inverter     |
                                                  /                                                                 |
   V1(5 V)                                        /                                                                  |
     |                                          /                                                                   |
     +---> [ S2: Right Button ] --+--(BTN_R)---/                                                                    |
                                  |                                                                                 |
                                  v                                                                                 |
                               [ R2: 10k ]                                                                          |
                                  |                                                                                 |
                                 GND                                                                                |
                                                                                                                    |
+-------------------------------------------------------------------------------------------------------------------+
|                                                                                                                   |
| 2. RELAY DRIVER STAGE (5 V Domain)                                                                                 |
|    (Low-Side Transistor Switch)                                                                                   |
|                                                                                                                   |
|    (From Logic Above)                                                                                             |
|            |                                         V1(5 V)                                                       |
|            v                                           |                                                          |
|      [ R3: 1k ]                                        |                                                          |
|            |                                           v                                                          |
|            +----------------------------------> [ Q1: Base ]                                                      |
|                                                        :                                                          |
|                                             (Controls Current Flow)                                               |
|                                                        :                                                          |
|                                      +-----------------+                                                          |
|                                      |                                                                            |
|                              [ Q1: Collector ]                                                                    |
|                                      ^                                                                            |
|                                      |                                                                            |
|                             (Node: RELAY_COIL_LO)                                                                 |
|                                      |                                                                            |
|                    +-----------------+-----------------+                                                          |
|                    |                                   |                                                          |
|           [ K1: Relay Coil ]                    [ D1: Diode ]                                                     |
|           (Control Side)                        (Protection)                                                      |
|                    |                            (Anode to Coll)                                                   |
|                    |                            (Cathode to VCC)                                                  |
|                    +-----------------+-----------------+                                                          |
|                                      ^                                                                            |
|                                      |                                                                            |
|                                    V1(5 V)                                                                         |
|                                                                                                                   |
|                              [ Q1: Emitter ]                                                                      |
|                                      |                                                                            |
|                                      v                                                                            |
|                                     GND                                                                           |
|                                                                                                                   |
+-------------------------------------------------------------------------------------------------------------------+
|                                                                                                                   |
| 3. MOTOR OUTPUT STAGE (12 V Domain)                                                                                |
|    (High Power Load)                                                                                              |
|                                                                                                                   |
|                       (Magnetic Link from K1 Coil Above)                                                          |
|                                      |                                                                            |
|                                      v                                                                            |
|    V2(12 V) ---------> [ K1: Switch (COM to NO) ] --(MOTOR_POS)--> [ M1: 12 V Motor ] ----> GND                     |
|                                                                                                                   |
+-------------------------------------------------------------------------------------------------------------------+

Truth table

We are using two NAND gates. The first combines the inputs; the second inverts the result to create an AND function.

Measurements and tests

1. Idle Check: Power on V1. Do not press any buttons. Measure the voltage at LOGIC_OUT (Pin 6). It should be ~0 V. The motor should be stopped.
2. Input Validation: Press S1 only. Measure voltage at Pin 1. It should be 5 V. Pin 2 should be 0 V. Output at Pin 6 must remain 0 V.
3. Active Test: Press and hold both S1 and S2 simultaneously.
   • Listen for the «click» of the relay K1.
   • Observe M1 spinning.
   • Measure the voltage at LOGIC_OUT; it should be close to 5 V.
4. Release Test: Release just one button. The motor must stop immediately.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Logic AND gate controlling a relay and motor

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================
* Generic NPN Transistor Model (2N2222)
.model 2N2222MOD NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)

* Generic Diode Model (1N4007)
.model D1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3 BV=1000 IBV=10m CJO=10p VJ=0.7 M=0.5 FC=0.5 TT=100n)

* Ideal Switch Model for Buttons and Relay Contact
* Vt=2.5V (Logic Threshold), Ron=0.1 Ohm, Roff=10 MegOhm
.model SW_IDEAL SW(Vt=2.5 Vh=0.1 Ron=0.1 Roff=10Meg)

* ==============================================================================
* POWER SUPPLIES
* ==============================================================================
* V1: 5V DC Supply for Logic and Relay Coil
V1 VCC 0 DC 5
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: Logic AND gate controlling a relay and motor

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================
* Generic NPN Transistor Model (2N2222)
.model 2N2222MOD NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)

* Generic Diode Model (1N4007)
.model D1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3 BV=1000 IBV=10m CJO=10p VJ=0.7 M=0.5 FC=0.5 TT=100n)

* Ideal Switch Model for Buttons and Relay Contact
* Vt=2.5V (Logic Threshold), Ron=0.1 Ohm, Roff=10 MegOhm
.model SW_IDEAL SW(Vt=2.5 Vh=0.1 Ron=0.1 Roff=10Meg)

* ==============================================================================
* POWER SUPPLIES
* ==============================================================================
* V1: 5V DC Supply for Logic and Relay Coil
V1 VCC 0 DC 5

* V2: 12V DC Supply for Motor
V2 V_MOTOR_RAIL 0 DC 12

* ==============================================================================
* INPUT STAGE (Safety Switches)
* ==============================================================================
* Simulation of User Pressing Buttons:
* We use Pulse sources (V_ACT_...) to control ideal switches (S1, S2).
* This preserves the Pull-down resistor topology.

* S1: Left Safety Switch (Pushbutton NO)
* Connects VCC to BTN_L when pressed.
* Pulse Pattern: Period 120us, Pulse 50us (Tests asynchronous press)
V_ACT_L ACT_L 0 PULSE(0 5 10u 1u 1u 50u 120u)
S1 VCC BTN_L ACT_L 0 SW_IDEAL
R1 BTN_L 0 10k

* S2: Right Safety Switch (Pushbutton NO)
* Connects VCC to BTN_R when pressed.
* Pulse Pattern: Period 100us, Pulse 50us
V_ACT_R ACT_R 0 PULSE(0 5 20u 1u 1u 50u 100u)
S2 VCC BTN_R ACT_R 0 SW_IDEAL
R2 BTN_R 0 10k

* ==============================================================================
* LOGIC STAGE (U1: 74HC00 Quad NAND)
* ==============================================================================
* Implementing logic using Behavioral Voltage Sources (B-Sources) with continuous
* sigmoid functions for convergence robustness.
* Logic High = 5V, Logic Low = 0V. Threshold ~ 2.5V.

* U1 Gate 1: Inputs BTN_L (Pin 1), BTN_R (Pin 2) -> Output NAND_INTER (Pin 3)
* Function: NAND(BTN_L, BTN_R)
B_U1_G1 NAND_INTER 0 V=5 * (1 - ( (1/(1+exp(-20*(V(BTN_L)-2.5)))) * (1/(1+exp(-20*(V(BTN_R)-2.5)))) ))

* U1 Gate 2: Inputs NAND_INTER (Pin 4, 5) -> Output LOGIC_OUT (Pin 6)
* Function: NAND(NAND_INTER, NAND_INTER) = NOT(NAND_INTER)
* Combined Function: AND(BTN_L, BTN_R)
B_U1_G2 LOGIC_OUT 0 V=5 * (1 - ( (1/(1+exp(-20*(V(NAND_INTER)-2.5)))) * (1/(1+exp(-20*(V(NAND_INTER)-2.5)))) ))

* ==============================================================================
* OUTPUT DRIVER STAGE
* ==============================================================================
* R3: Base current limiting
R3 LOGIC_OUT BASE 1k

* Q1: 2N2222 Relay Driver
* Emitter to GND, Collector to RELAY_COIL_LO
Q1 RELAY_COIL_LO BASE 0 2N2222MOD

* ==============================================================================
* RELAY STAGE (K1)
* ==============================================================================
* Relay Coil Configuration:
* Connected between VCC and RELAY_COIL_LO.
* Modeled as Inductor + Series Resistor.
L_K1 VCC K1_NODE 10m
R_K1 K1_NODE RELAY_COIL_LO 100

* D1: Flyback Diode (1N4007)
* Anode to RELAY_COIL_LO, Cathode to VCC (Reverse biased)
D1 RELAY_COIL_LO VCC D1N4007

* Relay Contact (Switch):
* Logic: Switch closes when Coil is energized.
* Coil is energized when Q1 is ON (RELAY_COIL_LO is Low).
* Control Voltage = V(VCC) - V(RELAY_COIL_LO).
* If Q1 ON: 5V - 0.2V = 4.8V (> 2.5V Threshold) -> Switch CLOSED.
* If Q1 OFF: 5V - 5V = 0V (< 2.5V Threshold) -> Switch OPEN.
B_K1_CTRL K1_CTRL 0 V = V(VCC) - V(RELAY_COIL_LO)
S_K1 V_MOTOR_RAIL MOTOR_POS K1_CTRL 0 SW_IDEAL

* ==============================================================================
* LOAD (Motor M1)
* ==============================================================================
* M1: 12V DC Motor connected between MOTOR_POS and 0
* Modeled as Resistor + Inductor
R_M1 MOTOR_POS M1_INT 20
L_M1 M1_INT 0 5m

* ==============================================================================
* ANALYSIS COMMANDS
* ==============================================================================
.op
* Transient analysis: 1us step, 500us total time
.tran 1u 500u

* Print results for batch processing
* Inputs: BTN_L, BTN_R
* Output: MOTOR_POS (Load Voltage)
* Debug: LOGIC_OUT, RELAY_COIL_LO
.print tran V(BTN_L) V(BTN_R) V(MOTOR_POS) V(LOGIC_OUT) V(RELAY_COIL_LO) I(L_M1)

.end

Simulation Results (Transient Analysis)

Analysis: The simulation confirms the AND logic behavior. The motor voltage (v(motor_pos)) only goes high (~12V) when both inputs (v(btn_l) and v(btn_r)) are high (~5V) simultaneously (e.g., around time index 60-100 and 300-340). When only one or neither is high, the motor voltage remains near zero.

Show raw data table (1202 rows)

Index   time            v(btn_l)        v(btn_r)        v(motor_pos)    v(logic_out)    v(relay_coil_lo l_m1#branch
0	0.000000e+00	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
1	1.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
2	2.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
3	4.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
4	8.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
5	1.600000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
6	3.200000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
7	6.400000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
8	1.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
9	2.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
10	3.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
11	4.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
12	5.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
13	6.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
14	7.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
15	8.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
16	9.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
17	1.000000e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
18	1.010000e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
19	1.027500e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
20	1.032344e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
21	1.040820e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
22	1.043167e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
23	1.047272e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
... (1178 more rows) ...

Common mistakes and how to avoid them

1. Floating Inputs: Forgetting R1 or R2 causes the NAND gate inputs to float, often reading as «High» due to noise. Solution: Ensure pull-down resistors are firmly connected to Ground.
2. Missing Flyback Diode: Omitting D1 creates voltage spikes when the relay turns off, which can destroy Q1 or reset the logic chip. Solution: Always place a diode across the relay coil (Cathode to positive).
3. Direct Drive: Attempting to drive the motor or relay directly from the 74HC00 output pin. Solution: Always use a transistor (Q1) to amplify the current for inductive loads like relays.

Troubleshooting

• Motor runs immediately upon power-up: Check if S1 or S2 are wired as Normally Closed instead of Normally Open, or if the transistor Q1 is shorted.
• Relay clicks but motor doesn’t run: Check the V2 power supply and the connections on the relay contacts (COM and NO).
• Logic works but gets hot: Check if VCC (Pin 14) and GND (Pin 7) are reversed. Disconnect power immediately.
• Erratic behavior: Add a 100 nF decoupling capacitor between Pin 14 and Pin 7 of the IC, close to the chip.

Possible improvements and extensions

1. Emergency Stop: Add a Normally Closed (NC) latching button in series with the relay coil or the base resistor R3 to cut power instantly regardless of logic state.
2. Visual Feedback: Add a green LED (with a 330 Ω resistor) connected to node LOGIC_OUT to indicate when the safety condition is met, even if the motor power (V2) is off.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic
Implement a logic circuit where a proposal passes only if two members vote «Yes» and a third member grants approval (no veto), using a single 74HC00 IC.

Objective and use case

In this practical case, you will build a decision-making circuit using digital logic. The system represents a committee where Member A and Member B must both vote in favor for a motion to pass, but Member C (the Chairperson) holds an «Authorization Key.» If Member C does not activate their switch (Logic Low), the vote is vetoed regardless of A and B.

• Corporate Governance: Models a board where majority support is needed but the CEO has final approval.
• Safety Interlocks: Represents a machine press where two operators must press buttons (A and B), but a Master Enable key (C) must be inserted for the machine to run.
• Security Access: Requires two distinct user keys plus a central server authorization signal.

Expected Outcome:
* Output High (LED ON): Only when Input A is High, Input B is High, AND Input C is High.
* Output Low (LED OFF): Any other combination (e.g., if A or B vote «No», or if C exerts veto by setting their input Low).
* Target Audience: Students and hobbyists learning to construct complex logic functions (3-input AND) using universal NAND gates.

Materials

• U1: 74HC00 (Quad 2-Input NAND Gate)
• SW1: 3-position DIP Switch (or three individual SPST switches), function: Inputs A, B, and C
• R1: 10 kΩ resistor, function: pull-down for Input A
• R2: 10 kΩ resistor, function: pull-down for Input B
• R3: 10 kΩ resistor, function: pull-down for Input C
• R4: 330 Ω resistor, function: LED current limiting
• D1: Red LED, function: Logic Output Indicator
• V1: 5 V DC Power Supply

Pin-out of the IC used

Chip: 74HC00 (Quad 2-input NAND)
This project utilizes all four gates inside the chip to create a 3-input AND function (Y = A · B · C).

Wiring guide

• VCC: Connect V1 positive terminal, U1 pin 14, and the common side of SW1.
• GND: Connect V1 negative terminal, U1 pin 7, R1 (bottom), R2 (bottom), R3 (bottom), and D1 (cathode).
• Input_A: Connect SW1 (Switch 1) to R1 (top) and U1 pin 1.
• Input_B: Connect SW1 (Switch 2) to R2 (top) and U1 pin 2.
• Input_C (Veto): Connect SW1 (Switch 3) to R3 (top) and U1 pin 9.
• Node_NAND1: Connect U1 pin 3 (Output 1) to U1 pin 4 and U1 pin 5 (Inputs of Gate 2).
• Node_AND_AB: Connect U1 pin 6 (Output 2) to U1 pin 10 (Input of Gate 3).
• Node_NAND_FINAL: Connect U1 pin 8 (Output 3) to U1 pin 12 and U1 pin 13 (Inputs of Gate 4).
• Vout: Connect U1 pin 11 (Final Output) to R4 (one side).
• LED_Anode: Connect R4 (other side) to D1 (anode).

Conceptual block diagram

Schematic

Practical Case: Veto Voting System (74HC00 Logic Flow)

INPUTS (Active High)           LOGIC PROCESSING (74HC00 Quad NAND)                               OUTPUT
=======================================================================================================

[ SW A + R1 ] --(Pin 1)-->+
                          |
                    [ U1: Gate 1 ] --(Pin 3)--> [ U1: Gate 2 ] --(Pin 6)---+
                    [ 2-In NAND  ]              [ NAND as NOT]             |
                          |                     (Pins 4+5)                 |
[ SW B + R2 ] --(Pin 2)-->+                                                |
                                                                           |
                                                                           v
                                                                     [ U1: Gate 3 ] --(Pin 8)--> [ U1: Gate 4 ] --(Pin 11)--> [ R4: 330R ] --> [ D1: LED ] --> GND
                                                                     [ 2-In NAND  ]              [ NAND as NOT]
                                                                     (Pin 10)      \             (Pins 12+13)
                                                                                    \
[ SW C + R3 ] -------------------------------------------------------(Pin 9)---------+
(Veto/Enable)

=======================================================================================================
Logic Summary:
1. Gate 1 & 2 form an AND gate for Inputs A & B.
2. Gate 3 & 4 form an AND gate for (Result of A/B) & Input C.
3. Final Function: LED turns ON only if A AND B AND C are all High.

Truth table

The circuit implements the logic function Y = A · B · C.
* A/B: Voters
* C: Chairman/Authorization (0 = Veto/Block, 1 = Allow)

Measurements and tests

1. Supply Check: Before inserting the IC, verify 5 V between VCC and GND lines on your breadboard.
2. Default State: Ensure all switches are OFF. Power on. LED should be OFF.
3. Veto Test: Turn Switch A and Switch B ON (High). Keep Switch C OFF (Low).
   • Observation: LED must remain OFF. This confirms the Veto is active.
4. Approval Test: With A and B still ON, turn Switch C ON.
   • Observation: LED should light up (Logic High, approx 3.5 V – 4.5 V).
5. Single Vote Test: Turn Switch A OFF while B and C are ON.
   • Observation: LED should turn OFF.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Veto Voting System
.width out=256

* ==============================================================================
* Components and Models
* ==============================================================================

* LED Model
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=10p)

* 74HC00 Quad 2-Input NAND Gate Subcircuit
* Pins: 1=1A, 2=1B, 3=1Y, 4=2A, 5=2B, 6=2Y, 7=GND, 8=3Y, 9=3A, 10=3B, 11=4Y, 12=4A, 13=4B, 14=VCC
.subckt 74HC00 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Logic Threshold (2.5V) and Gain (20)
.param Vth=2.5
.param K=20
* Gate 1: Inputs 1,2 -> Output 3
B1 3 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(1,7)-Vth)))) * (1/(1+exp(-K*(V(2,7)-Vth)))))
* Gate 2: Inputs 4,5 -> Output 6
B2 6 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(4,7)-Vth)))) * (1/(1+exp(-K*(V(5,7)-Vth)))))
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: Veto Voting System
.width out=256

* ==============================================================================
* Components and Models
* ==============================================================================

* LED Model
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=10p)

* 74HC00 Quad 2-Input NAND Gate Subcircuit
* Pins: 1=1A, 2=1B, 3=1Y, 4=2A, 5=2B, 6=2Y, 7=GND, 8=3Y, 9=3A, 10=3B, 11=4Y, 12=4A, 13=4B, 14=VCC
.subckt 74HC00 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Logic Threshold (2.5V) and Gain (20)
.param Vth=2.5
.param K=20
* Gate 1: Inputs 1,2 -> Output 3
B1 3 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(1,7)-Vth)))) * (1/(1+exp(-K*(V(2,7)-Vth)))))
* Gate 2: Inputs 4,5 -> Output 6
B2 6 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(4,7)-Vth)))) * (1/(1+exp(-K*(V(5,7)-Vth)))))
* Gate 3: Inputs 9,10 -> Output 8
B3 8 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(9,7)-Vth)))) * (1/(1+exp(-K*(V(10,7)-Vth)))))
* Gate 4: Inputs 12,13 -> Output 11
B4 11 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(12,7)-Vth)))) * (1/(1+exp(-K*(V(13,7)-Vth)))))
.ends 74HC00

* ==============================================================================
* Main Circuit Wiring
* ==============================================================================

* Power Supply (V1)
V1 VCC 0 DC 5

* Inputs (Simulating Switches SW1 positions A, B, C)
* Generating dynamic pulses to test the truth table (000 to 111)
* Input A (LSB, Period 100us)
Va Input_A 0 PULSE(0 5 10u 1u 1u 50u 100u)
* Input B (Period 200us)
Vb Input_B 0 PULSE(0 5 10u 1u 1u 100u 200u)
* Input C (MSB, Period 400us)
Vc Input_C 0 PULSE(0 5 10u 1u 1u 200u 400u)

* Pull-down Resistors (R1, R2, R3)
R1 Input_A 0 10k
R2 Input_B 0 10k
R3 Input_C 0 10k

* Logic IC U1 (74HC00)
* Connectivity based on Wiring Guide:
* Pin 1 (In A) -> Input_A
* Pin 2 (In B) -> Input_B
* Pin 3 (Out 1) -> Node_NAND1
* Pin 4 (In 2A) -> Node_NAND1
* Pin 5 (In 2B) -> Node_NAND1
* Pin 6 (Out 2) -> Node_AND_AB
* Pin 7 (GND)   -> 0
* Pin 8 (Out 3) -> Node_NAND_FINAL
* Pin 9 (In 3A) -> Input_C
* Pin 10 (In 3B)-> Node_AND_AB
* Pin 11 (Out 4)-> Vout
* Pin 12 (In 4A)-> Node_NAND_FINAL
* Pin 13 (In 4B)-> Node_NAND_FINAL
* Pin 14 (VCC)  -> VCC
XU1 Input_A Input_B Node_NAND1 Node_NAND1 Node_NAND1 Node_AND_AB 0 Node_NAND_FINAL Input_C Node_AND_AB Vout Node_NAND_FINAL Node_NAND_FINAL VCC 74HC00

* Output Stage
R4 Vout LED_Anode 330
D1 LED_Anode 0 DLED

* ==============================================================================
* Simulation Commands
* ==============================================================================

.op
.tran 1u 500u

* Print Inputs and Output to check logic (Vout should be High only when A, B, C are High)
.print tran V(Input_A) V(Input_B) V(Input_C) V(Vout)

.end

Simulation Results (Transient Analysis)

Analysis: The simulation successfully sweeps inputs A, B, and C. Vout is High (5V) only when A, B, and C are all High (e.g., around 33us, 301us, 559us). In all other states (000, 011, 101, 110, etc.), Vout remains Low (~0V). This matches the logic Y = A · B · C.

Show raw data table (671 rows)

Index   time            v(input_a)      v(input_b)      v(input_c)      v(vout)
0	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
1	1.000000e-08	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
2	2.000000e-08	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
3	4.000000e-08	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
4	8.000000e-08	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
5	1.600000e-07	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
6	3.200000e-07	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
7	6.400000e-07	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
8	1.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
9	2.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
10	3.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
11	4.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
12	5.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
13	6.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
14	7.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
15	8.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
16	9.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
17	1.000000e-05	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
18	1.010000e-05	5.000000e-01	5.000000e-01	5.000000e-01	-6.01853e-36
19	1.030000e-05	1.500000e+00	1.500000e+00	1.500000e+00	-6.01853e-36
20	1.048757e-05	2.437858e+00	2.437858e+00	2.437858e+00	-6.01853e-36
21	1.071179e-05	3.558937e+00	3.558937e+00	3.558937e+00	5.000000e+00
22	1.085965e-05	4.298271e+00	4.298271e+00	4.298271e+00	5.000000e+00
23	1.099537e-05	4.976846e+00	4.976846e+00	4.976846e+00	5.000000e+00
... (647 more rows) ...

Common mistakes and how to avoid them

1. Floating Inputs: Forgetting the pull-down resistors (R1, R2, R3). Without them, the CMOS inputs of the 74HC00 will float, causing erratic switching or oscillation.
2. Confusing Pinout: The 74HC00 pinout is standard, but mixing up Input pins (e.g., 1 A/1B) with Output pins (e.g., 1Y) is common. Double-check the datasheet diagram.
3. Misinterpreting «Veto»: In this design, Input C is an «Enable» line (Active High). If you think of Veto as «Switch ON to Block» (Active Low logic), the wiring of Switch C would need to be inverted. Here, Switch C ON means «Authorize».

Troubleshooting

• LED never turns ON: Check that the LED polarity is correct (Anode to resistor, Cathode to GND). Verify U1 is powered (Pin 14 to 5 V, Pin 7 to GND).
• LED stays ON even when switches are OFF: Check if R1, R2, or R3 are missing or disconnected. Ensure you are not using NC (Normally Closed) switches by mistake.
• Circuit works for A and B but C has no effect: Check the wiring on Gate 3 (Pins 8, 9, 10). Ensure pin 9 connects to Switch C and pin 10 connects to the output of the previous stage (Pin 6).

Possible improvements and extensions

1. Veto Indicator: Add a second LED (Green) driven by an unused gate (or a transistor) connected to Input C, indicating «Session Open» (Authorization Granted) or «Session Locked» (Veto).
2. Majority Vote Modification: Redesign the circuit to allow the proposal to pass if any two of the three members (A, B, C) vote Yes, removing the specific veto power and making all members equal.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic. Implement a logic safety stop for a water pump using a NAND gate.

Objective and use case

In this session, you will build a digital safety circuit using a 74HC00 NAND gate. The circuit monitors two liquid level sensors and automatically cuts power to a «pump» (simulated by an LED) only when both sensors indicate the tank is dangerously full.

• Industrial tank filling: Prevents chemical spills by ensuring redundant sensors must agree before triggering an emergency shutdown.
• Sump pump systems: Prevents motor burnout or overflow by managing logic states between high-water and critical-overflow marks.
• Home automation: Simple logic for reservoir management without needing a microcontroller.

Expected outcome:
* Normal Operation: The LED (pump) remains ON (Logic High, ~5 V) when the tank is empty or partially full.
* Emergency Stop: The LED turns OFF (Logic Low, ~0 V) immediately when both switch inputs are Logic High (simulating water detection).
* Validation: A specific Truth Table will be verified where only the input condition 1, 1 results in an output of 0.

Target audience: Basic level electronics students and hobbyists.

Materials

• V1: 5 V DC power supply, function: Main circuit power.
• U1: 74HC00, function: Quad 2-Input NAND Gate IC.
• S1: SPST Toggle Switch, function: High Level Sensor simulator.
• S2: SPST Toggle Switch, function: Safety Level Sensor simulator.
• R1: 10 kΩ resistor, function: Pull-down for S1.
• R2: 10 kΩ resistor, function: Pull-down for S2.
• R3: 330 Ω resistor, function: Current limiting for the Pump Status LED.
• D1: Green LED, function: Pump status indicator (ON = Running, OFF = Stopped).

Pin-out of the IC used

Chip: 74HC00 (Quad 2-Input NAND Gate)

Wiring guide

Construct the circuit following these node connections. Ensure the power supply is off while building.

• Power Rail: Connect V1 positive terminal to node VCC and negative terminal to node 0 (GND).
• IC Power: Connect U1 pin 14 to VCC and pin 7 to 0.
• Sensor 1 (Input A):
  • Connect S1 between VCC and node SENSOR_HI.
  • Connect R1 between SENSOR_HI and 0 (Pull-down).
  • Connect U1 pin 1 to node SENSOR_HI.
• Sensor 2 (Input B):
  • Connect S2 between VCC and node SENSOR_SAFE.
  • Connect R2 between SENSOR_SAFE and 0 (Pull-down).
  • Connect U1 pin 2 to node SENSOR_SAFE.
• Pump Control (Output):
  • Connect U1 pin 3 to node PUMP_CTRL.
  • Connect D1 (Anode) to node PUMP_CTRL.
  • Connect D1 (Cathode) to node LED_NODE.
  • Connect R3 between LED_NODE and 0.

Conceptual block diagram

Schematic

Title: Practical case: Water tank level control

      INPUTS (Sensors)                       PROCESSING (U1: 74HC00)                  OUTPUT (Pump Indicator)
   ======================                  ===========================              ===========================

   [ VCC ]
      |
   [ S1: High Sensor ]
      |
      +--(Node: SENSOR_HI)---------------> [ U1: Pin 1 (Input A) ]
      |                                             |
   [ R1: 10k Pull-Down ]                            |
      |                                             v
   [ GND ]                                     [ NAND Gate ] --(Node: PUMP_CTRL)--> [ D1: Green LED ]
                                                    ^                                       |
                                                    |                               (Node: LED_NODE)
   [ VCC ]                                          |                                       |
      |                                             |                                  [ R3: 330R ]
   [ S2: Safe Sensor ]                              |                                       |
      |                                             |                                    [ GND ]
      +--(Node: SENSOR_SAFE)-------------> [ U1: Pin 2 (Input B) ]
      |
   [ R2: 10k Pull-Down ]
      |
   [ GND ]

   (Note: U1 Power Connections -> Pin 14: VCC, Pin 7: GND)

Truth table

The 74HC00 acts as a safety interlock. The pump runs (Output 1) by default and only stops (Output 0) when the specific danger condition (1, 1) is met.

Measurements and tests

1. Default State Check: Ensure S1 and S2 are open (OFF). Power on the circuit. Measure the voltage at node PUMP_CTRL relative to GND. It should read approximately 5 V. The Green LED should be lit.
2. Single Sensor Test: Close S1 only. The LED should remain ON. Open S1 and close S2 only. The LED should remain ON.
3. Safety Stop Test: Close both S1 and S2 simultaneously.
   • Measure the voltage at node PUMP_CTRL. It should drop to near 0 V (< 0.1 V).
   • Confirm the LED turns OFF immediately.
4. Recovery: Open either switch; the LED should turn back ON.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Water tank level control
.width out=256

* --- Models ---
* Generic Green LED Model
.model DLED D(IS=1e-14 N=2 RS=10 BV=5 IBV=10u CJO=10p)
* Ideal Voltage-Controlled Switch Model
.model SW_IDEAL sw(vt=2.5 vh=0 ron=1 roff=10Meg)

* --- Power Supply ---
* V1: 5 V DC power supply
V1 VCC 0 DC 5

* --- Input Sensors (Switches + Pull-downs) ---
* S1: High Level Sensor simulator
* Modeled as a switch connected to VCC, controlled by a pulse source (V_ACT1)
* Timing: Period 100us, covers logic states quickly
V_ACT1 ACT1 0 PULSE(0 5 0 1u 1u 50u 100u)
S1 VCC SENSOR_HI ACT1 0 SW_IDEAL
R1 SENSOR_HI 0 10k
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: Water tank level control
.width out=256

* --- Models ---
* Generic Green LED Model
.model DLED D(IS=1e-14 N=2 RS=10 BV=5 IBV=10u CJO=10p)
* Ideal Voltage-Controlled Switch Model
.model SW_IDEAL sw(vt=2.5 vh=0 ron=1 roff=10Meg)

* --- Power Supply ---
* V1: 5 V DC power supply
V1 VCC 0 DC 5

* --- Input Sensors (Switches + Pull-downs) ---
* S1: High Level Sensor simulator
* Modeled as a switch connected to VCC, controlled by a pulse source (V_ACT1)
* Timing: Period 100us, covers logic states quickly
V_ACT1 ACT1 0 PULSE(0 5 0 1u 1u 50u 100u)
S1 VCC SENSOR_HI ACT1 0 SW_IDEAL
R1 SENSOR_HI 0 10k

* S2: Safety Level Sensor simulator
* Modeled as a switch connected to VCC, controlled by a pulse source (V_ACT2)
* Timing: Period 200us, provides different state combinations with S1
V_ACT2 ACT2 0 PULSE(0 5 0 1u 1u 100u 200u)
S2 VCC SENSOR_SAFE ACT2 0 SW_IDEAL
R2 SENSOR_SAFE 0 10k

* --- Logic IC: U1 (74HC00 Quad 2-Input NAND Gate) ---
* Wiring Guide connections:
* Pin 1 (Input A) -> SENSOR_HI
* Pin 2 (Input B) -> SENSOR_SAFE
* Pin 3 (Output)  -> PUMP_CTRL
* Pin 7 (GND)     -> 0
* Pin 14 (VCC)    -> VCC

.subckt 74HC00 1 2 3 7 14
    * Behavioral NAND implementation using continuous sigmoid functions for convergence
    * V(3) = VCC * (1 - (Sigmoid(In1) * Sigmoid(In2)))
    * Threshold is set to VCC/2 (approx 2.5V)
    B_NAND 3 7 V = V(14) * (1 - ( (1/(1+exp(-50*(V(1)-0.5*V(14))))) * (1/(1+exp(-50*(V(2)-0.5*V(14))))) ))
.ends

XU1 SENSOR_HI SENSOR_SAFE PUMP_CTRL 0 VCC 74HC00

* --- Output Stage ---
* D1: Pump Status LED (Green)
* R3: Current limiting resistor
D1 PUMP_CTRL LED_NODE DLED
R3 LED_NODE 0 330

* --- Simulation Directives ---
.op
* Transient analysis for 500us to capture full truth table sequence
.tran 1u 500u

* --- Output Printing ---
* Required to generate simulation log
.print tran V(SENSOR_HI) V(SENSOR_SAFE) V(PUMP_CTRL) V(LED_NODE)

Simulation Results (Transient Analysis)

Analysis: The simulation successfully cycles through all 4 logic states. When both inputs are High (~5V), the output PUMP_CTRL goes Low (~0V) and the LED voltage drops to ~0V (OFF). In all other states (00, 01, 10), the output is High (~5V) and the LED node is ~3.46V (ON).

Show raw data table (810 rows)

Index   time            v(sensor_hi)    v(sensor_safe)  v(pump_ctrl)    v(led_node)
0	0.000000e+00	4.995005e-03	4.995005e-03	5.000000e+00	3.463208e+00
1	1.000000e-08	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
2	2.000000e-08	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
3	4.000000e-08	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
4	8.000000e-08	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
5	1.600000e-07	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
6	3.200000e-07	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
7	3.562500e-07	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
8	4.196875e-07	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
9	4.372461e-07	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
10	4.679736e-07	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
11	4.795524e-07	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
12	4.902290e-07	4.995005e-03	4.995005e-03	5.000000e+00	3.463209e+00
13	5.023412e-07	4.999500e+00	4.999500e+00	4.417025e-69	-7.81556e-01
14	5.138120e-07	4.999500e+00	4.999500e+00	4.417025e-69	1.002344e-01
15	5.170059e-07	4.999500e+00	4.999500e+00	4.417025e-69	3.466376e-02
16	5.182905e-07	4.999500e+00	4.999500e+00	4.417025e-69	2.349502e-02
17	5.201200e-07	4.999500e+00	4.999500e+00	4.417025e-69	1.345184e-02
18	5.222326e-07	4.999500e+00	4.999500e+00	4.417025e-69	7.036188e-03
19	5.244685e-07	4.999500e+00	4.999500e+00	4.417025e-69	3.539225e-03
20	5.268938e-07	4.999500e+00	4.999500e+00	4.417025e-69	1.673565e-03
21	5.291278e-07	4.999500e+00	4.999500e+00	4.417025e-69	8.446489e-04
22	5.313933e-07	4.999500e+00	4.999500e+00	4.417025e-69	4.221950e-04
23	5.337647e-07	4.999500e+00	4.999500e+00	4.417025e-69	2.037947e-04
... (786 more rows) ...

Common mistakes and how to avoid them

1. Floating Inputs: Forgetting R1 or R2 results in erratic switching because the CMOS inputs pick up electrical noise when switches are open. Fix: Always ensure inputs are pulled to Ground via resistors when the switch is open.
2. LED Polarity: Connecting the LED backwards prevents it from lighting even when logic is High. Fix: Ensure the longer leg (Anode) faces the IC output pin.
3. Shorting Output to Ground: Connecting Pin 3 directly to Ground to «test» it will damage the IC when it tries to output High. Fix: Always measure voltage with a multimeter in parallel, never force a node to ground with a wire.

Troubleshooting

• Symptom: LED is always ON, even when both switches are closed.
  • Cause: Resistors R1/R2 might be connected to VCC instead of GND, or the IC is bypassed.
  • Fix: Check that R1 and R2 connect to the negative rail (0) and switches connect to VCC.
• Symptom: LED never turns ON.
  • Cause: LED reversed or R3 is too high value/open.
  • Fix: Check D1 orientation and continuity of R3.
• Symptom: Circuit behaves erratically when touching wires.
  • Cause: Floating inputs (Missing pull-down resistors).
  • Fix: Verify R1 and R2 are securely connected to node 0.

Possible improvements and extensions

1. Visual and Audible Alarm: Connect an additional active buzzer (via a transistor driver) to the output, but invert the signal first so the buzzer sounds when the pump stops.
2. Motor Drive: Replace the LED with an NPN transistor (like 2N2222) and a relay to control a real DC water pump motor, adding a flyback diode for protection.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic | Build a fail-safe alarm system using NAND logic to detect open windows.

Objective and use case

In this practical case, you will build a digital logic circuit that monitors two window sensors. The alarm will remain silent (LED OFF) only when both windows are securely closed. If either window is opened—or if a wire is cut—the alarm triggers (LED ON).

• Home Security: Monitoring multiple entry points (windows/doors) where all must be closed to secure the perimeter.
• Machine Safety: Ensuring all safety guards or maintenance hatches are closed before a machine can operate (or signaling a fault if opened).
• Fail-Safe Design: Demonstrating how active-high loops detect broken wires or open switches as alarm conditions.

Expected outcome:
* Safe State: When both switches (windows) are closed (Logic 1), the Output is 0 V (LED OFF).
* Alarm State: If Switch 1 OR Switch 2 is opened (Logic 0), the Output rises to ≈ 5 V (LED ON).
* Logic Verification: Confirmation of the NAND truth table behavior where Output is LOW only if all inputs are HIGH.

Target audience: Electronics students and hobbyists learning basic digital logic gates.

Materials

• V1: 5 V DC power supply, function: Main circuit power
• U1: 74HC00, function: Quad 2-input NAND gate IC
• SW1: SPST switch, function: Window 1 sensor (Closed = Window Closed)
• SW2: SPST switch, function: Window 2 sensor (Closed = Window Closed)
• R1: 10 kΩ resistor, function: Pull-down for SW1
• R2: 10 kΩ resistor, function: Pull-down for SW2
• R3: 330 Ω resistor, function: Current limiting for LED
• D1: Red LED, function: Alarm indicator

Pin-out of the IC used

Chip Selected: 74HC00 (Quad 2-Input NAND Gate)

Wiring guide

This guide uses specific node names to help you visualize the connections on a breadboard.

• Power Rail: Connect V1 positive terminal to node VCC and negative terminal to node 0.
• IC Power: Connect U1 pin 14 to VCC and U1 pin 7 to 0.
• Sensor 1: Connect SW1 between VCC and node SENS1.
• Pull-down 1: Connect R1 between SENS1 and 0.
• Sensor 2: Connect SW2 between VCC and node SENS2.
• Pull-down 2: Connect R2 between SENS2 and 0.
• Logic Input: Connect U1 pin 1 (1 A) to SENS1 and U1 pin 2 (1B) to SENS2.
• Logic Output: Connect U1 pin 3 (1Y) to node ALARM_OUT.
• Indicator: Connect R3 between ALARM_OUT and the Anode of D1.
• LED Ground: Connect the Cathode of D1 to node 0.

Conceptual block diagram

Schematic

Title: Practical case: Window sensor security alarm

(Input Stage: Sensors)                  (Processing Stage: Logic)             (Output Stage: Alarm)

[ VCC ]
   |
[ SW1: Window 1 ]
   |
   +--(SENS1)-------+-----------------> [ U1: Pin 1 (Input A) ]
                    |                                         |
                 [ R1: 10k ]                                  v
                    |                                 [ U1: NAND Gate ] --(ALARM_OUT)--> [ R3: 330 Ω ] --> [ D1: LED ] --> GND
                 [ GND ]                                      ^
                                                              |
[ VCC ]             |                                         |
   |                |                                         |
[ SW2: Window 2 ]   |                                         |
   |                |                                         |
   +--(SENS2)-------+-----------------> [ U1: Pin 2 (Input B) ]
                    |
                 [ R2: 10k ]
                    |
                 [ GND ]

Truth table

The 74HC00 implements the NAND function. In this security context, Logic 1 represents a «Closed Window» (Safe), and Logic 0 represents an «Open Window» (Breach).

Measurements and tests

Follow these steps to validate your alarm system:

1. Initial Power-Up: Ensure both switches (SW1, SW2) are closed. Turn on the 5 V supply. The LED D1 should be OFF.
2. Voltage Check (Secure): Use a multimeter to measure the voltage at node ALARM_OUT. It should be close to 0 V (< 0.2 V).
3. Breach Test 1: Open SW1 while keeping SW2 closed. The LED should turn ON. Measure ALARM_OUT; it should read close to 5 V.
4. Breach Test 2: Close SW1 and open SW2. The LED should turn ON.
5. Total Breach: Open both switches. The LED should remain ON.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Window sensor security alarm
.width out=256
* ngspice netlist

* --- Component Models ---
* Switch model for SW1 and SW2 (Sensors)
* Vt=2.5V: Switch closes when control voltage > 2.5V
* Ron=1m: Low resistance when closed
* Roff=100Meg: High resistance when open
.model SW_MOD SW(Vt=2.5 Ron=1m Roff=100Meg)

* LED model for D1
.model LED_RED D(IS=1e-22 RS=5 N=1.5 CJO=10p BV=5)

* --- Power Supply ---
* V1: 5 V DC power supply connected to VCC and 0 (GND)
V1 VCC 0 DC 5

* --- Window Sensor 1 ---
* Control source V_ACT1 simulates the physical action of opening/closing Window 1
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: Window sensor security alarm
.width out=256
* ngspice netlist

* --- Component Models ---
* Switch model for SW1 and SW2 (Sensors)
* Vt=2.5V: Switch closes when control voltage > 2.5V
* Ron=1m: Low resistance when closed
* Roff=100Meg: High resistance when open
.model SW_MOD SW(Vt=2.5 Ron=1m Roff=100Meg)

* LED model for D1
.model LED_RED D(IS=1e-22 RS=5 N=1.5 CJO=10p BV=5)

* --- Power Supply ---
* V1: 5 V DC power supply connected to VCC and 0 (GND)
V1 VCC 0 DC 5

* --- Window Sensor 1 ---
* Control source V_ACT1 simulates the physical action of opening/closing Window 1
* Logic: High (5V) = Window Closed, Low (0V) = Window Open
* Timing: Toggles every 100us (Period 200us)
V_ACT1 ACT1 0 PULSE(0 5 0 1u 1u 100u 200u)

* SW1: Connects VCC to SENS1 when window is closed
S1 VCC SENS1 ACT1 0 SW_MOD

* R1: Pull-down resistor for SENS1 (10k)
R1 SENS1 0 10k

* --- Window Sensor 2 ---
* Control source V_ACT2 simulates Window 2
* Timing: Toggles every 200us (Period 400us) to test all truth table combinations
V_ACT2 ACT2 0 PULSE(0 5 0 1u 1u 200u 400u)

* SW2: Connects VCC to SENS2 when window is closed
S2 VCC SENS2 ACT2 0 SW_MOD

* R2: Pull-down resistor for SENS2 (10k)
R2 SENS2 0 10k

* --- Logic IC: U1 (74HC00) ---
* Quad 2-input NAND gate. We instantiate one gate.
* Pin mapping according to wiring guide:
* Pin 1 (Input A) -> SENS1
* Pin 2 (Input B) -> SENS2
* Pin 3 (Output Y) -> ALARM_OUT
* Pin 7 -> GND (0), Pin 14 -> VCC
XU1 SENS1 SENS2 ALARM_OUT 0 VCC 74HC00_GATE

* Subcircuit for NAND Gate using robust continuous functions
.subckt 74HC00_GATE A B Y GND VCC
* Logic: Y = NAND(A, B) = NOT(A AND B)
* Implemented using sigmoid functions for convergence:
* 1 / (1 + exp(-k*(V-Vth))) acts as a smooth logical comparator.
* Vth = 2.5V, k = 20
B_NAND Y GND V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) ))
.ends

* --- Alarm Output Indicator ---
* R3: Current limiting resistor (330 Ohm)
R3 ALARM_OUT LED_ANODE 330

* D1: Red LED connected to Ground
D1 LED_ANODE 0 LED_RED

* --- Simulation Commands ---
.op
* Transient analysis for 500us to capture all logic states
.tran 1u 500u

* Output configuration
* We print the Sensor inputs and the Alarm output
.print tran V(SENS1) V(SENS2) V(ALARM_OUT) V(LED_ANODE)

.end

Simulation Results (Transient Analysis)

Analysis: The simulation correctly implements the NAND logic truth table. When both sensors are High (5V, Closed), the Output is Low (~0V). If either or both sensors are Low (Open), the Output goes High (5V), activating the LED (approx 1.83V at anode).

Show raw data table (657 rows)

Index   time            v(sens1)        v(sens2)        v(alarm_out)    v(led_anode)
0	0.000000e+00	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
1	1.000000e-08	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
2	2.000000e-08	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
3	4.000000e-08	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
4	8.000000e-08	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
5	1.600000e-07	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
6	3.200000e-07	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
7	3.562500e-07	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
8	4.196875e-07	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
9	4.372461e-07	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
10	4.679736e-07	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
11	4.795524e-07	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
12	4.902290e-07	4.999500e-04	4.999500e-04	5.000000e+00	1.833072e+00
13	5.023412e-07	5.000000e+00	5.000000e+00	3.894872e-36	1.057689e+00
14	5.138120e-07	5.000000e+00	5.000000e+00	3.894872e-36	-7.61250e-02
15	5.160398e-07	5.000000e+00	5.000000e+00	3.894872e-36	-3.72798e-02
16	5.172425e-07	5.000000e+00	5.000000e+00	3.894872e-36	-2.57490e-02
17	5.188923e-07	5.000000e+00	5.000000e+00	3.894872e-36	-1.54585e-02
18	5.214063e-07	5.000000e+00	5.000000e+00	3.894872e-36	-6.97976e-03
19	5.238372e-07	5.000000e+00	5.000000e+00	3.894872e-36	-3.25627e-03
20	5.261078e-07	5.000000e+00	5.000000e+00	3.894872e-36	-1.60566e-03
21	5.281984e-07	5.000000e+00	5.000000e+00	3.894872e-36	-8.40881e-04
22	5.304310e-07	5.000000e+00	5.000000e+00	3.894872e-36	-4.20300e-04
23	5.328536e-07	5.000000e+00	5.000000e+00	3.894872e-36	-1.97001e-04
... (633 more rows) ...

Common mistakes and how to avoid them

1. Floating Inputs: Forgetting R1 or R2 causes the inputs to «float» when switches are open, leading to erratic LED flickering. Solution: Always ensure inputs have a path to ground (via pull-down resistors) when the switch is open.
2. LED Polarity: Connecting the LED backwards prevents it from lighting up even when the alarm is active. Solution: Ensure the longer leg (Anode) faces the resistor and IC output.
3. Incorrect Switch Wiring: Placing the switch in parallel with the resistor instead of in series with the voltage source creates a short circuit. Solution: Follow the wiring guide: VCC -> Switch -> Node -> Resistor -> GND.

Troubleshooting

• Symptom: LED is always ON, even when switches are closed.
  • Cause: One of the switches is not making contact, or an input wire is loose.
  • Fix: Check continuity across SW1 and SW2; ensure pin 1 and pin 2 actually receive 5 V.
• Symptom: LED never turns ON.
  • Cause: LED is reversed, IC is not powered, or R3 is too high.
  • Fix: Check pin 14 for 5 V. Reverse the LED. Verify R3 is 330 Ω, not 330 kΩ.
• Symptom: Logic works reversed (LED ON when safe, OFF when open).
  • Cause: You may be using an AND gate (74HC08) instead of NAND, or your switch/resistor logic is inverted (Pull-ups instead of Pull-downs).
  • Fix: Verify the chip number is 74HC00.

Possible improvements and extensions

1. Audible Alarm: Connect the base of an NPN transistor to ALARM_OUT to drive a 5 V active buzzer, adding sound to the light.
2. Latching Alarm: Use the remaining gates in the 74HC00 to build an SR Latch. This would keep the alarm sounding even if the burglar closes the window immediately after entering.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Medium. Design a logic circuit that alerts the user when a water sensor stops detecting liquid using a NOT gate.

Objective and use case

In this case, you will build a monitoring circuit using a 74HC04 inverter that illuminates a red LED when a tank’s liquid level drops below a critical point.

• Prevents pump damage: Stops water pumps from running dry in hydroponic systems.
• Household safety: Alerts when rooftop reserve tanks are empty.
• Industrial maintenance: Visual flag for coolant refill requirements.

Expected outcome:
* Water Present: The sensor is open (Logic 1 input) $\rightarrow$ LED remains OFF.
* Tank Empty: The sensor closes (Logic 0 input) $\rightarrow$ LED turns ON.
* Logic Level: $V_{in} \approx 0\text{ V}$ activates the alert; $V_{in} \approx 5\text{ V}$ indicates normal status.

Target audience: Electronics students and hobbyists familiar with basic digital logic.

Materials

• V1: 5 V DC power supply, function: main circuit power
• U1: 74HC04 Hex Inverter IC, function: logic inversion
• S1: Float switch (SPST, configured to Close when Empty), function: liquid level sensor
• R1: 10 kΩ resistor, function: pull-up for sensor signal
• R2: 330 Ω resistor, function: LED current limiting
• D1: Red LED, function: visual empty alert
• C1: 100 nF ceramic capacitor, function: power supply decoupling

Pin-out of the IC used

Selected Chip: 74HC04 (Hex Inverter)

Wiring guide

• V1 connects between node VCC and node GND.
• C1 connects between node VCC and node GND (placed physically close to U1).
• R1 connects between node VCC and node SENSE_IN.
• S1 connects between node SENSE_IN and node GND.
• U1 pin 1 connects to node SENSE_IN.
• U1 pin 2 connects to node ALERT_OUT.
• U1 pin 14 connects to VCC; pin 7 connects to GND.
• R2 connects between node ALERT_OUT and node LED_ANODE.
• D1 connects between node LED_ANODE (Anode) and node GND (Cathode).

Conceptual block diagram

Schematic

[ INPUT / SENSOR ]                 [ LOGIC PROCESSING ]                 [ OUTPUT / ALERT ]

[ VCC 5V ] --> [ R1: 10k ] --+
               (Pull-Up)     |
                             |
                             V
                        (SENSE_IN) ---->+------------------+
                        (Pin 1)         |    U1: 74HC04    |
                             ^          |   Hex Inverter   |--(ALERT_OUT)--> [ R2: 330R ] --> [ D1: Red LED ] --> GND
                             |          |   (Pin 1 -> 2)   |  (Pin 2)        (Limiting)       (Anode/Cathode)
[ GND 0V ] --> [ S1: Float ]-+          +------------------+
               (Switch)                           ^
                                                  |
                                            [ C1: 100nF ]
                                            (Decoupling)
                                            (VCC / GND)

Truth table

Measurements and tests

1. Supply Check: Measure voltage between VCC and GND. Ensure it is stable at 5 V.
2. Full Tank Simulation: Manually lift the float (ensure S1 is OPEN). Measure voltage at SENSE_IN. It should be $\approx 5\text{ V}$. Verify LED is OFF.
3. Empty Tank Simulation: Drop the float (ensure S1 is CLOSED). Measure voltage at SENSE_IN. It should be $\approx 0\text{ V}$.
4. Logic Output: While S1 is closed (Empty), measure voltage at ALERT_OUT. It should be $\approx 5\text{ V}$.
5. Current Draw: Measure the current through D1 ($I_{led}$) when ON. It should be approximately 10–12 mA depending on the specific LED voltage drop.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Empty Tank Level Indicator

* ==============================================================================
* BILL OF MATERIALS & COMPONENTS
* ==============================================================================

* --- Power Supply ---
* V1: 5 V DC power supply
V1 VCC 0 DC 5

* --- Decoupling ---
* C1: 100 nF ceramic capacitor (Power supply decoupling)
C1 VCC 0 100n

* --- Sensor Input Section ---
* R1: 10 kΩ resistor (Pull-up for sensor signal)
R1 VCC SENSE_IN 10k

* S1: Float switch (SPST)
* Wiring: Connects between node SENSE_IN and node GND.
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: Empty Tank Level Indicator

* ==============================================================================
* BILL OF MATERIALS & COMPONENTS
* ==============================================================================

* --- Power Supply ---
* V1: 5 V DC power supply
V1 VCC 0 DC 5

* --- Decoupling ---
* C1: 100 nF ceramic capacitor (Power supply decoupling)
C1 VCC 0 100n

* --- Sensor Input Section ---
* R1: 10 kΩ resistor (Pull-up for sensor signal)
R1 VCC SENSE_IN 10k

* S1: Float switch (SPST)
* Wiring: Connects between node SENSE_IN and node GND.
* Simulation: Modeled as a Voltage Controlled Switch (SW).
* Logic: 
*   - Tank Full (Float Up) -> Switch Open -> SENSE_IN pulled to VCC.
*   - Tank Empty (Float Down) -> Switch Closed -> SENSE_IN pulled to GND.
* Control Source V_FLOAT_ACT simulates the float movement.
*   - 0V = Float Up (Full)
*   - 5V = Float Down (Empty)
S1 SENSE_IN 0 FLOAT_CTRL 0 SW_FLOAT
.model SW_FLOAT SW(Vt=2.5 Ron=0.1 Roff=10Meg)

* Stimulus: Float starts Up (Full), drops to Down (Empty) at 50us, returns at 200us.
V_FLOAT_ACT FLOAT_CTRL 0 PULSE(0 5 50u 1u 1u 150u 400u)

* --- Logic Processing ---
* U1: 74HC04 Hex Inverter
* Wiring Guide: Pin 1 (In) -> SENSE_IN, Pin 2 (Out) -> ALERT_OUT
* Power: Pin 14 -> VCC, Pin 7 -> GND
* Implemented as a subcircuit to strictly map pins.
XU1 SENSE_IN ALERT_OUT 0 VCC 74HC04_GATE

* Subcircuit definition for one gate of 74HC04
.subckt 74HC04_GATE IN OUT GND VCC
    * Behavioral voltage source for robust logic inversion
    * Uses sigmoid function for convergence: Vout = VCC if Vin < 2.5V
    B1 OUT GND V = V(VCC) * (1 / (1 + exp(50 * (V(IN) - 2.5))))
.ends

* --- Output Alert ---
* R2: 330 Ω resistor (LED current limiting)
R2 ALERT_OUT LED_ANODE 330

* D1: Red LED (Visual empty alert)
* Wiring: Anode -> LED_ANODE, Cathode -> GND
D1 LED_ANODE 0 LED_RED
.model LED_RED D(IS=1e-14 N=2 RS=5 BV=5 IBV=10u CJO=40p)

* ==============================================================================
* ANALYSIS COMMANDS
* ==============================================================================

* Operating Point Analysis
.op

* Transient Analysis
* Run for 500us to capture the float switch activation cycle
.tran 1u 500u

* Output Printing
* Monitor Sensor Input, Inverter Output, and LED Voltage
.print tran V(SENSE_IN) V(ALERT_OUT) V(LED_ANODE) V(FLOAT_CTRL)

.end

Simulation Results (Transient Analysis)

Show raw data table (1190 rows)

Index   time            v(sense_in)     v(alert_out)    v(led_anode)
0	0.000000e+00	4.995005e+00	3.316079e-54	-1.70080e-28
1	1.000000e-08	4.995005e+00	3.316079e-54	-9.73961e-29
2	2.000000e-08	4.995005e+00	3.316079e-54	-1.41516e-29
3	4.000000e-08	4.995005e+00	3.316079e-54	8.723601e-29
4	8.000000e-08	4.995005e+00	3.316079e-54	1.163518e-28
5	1.600000e-07	4.995005e+00	3.316079e-54	4.380930e-29
6	3.200000e-07	4.995005e+00	3.316079e-54	-1.45299e-29
7	6.400000e-07	4.995005e+00	3.316079e-54	-1.01395e-29
8	1.280000e-06	4.995005e+00	3.316079e-54	-5.46095e-32
9	2.280000e-06	4.995005e+00	3.316079e-54	4.098577e-31
10	3.280000e-06	4.995005e+00	3.316079e-54	2.282032e-32
11	4.280000e-06	4.995005e+00	3.316079e-54	-9.50625e-33
12	5.280000e-06	4.995005e+00	3.316079e-54	-1.09186e-33
13	6.280000e-06	4.995005e+00	3.316079e-54	1.911218e-34
14	7.280000e-06	4.995005e+00	3.316079e-54	3.847480e-35
15	8.280000e-06	4.995005e+00	3.316079e-54	-2.97995e-36
16	9.280000e-06	4.995005e+00	3.316079e-54	-1.15977e-36
17	1.028000e-05	4.995005e+00	3.316079e-54	1.723722e-38
18	1.128000e-05	4.995005e+00	3.316079e-54	3.117034e-38
19	1.228000e-05	4.995005e+00	3.316079e-54	1.177223e-39
20	1.328000e-05	4.995005e+00	3.316079e-54	-7.52109e-40
21	1.428000e-05	4.995005e+00	3.316079e-54	-6.99870e-41
22	1.528000e-05	4.995005e+00	3.316079e-54	1.597704e-41
23	1.628000e-05	4.995005e+00	3.316079e-54	2.660714e-42
... (1166 more rows) ...

Common mistakes and how to avoid them

1. Leaving inputs floating: Even though we only use one gate (Pin 1/2), unused inputs on CMOS chips (pins 3, 5, 9, 11, 13) should be tied to GND or VCC to prevent oscillation and excess power consumption.
2. Incorrect Pull-up wiring: Connecting the resistor in series with the input instead of as a pull-up to VCC. Ensure R1 goes strictly to 5V.
3. Sensor Logic inversion: Using a sensor that is Open when Empty without changing the circuit logic. This would cause the light to be ON when the tank is full. Ensure the mechanical action matches the truth table.

Troubleshooting

• LED is always ON: Check if S1 is stuck in the Closed position or if pin 1 is shorted to ground.
• LED never turns ON: Check if the float switch is actually closing the circuit to ground. Measure resistance across S1 terminals while moving the float.
• Chip gets hot: Check for short circuits at the output or if VCC/GND are reversed (Pins 14 and 7).
• LED flickers: The liquid might be turbulent. Add a capacitor (e.g., 10 µF) in parallel with S1 to create a hardware debounce delay.

Possible improvements and extensions

1. Audio Alert: Add a 5V active buzzer in parallel with the LED/Resistor combo to provide an audible alarm when the tank is empty.
2. Hysteresis: Replace the 74HC04 with a 74HC14 (Schmitt Trigger Inverter). This prevents the LED from jittering if the water level is right at the switching threshold.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic. Build a safety circuit that cuts a ‘Ready’ signal instantly when a stop button is pressed.

Objective and use case

In this tutorial, you will build a digital logic circuit that inverts an input signal. Specifically, a «System Ready» indicator (Green LED) will remain active by default and will immediately turn off when an emergency pushbutton is pressed.

• Why it is useful:

  • Industrial safety: Simulates an emergency kill switch where the active state shuts down machinery.
  • Security systems: Sensors (like door contacts) often break a circuit to trigger an alarm or change a status.
  • Fail-safe logic: Ensures a system defaults to «safe» (off) when an active intervention occurs.

• Expected outcome:

  • Idle State: When the button is NOT pressed (Logic 0), the Green LED is ON (Logic 1).
  • Active State: When the button IS pressed (Logic 1), the Green LED turns OFF (Logic 0).
  • Signal Voltage: Input transitions between 0 V and 5 V; Output inverts logically.

• Target audience and level: Students and hobbyists learning basic digital inversion.

Materials

• V1: 5 V DC supply, function: main power source.
• U1: 74HC04 Hex Inverter IC, function: logic inversion (NOT gate).
• S1: Pushbutton (Normally Open), function: emergency signal trigger.
• R1: 10 kΩ resistor, function: pull-down resistor for input stability.
• R2: 330 Ω resistor, function: current limiting for the LED.
• D1: Green LED, function: ‘System Ready’ indicator.

Pin-out of the IC used

Selected Chip: 74HC04 (Hex Inverter)

Wiring guide

Construct the circuit following these node connections (Nodes: VCC, 0, V_IN, V_OUT):

• Power Supply:
  • V1 connects between VCC (positive) and 0 (negative/GND).
  • U1 Pin 14 connects to VCC.
  • U1 Pin 7 connects to 0.
• Input Stage (Button Logic):
  • S1 connects between VCC and V_IN.
  • R1 connects between V_IN and 0 (This pulls the input to 0 V when the button is open).
  • U1 Pin 1 (Input 1A) connects to V_IN.
• Output Stage (Indicator):
  • U1 Pin 2 (Output 1Y) connects to V_OUT.
  • R2 connects between V_OUT and node LED_ANODE.
  • D1 Anode connects to LED_ANODE.
  • D1 Cathode connects to 0.

Conceptual block diagram

Schematic

[ INPUT STAGE ]                          [ LOGIC STAGE ]                       [ OUTPUT STAGE ]

    [ V1: 5V Supply ] --(Power VCC)--------> [ U1 Power: Pin 14 ]

    [ S1: Pushbutton ] --(Press = 5V)--+
    (Emergency Trig)                   |
                                       v
                                  [ Node V_IN ] --(Pin 1)--> [   U1: 74HC04   ] --(Pin 2)--> [ R2: 330 Ohm ] --> [ D1: Green LED ] --> [ GND ]
                                       ^                     [ Hex Inverter IC]              (Current Limit)     (System Ready)
                                       |                     [   (NOT Gate)   ]
    [ R1: 10k Resistor ] --(Open = 0V)-+                     [  GND: Pin 7    ]
    (Pull-down to GND)                                             |
                                                                   v
                                                                [ GND ]

Truth table

The 74HC04 implements the Boolean NOT function ($Y = \overline{A}$).

Measurements and tests

Follow these steps to validate the emergency deactivation logic:

1. Idle Check:

   • Ensure the power supply is on. Do not touch the button.
   • Visual: The Green LED should be lit.
   • Measurement: Use a multimeter to measure voltage at V_IN (Pin 1). It should be approx 0 V.
   • Measurement: Measure voltage at V_OUT (Pin 2). It should be approx 5 V (Logic High).

2. Activation Check:

   • Press and hold the pushbutton S1.
   • Visual: The Green LED must turn OFF immediately.
   • Measurement: Voltage at V_IN should rise to 5 V.
   • Measurement: Voltage at V_OUT should drop to approx 0 V (Logic Low).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Emergency deactivation
* Circuit: Inverter Logic (NOT Gate) with LED Indicator

* --- Power Supply ---
* V1: Main 5V DC supply
V1 VCC 0 DC 5

* --- Input Stage (Button Logic) ---
* Components: S1 (Pushbutton), R1 (Pull-down)
* Connectivity: S1 connects VCC to V_IN. R1 connects V_IN to 0.
* Logic: 
*   - Button Released (Default): S1 Open -> V_IN pulled to 0V by R1.
*   - Button Pressed (Emergency): S1 Closed -> V_IN pulled to 5V (VCC).

* Simulation of S1 (Normally Open Pushbutton):
* Modeled as a Voltage-Controlled Switch (S1) driven by SW_CTRL.
* Vt=2.5V ensures switch closes when control signal is 5V.
S1 VCC V_IN SW_CTRL 0 SW_BTN
.model SW_BTN SW(Vt=2.5 Vh=0.1 Ron=1 Roff=10Meg)

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans

* Practical case: Emergency deactivation
* Circuit: Inverter Logic (NOT Gate) with LED Indicator

* --- Power Supply ---
* V1: Main 5V DC supply
V1 VCC 0 DC 5

* --- Input Stage (Button Logic) ---
* Components: S1 (Pushbutton), R1 (Pull-down)
* Connectivity: S1 connects VCC to V_IN. R1 connects V_IN to 0.
* Logic: 
*   - Button Released (Default): S1 Open -> V_IN pulled to 0V by R1.
*   - Button Pressed (Emergency): S1 Closed -> V_IN pulled to 5V (VCC).

* Simulation of S1 (Normally Open Pushbutton):
* Modeled as a Voltage-Controlled Switch (S1) driven by SW_CTRL.
* Vt=2.5V ensures switch closes when control signal is 5V.
S1 VCC V_IN SW_CTRL 0 SW_BTN
.model SW_BTN SW(Vt=2.5 Vh=0.1 Ron=1 Roff=10Meg)

* Control Signal (User Finger Simulation):
* Generates a pulse: 0V (Released) -> 5V (Pressed) -> 0V (Released).
* Timeline: Idle for 100us, Press for 300us, then Release.
V_BTN_CTRL SW_CTRL 0 PULSE(0 5 100u 1u 1u 300u 1000u)

* R1: 10k Pull-down resistor
R1 V_IN 0 10k

* --- Logic Stage (U1) ---
* Component: 74HC04 Hex Inverter
* Connectivity: Pin 1 (Input) -> V_IN, Pin 2 (Output) -> V_OUT.
* Power: Pin 14 -> VCC, Pin 7 -> 0.
XU1 V_IN V_OUT 0 VCC 74HC04_INV

* Subcircuit for 74HC04 Inverter
* Behavioral model: Output is High when Input is Low.
* Uses a sigmoid function for smooth switching and convergence.
.subckt 74HC04_INV In Out Gnd Vcc
B1 Out Gnd V = V(Vcc,Gnd) / (1 + exp(50 * (V(In,Gnd) - V(Vcc,Gnd)/2)))
.ends

* --- Output Stage (Indicator) ---
* Components: R2 (Resistor), D1 (Green LED)
* Connectivity: V_OUT -> R2 -> LED_ANODE -> D1 -> 0
* Logic: 
*   - V_IN=0 (Ready) -> V_OUT=5 -> LED ON.
*   - V_IN=5 (Emergency) -> V_OUT=0 -> LED OFF.

R2 V_OUT LED_ANODE 330

* D1: Green LED
D1 LED_ANODE 0 LED_GREEN
.model LED_GREEN D(Is=1e-22 Rs=5 N=1.5 Cjo=10p Vj=0.75 M=0.33 BV=5 Ibv=10u)

* --- Simulation Directives ---
* Transient analysis to observe the button press event
.tran 10u 600u

* Output data for analysis
.print tran V(V_IN) V(V_OUT) V(LED_ANODE) V(SW_CTRL)

* Calculate DC operating point
.op

.end

Simulation Results (Transient Analysis)

Show raw data table (260 rows)

Index   time            v(v_in)         v(v_out)        v(led_anode)
0	0.000000e+00	4.995005e-03	5.000000e+00	1.833072e+00
1	6.000000e-08	4.995005e-03	5.000000e+00	1.833072e+00
2	1.200000e-07	4.995005e-03	5.000000e+00	1.833072e+00
3	2.400000e-07	4.995005e-03	5.000000e+00	1.833072e+00
4	4.800000e-07	4.995005e-03	5.000000e+00	1.833072e+00
5	9.600000e-07	4.995005e-03	5.000000e+00	1.833072e+00
6	1.920000e-06	4.995005e-03	5.000000e+00	1.833072e+00
7	3.840000e-06	4.995005e-03	5.000000e+00	1.833072e+00
8	7.680000e-06	4.995005e-03	5.000000e+00	1.833072e+00
9	1.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
10	2.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
11	3.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
12	4.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
13	5.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
14	6.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
15	7.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
16	8.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
17	9.536000e-05	4.995005e-03	5.000000e+00	1.833072e+00
18	1.000000e-04	4.995005e-03	5.000000e+00	1.833072e+00
19	1.001000e-04	4.995005e-03	5.000000e+00	1.833072e+00
20	1.002750e-04	4.995005e-03	5.000000e+00	1.833072e+00
21	1.003234e-04	4.995005e-03	5.000000e+00	1.833072e+00
22	1.004082e-04	4.995005e-03	5.000000e+00	1.833072e+00
23	1.004317e-04	4.995005e-03	5.000000e+00	1.833072e+00
... (236 more rows) ...

Common mistakes and how to avoid them

1. Floating Input: Omitting R1 (pull-down resistor) causes the input to float when the button is released.
   • Solution: Always ensure the input pin is connected to GND via a resistor (e.g., 10 kΩ) when the switch is open.
2. LED Reversed: The LED does not light up even when the output is High.
   • Solution: Check D1 polarity. The longer leg (Anode) must face the resistor/IC output; the shorter leg (Cathode) goes to Ground.
3. Short Circuiting Power: Connecting the button directly between VCC and GND without the gate input in between or wiring the button in parallel with the supply.
   • Solution: Follow the node list carefully. The button connects VCC to the Input Pin, not directly to Ground.

Troubleshooting

• Symptom: LED is always ON, pressing the button does nothing.
  • Cause: The button is not connected to VCC, or the input pin is permanently grounded.
  • Fix: Check continuity across S1 when pressed. Ensure S1 connects to Pin 1.
• Symptom: LED is always OFF.
  • Cause: IC not powered, LED reversed, or input permanently connected to VCC.
  • Fix: Measure Pin 14 (VCC) and Pin 7 (GND). Check V_IN voltage; it should be 0 V when the button is released.
• Symptom: LED flickers when your hand gets close to the wire.
  • Cause: Floating input (Missing R1).
  • Fix: Install the 10 kΩ pull-down resistor securely between Pin 1 and Ground.

Possible improvements and extensions

1. Add a «Stop» Indicator: Add a second inverter (or use another gate on the same chip) to drive a Red LED that turns ON when the system is stopped (Output High when Input High).
2. Latching Circuit: Replace the simple NOT gate with a Flip-Flop logic circuit so that once the emergency button is pressed, the system stays off even if the button is released, requiring a separate «Reset» button.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are