Practical case: Nurse call bell

Level: Basic – Implement an OR gate to activate an alert from two independent switches.

Objective and use case

You will build a basic nurse call circuit using a digital OR gate to trigger a visual alert whenever either of two patient bed switches is pressed.

Why it is useful:
* Allows centralized monitoring of multiple independent trigger points.
* Demonstrates how basic digital logic simplifies parallel alarm systems without cross-wiring physical switches.
* Forms the foundation for larger, more complex call bell or security systems.

Expected outcome:
* Pressing switch A drives the output HIGH (near 5 V), lighting the LED.
* Pressing switch B drives the output HIGH (near 5 V), lighting the LED.
* Pressing both switches simultaneously drives the output HIGH, lighting the LED.
* The output remains LOW (0 V) and the LED stays off when no switches are pressed.

Target audience and level: Beginners learning digital logic gates and the importance of pull-down networks.

Materials

V1: 5 V DC supply
U1: 74HC32 quad 2-input OR gate IC
SW1: Push button switch, normally open, function: Bed A trigger
SW2: Push button switch, normally open, function: Bed B trigger
R1: 10 kΩ resistor, function: pull-down for VA
R2: 10 kΩ resistor, function: pull-down for VB
R3: 330 Ω resistor, function: LED current limiting
D1: Red LED, function: alert indicator

Pin-out of the IC used

74HC32 (Quad 2-Input OR Gate)

Pin	Name	Logic function	Connection in this case
1	1 A	Input 1 for Gate 1	Node `VA` (Switch A)
2	1B	Input 2 for Gate 1	Node `VB` (Switch B)
3	1Y	Output of Gate 1	Node `VOUT` (to LED circuit)
7	GND	Ground	Node `0`
14	VCC	Power Supply	Node `VCC`

(Note: Pins 4, 5, 8, 9, 10, 11, 12, 13 are unused inputs and should be tied to Ground in a permanent circuit to prevent CMOS latch-up).

Wiring guide

V1: positive terminal connects to VCC; negative terminal connects to 0.
SW1: connects between VCC and VA.
SW2: connects between VCC and VB.
R1: connects between VA and 0.
R2: connects between VB and 0.
U1 (pin 14): connects to VCC.
U1 (pin 7): connects to 0.
U1 (pin 1): connects to VA.
U1 (pin 2): connects to VB.
U1 (pin 3): connects to VOUT.
R3: connects between VOUT and the anode of D1.
D1: cathode connects to 0.

Conceptual block diagram

Schematic

VCC --> [ SW1: Bed A ] --(VA)--> [ R1: 10 kΩ Pull-down ] --> GND
                             \
                              -->(Pin 1) \
                                          [ U1: 74HC32 OR Gate ] --(VOUT, Pin 3)--> [ R3: 330 Ω ] --> [ D1: Red LED ] --> GND
                                          /
                              -->(Pin 2) /
                             /
VCC --> [ SW2: Bed B ] --(VB)--> [ R2: 10 kΩ Pull-down ] --> GND

Electrical Schematic

Truth table

Input A (`VA`)	Input B (`VB`)	Output Y (`VOUT`)	LED State
0 (LOW)	0 (LOW)	0 (LOW)	OFF
0 (LOW)	1 (HIGH)	1 (HIGH)	ON
1 (HIGH)	0 (LOW)	1 (HIGH)	ON
1 (HIGH)	1 (HIGH)	1 (HIGH)	ON

Measurements and tests

Power Verification: Measure the voltage between VCC and 0 using a multimeter to ensure it is exactly 5 V.
Idle State Testing: Without pressing any buttons, measure the voltage at nodes VA and VB. Both should read exactly 0 V. The node VOUT should also read 0 V.
Logic HIGH Testing: Press and hold SW1. Measure node VA (should be ~5 V) and measure node VOUT (should be ~5 V). Verify the LED is ON. Repeat this process for SW2 and node VB.
Current Measurement (Optional): Place your multimeter in series with R3 and D1 to measure the forward current of the LED (it should be roughly 8-10 mA depending on the LED’s forward voltage drop).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Nurse call bell
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Bed A Trigger (SW1)
* Modeled as a voltage-controlled switch activated by a pulse to simulate a user pressing the button
VctrlA ctrlA 0 PULSE(0 5 10u 1u 1u 40u 100u)
S1 VCC VA ctrlA 0 my_switch

* Bed B Trigger (SW2)
* Modeled as a voltage-controlled switch activated by a pulse to simulate a user pressing the button
VctrlB ctrlB 0 PULSE(0 5 10u 1u 1u 90u 200u)
S2 VCC VB ctrlB 0 my_switch

* Pull-down resistors for switch inputs
R1 VA 0 10k
R2 VB 0 10k

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

* Practical case: Nurse call bell
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Bed A Trigger (SW1)
* Modeled as a voltage-controlled switch activated by a pulse to simulate a user pressing the button
VctrlA ctrlA 0 PULSE(0 5 10u 1u 1u 40u 100u)
S1 VCC VA ctrlA 0 my_switch

* Bed B Trigger (SW2)
* Modeled as a voltage-controlled switch activated by a pulse to simulate a user pressing the button
VctrlB ctrlB 0 PULSE(0 5 10u 1u 1u 90u 200u)
S2 VCC VB ctrlB 0 my_switch

* Pull-down resistors for switch inputs
R1 VA 0 10k
R2 VB 0 10k

* U1: 74HC32 quad 2-input OR gate IC (using 1 gate)
* Wiring: Pin 1 -> VA, Pin 2 -> VB, Pin 3 -> VOUT, Pin 14 -> VCC, Pin 7 -> 0
XU1 VA VB VOUT VCC 0 74HC32_OR

* Alert Indicator (LED and current limiting resistor)
R3 VOUT D1_A 330
D1 D1_A 0 DLED

* --- Models and Subcircuits ---

* Ideal switch model
.model my_switch SW(vt=2.5 vh=0.5 ron=1 roff=100MEG)

* Generic Red LED model
.model DLED D(IS=1e-20 N=2.2 RS=2)

* Behavioral model for a 74HC32 OR gate (Continuous functions for robust convergence)
.subckt 74HC32_OR A B Y VCC GND
RinA A GND 10MEG
RinB B GND 10MEG
* OR Logic: V_out = VCC * (1 - (1-A)*(1-B)) implemented with sigmoids
B1 Y_int GND V = V(VCC) * (1 - (1 - 1/(1+exp(-50*(V(A)-2.5)))) * (1 - 1/(1+exp(-50*(V(B)-2.5)))))
Rout Y_int Y 10
.ends

* --- Analysis Directives ---

.tran 1u 250u
.print tran V(VA) V(VB) V(VOUT) V(D1_A)
.op
.end

Simulation Results (Transient Analysis)

Analysis: The transient analysis spans 0 s to 250 us and captures the switching interval. Main ranges: v(vout) -1.01e-29 uV -> 4.92 V; v(va) 499 uV -> 5 V; v(vb) 499 uV -> 5 V.

Show raw data table (354 rows)

Index   time            v(va)           v(vb)           v(vout)         v(d1_a)
0	0.000000e+00	4.994506e-04	4.994506e-04	-1.00582e-35	-3.41977e-34
1	1.000000e-08	4.994506e-04	4.994506e-04	-6.04520e-52	-2.05537e-50
2	2.000000e-08	4.994506e-04	4.994506e-04	6.045198e-52	2.055367e-50
3	4.000000e-08	4.994506e-04	4.994506e-04	1.816637e-67	6.176631e-66
4	8.000000e-08	4.994506e-04	4.994506e-04	-7.26682e-68	-2.47066e-66
5	1.600000e-07	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
6	3.200000e-07	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
7	6.400000e-07	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
8	1.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
9	2.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
10	3.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
11	4.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
12	5.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
13	6.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
14	7.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
15	8.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
16	9.280000e-06	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
17	1.000000e-05	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
18	1.010000e-05	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
19	1.030000e-05	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
20	1.035875e-05	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
21	1.046156e-05	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
22	1.049002e-05	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
23	1.053982e-05	4.994506e-04	4.994506e-04	-1.94609e-72	-1.94609e-72
... (330 more rows) ...

Reference SPICE netlist (ngspice)

* Practical case: Nurse call bell
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Bed A Trigger (SW1)
* Modeled as a voltage-controlled switch activated by a pulse to simulate a user pressing the button
VctrlA ctrlA 0 PULSE(0 5 10u 1u 1u 40u 100u)
S1 VCC VA ctrlA 0 my_switch

* Bed B Trigger (SW2)
* Modeled as a voltage-controlled switch activated by a pulse to simulate a user pressing the button
VctrlB ctrlB 0 PULSE(0 5 10u 1u 1u 90u 200u)
S2 VCC VB ctrlB 0 my_switch

* Pull-down resistors for switch inputs
R1 VA 0 10k
R2 VB 0 10k

* U1: 74HC32 quad 2-input OR gate IC (using 1 gate)
* Wiring: Pin 1 -> VA, Pin 2 -> VB, Pin 3 -> VOUT, Pin 14 -> VCC, Pin 7 -> 0
XU1 VA VB VOUT VCC 0 74HC32_OR

* Alert Indicator (LED and current limiting resistor)
R3 VOUT D1_A 330
D1 D1_A 0 DLED

* --- Models and Subcircuits ---

* Ideal switch model
.model my_switch SW(vt=2.5 vh=0.5 ron=1 roff=100MEG)

* Generic Red LED model
.model DLED D(IS=1e-20 N=2.2 RS=2)

* Behavioral model for a 74HC32 OR gate (Continuous functions for robust convergence)
.subckt 74HC32_OR A B Y VCC GND
RinA A GND 10MEG
RinB B GND 10MEG
* OR Logic: V_out = VCC * (1 - (1-A)*(1-B)) implemented with sigmoids
B1 Y_int GND V = V(VCC) * (1 - (1 - 1/(1+exp(-50*(V(A)-2.5)))) * (1 - 1/(1+exp(-50*(V(B)-2.5)))))
Rout Y_int Y 10
.ends

* --- Analysis Directives ---

.tran 1u 250u
.print tran V(VA) V(VB) V(VOUT) V(D1_A)
.op
.end

Simulation Results (Transient Analysis)

Analysis: The transient analysis spans 0 s to 250 us and captures the switching interval. Main ranges: v(vout) -1.01e-29 uV -> 4.92 V; v(va) 499 uV -> 5 V; v(vb) 499 uV -> 5 V.

Common mistakes and how to avoid them

Floating inputs: Forgetting the pull-down resistors (R1 and R2). Without them, the voltage at the gate inputs will float when the switches are open, causing random, unpredictable triggering of the alarm.
Omitting power connections to the IC: Forgetting to connect pins 7 and 14 to Ground and VCC, respectively. The logic gate cannot function without its own power supply.
Leaving unused CMOS inputs floating: The 74HC32 is a CMOS device. Any unused input pins (e.g., pins 4, 5, 9, 10, 12, 13) should be tied to Ground (0) to prevent excess power consumption or erratic behavior.

Troubleshooting

Symptom: The LED stays ON constantly, even when no buttons are pressed.
Cause: One of the pull-down resistors (R1 or R2) is missing or not properly connected to ground.
Fix: Verify the connection of the resistors between inputs VA or VB and node 0.
Symptom: The LED never turns ON.
Cause: LED is installed backward, missing VCC/GND to the IC, or a disconnected R3.
Fix: Check LED polarity (flat side / shorter leg goes to node 0). Ensure pins 7 and 14 on U1 have power.
Symptom: The LED turns ON randomly when my hand is near the breadboard.
Cause: The circuit is experiencing a «floating input» acting as an antenna picking up stray capacitance.
Fix: Check your pull-down resistors. Make sure they firmly connect the input pins to ground.
Symptom: Output is logic HIGH (measured at pin 3), but LED is extremely dim.
Cause: The current limiting resistor R3 is too large (e.g., 10 kΩ instead of 330 Ω).
Fix: Replace R3 with the correct 330 Ω value.

Possible improvements and extensions

Add an audible alert: Connect an active 5 V buzzer in parallel with the LED/resistor combination so that triggering the switch produces both a light and a sound.
Implement a latching circuit: In a real hospital, the light must stay ON until a nurse arrives to reset it. Feed the output of the OR gate into the SET pin of an SR Latch (or use logic gates to build one), and add a third «Reset» button at the nurse station.

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Practical case: 0-9 counter with TTL-compatible reset

0-9 counter with TTL-compatible reset prototype (Maker Style)

Level: Medium — Build a decimal counter that advances from 0 to 9 and resets automatically using a TTL-compatible AND gate.

Objective and use case

You will build a decimal counter based on a 74LS93 ripple counter and a 74HCT08 AND gate. The circuit counts from 0000 to 1001 and automatically resets when 1010 appears.

This is useful for:
– Simple event counters with a decimal display interface
– Clock divider stages for timing experiments
– Learning how asynchronous reset works in ripple counters
– Testing TTL-to-CMOS/HCT logic compatibility in mixed logic designs

Expected outcome:
– QA, QB, QC, and QD show a binary count sequence from 0 to 9
– RESET_NODE goes HIGH only when QB = 1 and QD = 1
– The counter clears immediately when state 1010 is reached
– LEDs on the four outputs visibly repeat the decimal cycle
– Logic supply remains at +5 V, with TTL-compatible levels between the 74LS93 and 74HCT08

Target audience and level: Students and technicians with basic digital electronics experience.

Materials

U1: 74LS93 4-bit ripple counter, function: binary count generation
U2: 74HCT08 quad 2-input AND gate, function: TTL-compatible reset detection
V1: 5 V DC supply, function: power for the logic circuit
X1: clock source 0-5 V square wave, function: CLK_IN signal
D1: red LED, function: QA indicator
D2: red LED, function: QB indicator
D3: red LED, function: QC indicator
D4: red LED, function: QD indicator
R1: 330 Ω resistor, function: current limiting for D1
R2: 330 Ω resistor, function: current limiting for D2
R3: 330 Ω resistor, function: current limiting for D3
R4: 330 Ω resistor, function: current limiting for D4
C1: 100 nF capacitor, function: local decoupling for U1
C2: 100 nF capacitor, function: local decoupling for U2

Pin-out of the IC used

74LS93

Pin	Name	Logic function	Connection in this case
5	VCC	+5 V supply	`VCC`
10	GND	Ground	`0`
14	CP0	Clock input A	`CLK_IN`
1	CP1	Clock input B	Connected to `QA` for cascade
2	R0(1)	Asynchronous reset input	`RESET_NODE`
3	R0(2)	Asynchronous reset input	`RESET_NODE`
12	QA	LSB output	`QA`, LED D1, and feedback to `CP1`
9	QB	Counter output	`QB`, LED D2, and reset detect input
8	QC	Counter output	`QC`, LED D3
11	QD	MSB output	`QD`, LED D4, and reset detect input

74HCT08

Pin	Name	Logic function	Connection in this case
14	VCC	+5 V supply	`VCC`
7	GND	Ground	`0`
1	1 A	AND input A	`QB`
2	1B	AND input B	`QD`
3	1Y	AND output	`RESET_NODE`

Wiring guide

V1 connects between VCC and 0.
C1 connects between VCC and 0, placed close to U1.
C2 connects between VCC and 0, placed close to U2.
U1 pin 5 connects to VCC.
U1 pin 10 connects to 0.
U1 pin 14 connects to CLK_IN.
U1 pin 1 connects to node QA.
U1 pin 2 connects to RESET_NODE.
U1 pin 3 connects to RESET_NODE.
U1 pin 12 connects to node QA.
U1 pin 9 connects to node QB.
U1 pin 8 connects to node QC.
U1 pin 11 connects to node QD.
U2 pin 14 connects to VCC.
U2 pin 7 connects to 0.
U2 pin 1 connects to node QB.
U2 pin 2 connects to node QD.
U2 pin 3 connects to node RESET_NODE.
R1 connects between QA and node LED1_A.
D1 connects between LED1_A and 0.
R2 connects between QB and node LED2_A.
D2 connects between LED2_A and 0.
R3 connects between QC and node LED3_A.
D3 connects between LED3_A and 0.
R4 connects between QD and node LED4_A.
D4 connects between LED4_A and 0.

Use the 74HCT08, not the 74HC08, because the reset gate is driven by 74LS93 TTL outputs and must accept TTL-compatible HIGH levels reliably.

Conceptual block diagram

Schematic

Practical case: 0-9 counter with TTL-compatible reset (74LS93 + 74HCT08)

[ X1: CLK_IN 0-5 V square ] --> [ U1: 74LS93 4-bit Ripple Counter (CP0 pin14) ]
(Internal to U1: QA (pin12) --> CP1 (pin1) for divide-by-10 configuration)

U1 Q outputs to indicators (loads on the right):
[ U1: QA (pin12) ] --> [ R1: 330 Ω ] --> [ D1: Red LED ] --> GND
[ U1: QB (pin9)  ] --> [ R2: 330 Ω ] --> [ D2: Red LED ] --> GND
[ U1: QC (pin8)  ] --> [ R3: 330 Ω ] --> [ D3: Red LED ] --> GND
[ U1: QD (pin11) ] --> [ R4: 330 Ω ] --> [ D4: Red LED ] --> GND

Reset detection (separate branches; TTL-compatible gate):
[ Tap: U1.QB (pin9) ] -->
[ Tap: U1.QD (pin11) ] --> [ U2: 74HCT08 AND (pins 1,2→3) ] --(RESET_NODE)--> (to U1 Async Reset R0(1),R0(2) pins 2 & 3)

Power and decoupling (for completeness):
[ V1: +5 V ] --> [ U1: VCC pin5 ]          ; return GND --> (U1 GND pin10)
[ V1: +5 V ] --> [ U2: VCC pin14 ]         ; return GND --> (U2 GND pin7)
[ C1: 100 nF ] between U1 VCC and GND (place close to U1)
[ C2: 100 nF ] between U2 VCC and GND (place close to U2)

Electrical Schematic

Electrical diagram

🔒 This electrical diagram is premium. With the monthly membership (7-day free trial) you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Truth table

This table corresponds to the AND gate used for reset detection.

QB	QD	RESET_NODE
0	0	0
0	1	0
1	0	0
1	1	1

Measurements and tests

Power-off continuity check
Verify VCC is not shorted to 0.
Confirm U1 reset pins 2 and 3 are tied together at RESET_NODE.
Confirm U1 pin 1 is connected to QA.
Power-on static check
Apply +5 V.
Check that U1 and U2 both receive correct supply voltage.
With no clock applied, outputs may start in an unknown state; a brief manual reset to RESET_NODE = HIGH should force QA QB QC QD = 0000.
Clock verification
Measure CLK_IN with an oscilloscope.
Use a slow frequency such as 1 Hz to 10 Hz for visual LED observation.
Confirm the clock swings approximately from 0 V to 5 V.
Counter sequence check
Measure QA, QB, QC, and QD.
Verify the sequence:
- 0000
- 0001
- 0010
- 0011
- 0100
- 0101
- 0110
- 0111
- 1000
- 1001
The next attempted state is 1010, but it must reset immediately to 0000.
Reset-node validation
Measure RESET_NODE.
It should remain LOW for counts 0000 through 1001.
It should pulse HIGH when QB = 1 and QD = 1, which corresponds to detection of 1010.
LED observation
D1 must toggle at the highest visible rate.
D2 toggles at half the QA rate.
D3 and D4 toggle progressively slower.
The visible pattern must repeat every 10 clock pulses.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Decade counter 0-9 with reset (Corrected)
.width out=256
* Fixed Impedance and Timing issues for 74LS93 ripple counter
* Ngspice compliant netlist

* --- COMPONENT MODELS ---
* Generic Red LED Model
.model DLED D(IS=1e-14 N=1.7 RS=10 BV=5 IBV=10u CJO=10p)

* --- LOGIC GATE SUBCIRCUITS (Behavioral with Low Impedance Output) ---
* IMPORTANT: Output Impedance reduced to 50 ohms to drive LEDs and avoid loading effects.
* Delays (C1=10p) maintained for convergence and latch feedback.

* Inverter (Standard Delay ~500ps)
.subckt INV A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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🔓 See premium access plans

* Practical case: Decade counter 0-9 with reset (Corrected)
.width out=256
* Fixed Impedance and Timing issues for 74LS93 ripple counter
* Ngspice compliant netlist

* --- COMPONENT MODELS ---
* Generic Red LED Model
.model DLED D(IS=1e-14 N=1.7 RS=10 BV=5 IBV=10u CJO=10p)

* --- LOGIC GATE SUBCIRCUITS (Behavioral with Low Impedance Output) ---
* IMPORTANT: Output Impedance reduced to 50 ohms to drive LEDs and avoid loading effects.
* Delays (C1=10p) maintained for convergence and latch feedback.

* Inverter (Standard Delay ~500ps)
.subckt INV A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* Fast Inverter (Minimal Delay ~5ps) - Used for Clock Edge logic to prevent races
.subckt INV_FAST A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 0.1p
.ends

* 2-Input NAND
.subckt NAND2 A B Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) ))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* 3-Input NAND
.subckt NAND3 A B C Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) * (1/(1+exp(-20*(V(C)-2.5)))) ))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* 2-Input AND
.subckt AND2 A B Y VCC GND
B1 Y_int 0 V = V(VCC) * ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) )
R1 Y_int Y 50
C1 Y 0 10p
.ends

* --- FLIP-FLOP SUBCIRCUIT ---
* T-FlipFlop: Negative Edge Triggered with Active High Clear
* Uses INV_FAST for clock inversion to ensure Master-Slave non-overlap (Race Fix).
.subckt TFF_NEG_CLR CLK CLR Q QBAR VCC GND
* Invert Clear
XINV_CLR CLR CLR_BAR VCC GND INV

* Invert Clock FAST (Avoids race where both Master and Slave are transparent)
XINV_CLK CLK CLK_BAR VCC GND INV_FAST

* -- Master Latch (Tracks D=QBAR when CLK=1) --
XG1 QBAR CLK M_SET_BAR VCC GND NAND2
XG2 Q CLK CLR_BAR M_RST_BAR VCC GND NAND3
XL1 M_SET_BAR M_QBAR M_Q VCC GND NAND2
XL2 M_RST_BAR M_Q CLR_BAR M_QBAR VCC GND NAND3

* -- Slave Latch (Tracks Master when CLK=0 -> CLK_BAR=1) --
* Uses CLK_BAR which is delayed only slightly less than gates, ensuring clean handover.
XG3 M_Q CLK_BAR S_SET_BAR VCC GND NAND2
XG4 M_QBAR CLK_BAR S_RST_BAR VCC GND NAND2
XL3 S_SET_BAR QBAR Q VCC GND NAND2
XL4 S_RST_BAR Q CLR_BAR QBAR VCC GND NAND3
.ends

* --- IC SUBCIRCUITS ---

* U1: 74LS93 4-Bit Binary Counter
* Pinout mapping adjusted to match standard 14-pin DIP in netlist order:
* 1=IN_B, 2=R0(1), 3=R0(2), 5=VCC, 8=QC, 9=QB, 10=GND, 11=QD, 12=QA, 14=IN_A
.subckt 74LS93 IN_B R0_1 R0_2 VCC QC QB GND QD QA IN_A
* Internal Reset Logic: Reset if R0_1 AND R0_2 are High
XAND_RST R0_1 R0_2 RESET VCC GND AND2

* Section 1: 1-bit counter (Input A -> QA)
XFFA IN_A RESET QA QA_BAR VCC GND TFF_NEG_CLR

* Section 2: 3-bit ripple counter (Input B -> QB -> QC -> QD)
XFFB IN_B RESET QB QB_BAR VCC GND TFF_NEG_CLR
XFFC QB RESET QC QC_BAR VCC GND TFF_NEG_CLR
XFFD QC RESET QD QD_BAR VCC GND TFF_NEG_CLR
.ends

* U2: 74HCT08 Quad 2-Input AND Gate
* HCT input thresholds are TTL-compatible, so 74LS93 HIGH outputs
* reliably drive the reset-detect gate in a real classroom build.
* Pins: 1=1A, 2=1B, 3=1Y, 7=GND, 14=VCC
.subckt 74HCT08 1A 1B 1Y GND VCC
XG1 1A 1B 1Y VCC GND AND2
.ends

* --- MAIN CIRCUIT ---

* 1. Power Supply
V1 VCC 0 DC 5

* 2. Clock Signal (50kHz)
V2 CLK_IN 0 PULSE(0 5 1u 100n 100n 10u 20u)

* 3. U1: 74LS93 Counter
* Wiring Guide connections:
* Pin 1 (CKB) connects to QA_NODE (Cascade)
* Pin 12 (QA) connects to QA_NODE
* Pin 14 (CKA) connects to CLK_IN
* Pin 2, 3 connect to RESET_NODE
* Outputs to LEDs
XU1 QA_NODE RESET_NODE RESET_NODE VCC QC_NODE QB_NODE 0 QD_NODE QA_NODE CLK_IN 74LS93

* 4. U2: 74HCT08 Reset Logic
* Reset when Count=10 (Binary 1010 -> QD=1, QB=1)
* Inputs: QB_NODE, QD_NODE -> Output: RESET_NODE
XU2 QB_NODE QD_NODE RESET_NODE 0 VCC 74HCT08

* 5. LED Indicators (with Current Limiting Resistors)
* Bit 0 (QA)
R1 QA_NODE N_D1 330
D1 N_D1 0 DLED

* Bit 1 (QB)
R2 QB_NODE N_D2 330
D2 N_D2 0 DLED

* Bit 2 (QC)
R3 QC_NODE N_D3 330
D3 N_D3 0 DLED

* Bit 3 (QD)
R4 QD_NODE N_D4 330
D4 N_D4 0 DLED

* --- SIMULATION COMMANDS ---
.op
* Transient analysis: 500us to see counts 0-9 and reset
.tran 100n 500u

* Print essential nodes. CLK_IN first.
.print tran V(CLK_IN) V(QA_NODE) V(QB_NODE) V(QC_NODE) V(QD_NODE) V(RESET_NODE)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation successfully demonstrates a 4-bit counting sequence. The counter increments on the falling edge of the clock. The reset logic triggers correctly when the count reaches 10 (Binary 1010: QD=High, QB=High), forcing the outputs back to 0 immediately, effectively creating a 0-9 decade counter.
* bom_vs_spice equivalences ignored:
*   - Clock source V2 modeled as a PULSE voltage source.
*   - LEDs (D1-D4) modeled as generic diodes with specific parameters (DLED).
*   - U1 (74LS93) modeled as a behavioral subcircuit using flip-flops and logic gates.
*   - U2 (74HCT08) modeled as a behavioral subcircuit using AND gates.
* overall_comment: The circuit is well-designed and the SPICE netlist accurately reflects the intended decade counter logic. The behavioral models for the 74LS93 and 74HCT08 are robust, including necessary delays to prevent race conditions. The simulation logs confirm the modulo-10 reset operation works as expected. This is a solid didactic example.
* --------------------------------------

Simulation Results (Transient Analysis)

Analysis: The simulation successfully demonstrates a 4-bit counting sequence. The counter increments on the falling edge of the clock. The reset logic triggers correctly when the count reaches 10 (Binary 1010: QD=High, QB=High), forcing the outputs back to 0 immediately, effectively creating a 0-9 decade counter.

Show raw data table (6785 rows)

Index   time            v(clk_in)       v(qa_node)      v(qb_node)      v(qc_node)      v(qd_node)      v(reset_node)
0	0.000000e+00	0.000000e+00	-7.27413e-30	4.514570e+00	-7.27413e-30	-7.27411e-30	9.643749e-22
1	1.000000e-09	0.000000e+00	-6.24961e-30	4.514570e+00	-6.24960e-30	-6.24960e-30	9.643749e-22
2	2.000000e-09	0.000000e+00	-4.31599e-30	4.514570e+00	-4.31599e-30	-4.31599e-30	9.643749e-22
3	4.000000e-09	0.000000e+00	-8.63940e-32	4.514570e+00	-8.63867e-32	-8.63940e-32	9.643749e-22
4	8.000000e-09	0.000000e+00	6.051302e-30	4.514570e+00	6.051309e-30	6.051302e-30	9.643749e-22
5	1.600000e-08	0.000000e+00	8.619372e-30	4.514570e+00	8.619381e-30	8.619372e-30	9.643749e-22
6	3.200000e-08	0.000000e+00	4.420001e-30	4.514570e+00	4.420001e-30	4.419984e-30	9.643749e-22
7	6.400000e-08	0.000000e+00	-8.88725e-31	4.514570e+00	-8.88725e-31	-8.88708e-31	9.643749e-22
8	1.280000e-07	0.000000e+00	-1.16882e-30	4.514570e+00	-1.16881e-30	-1.16884e-30	9.643749e-22
9	2.280000e-07	0.000000e+00	-1.70113e-31	4.514570e+00	-1.70131e-31	-1.70113e-31	9.643749e-22
10	3.280000e-07	0.000000e+00	1.102262e-31	4.514570e+00	1.101893e-31	1.102078e-31	9.643749e-22
11	4.280000e-07	0.000000e+00	-2.09740e-32	4.514570e+00	-2.09440e-32	-2.09556e-32	9.643749e-22
12	5.280000e-07	0.000000e+00	3.730926e-32	4.514570e+00	3.729081e-32	3.729081e-32	9.643749e-22
13	6.280000e-07	0.000000e+00	-4.04764e-32	4.514570e+00	-4.04464e-32	-4.04395e-32	9.643749e-22
14	7.280000e-07	0.000000e+00	3.793658e-32	4.514570e+00	3.789968e-32	3.791813e-32	9.643749e-22
15	8.280000e-07	0.000000e+00	-3.71737e-32	4.514570e+00	-3.71437e-32	-3.71552e-32	9.643749e-22
16	9.280000e-07	0.000000e+00	3.658968e-32	4.514570e+00	3.657123e-32	3.658968e-32	9.643749e-22
17	1.000000e-06	0.000000e+00	-3.53679e-32	4.514570e+00	-3.53610e-32	-3.53496e-32	9.643749e-22
18	1.010000e-06	5.000000e-01	-2.79091e-33	4.514570e+00	-2.80820e-33	-2.79091e-33	9.643749e-22
19	1.030000e-06	1.500000e+00	1.602683e-33	4.514570e+00	1.585385e-33	1.602683e-33	9.643749e-22
20	1.048757e-06	2.437856e+00	4.312441e+00	4.514570e+00	-1.25584e-33	-1.27306e-33	9.643749e-22
21	1.062135e-06	3.106726e+00	4.691659e+00	4.514570e+00	1.096887e-33	1.103161e-33	9.643749e-22
22	1.071814e-06	3.590675e+00	4.366639e+00	4.514570e+00	-8.23695e-34	-8.33794e-34	9.643749e-22
23	1.080871e-06	4.043525e+00	4.636207e+00	4.514570e+00	6.872047e-34	7.032322e-34	9.643749e-22
... (6761 more rows) ...

Reference SPICE netlist (ngspice)

* Practical case: Decade counter 0-9 with reset (Corrected)
.width out=256
* Fixed Impedance and Timing issues for 74LS93 ripple counter
* Ngspice compliant netlist

* --- COMPONENT MODELS ---
* Generic Red LED Model
.model DLED D(IS=1e-14 N=1.7 RS=10 BV=5 IBV=10u CJO=10p)

* --- LOGIC GATE SUBCIRCUITS (Behavioral with Low Impedance Output) ---
* IMPORTANT: Output Impedance reduced to 50 ohms to drive LEDs and avoid loading effects.
* Delays (C1=10p) maintained for convergence and latch feedback.

* Inverter (Standard Delay ~500ps)
.subckt INV A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* Fast Inverter (Minimal Delay ~5ps) - Used for Clock Edge logic to prevent races
.subckt INV_FAST A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 0.1p
.ends

* 2-Input NAND
.subckt NAND2 A B Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) ))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* 3-Input NAND
.subckt NAND3 A B C Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) * (1/(1+exp(-20*(V(C)-2.5)))) ))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* 2-Input AND
.subckt AND2 A B Y VCC GND
B1 Y_int 0 V = V(VCC) * ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) )
R1 Y_int Y 50
C1 Y 0 10p
.ends

* --- FLIP-FLOP SUBCIRCUIT ---
* T-FlipFlop: Negative Edge Triggered with Active High Clear
* Uses INV_FAST for clock inversion to ensure Master-Slave non-overlap (Race Fix).
.subckt TFF_NEG_CLR CLK CLR Q QBAR VCC GND
* Invert Clear
XINV_CLR CLR CLR_BAR VCC GND INV

* Invert Clock FAST (Avoids race where both Master and Slave are transparent)
XINV_CLK CLK CLK_BAR VCC GND INV_FAST

* -- Master Latch (Tracks D=QBAR when CLK=1) --
XG1 QBAR CLK M_SET_BAR VCC GND NAND2
XG2 Q CLK CLR_BAR M_RST_BAR VCC GND NAND3
XL1 M_SET_BAR M_QBAR M_Q VCC GND NAND2
XL2 M_RST_BAR M_Q CLR_BAR M_QBAR VCC GND NAND3

* -- Slave Latch (Tracks Master when CLK=0 -> CLK_BAR=1) --
* Uses CLK_BAR which is delayed only slightly less than gates, ensuring clean handover.
XG3 M_Q CLK_BAR S_SET_BAR VCC GND NAND2
XG4 M_QBAR CLK_BAR S_RST_BAR VCC GND NAND2
XL3 S_SET_BAR QBAR Q VCC GND NAND2
XL4 S_RST_BAR Q CLR_BAR QBAR VCC GND NAND3
.ends

* --- IC SUBCIRCUITS ---

* U1: 74LS93 4-Bit Binary Counter
* Pinout mapping adjusted to match standard 14-pin DIP in netlist order:
* 1=IN_B, 2=R0(1), 3=R0(2), 5=VCC, 8=QC, 9=QB, 10=GND, 11=QD, 12=QA, 14=IN_A
.subckt 74LS93 IN_B R0_1 R0_2 VCC QC QB GND QD QA IN_A
* Internal Reset Logic: Reset if R0_1 AND R0_2 are High
XAND_RST R0_1 R0_2 RESET VCC GND AND2

* Section 1: 1-bit counter (Input A -> QA)
XFFA IN_A RESET QA QA_BAR VCC GND TFF_NEG_CLR

* Section 2: 3-bit ripple counter (Input B -> QB -> QC -> QD)
XFFB IN_B RESET QB QB_BAR VCC GND TFF_NEG_CLR
XFFC QB RESET QC QC_BAR VCC GND TFF_NEG_CLR
XFFD QC RESET QD QD_BAR VCC GND TFF_NEG_CLR
.ends

* U2: 74HCT08 Quad 2-Input AND Gate
* HCT input thresholds are TTL-compatible, so 74LS93 HIGH outputs
* reliably drive the reset-detect gate in a real classroom build.
* Pins: 1=1A, 2=1B, 3=1Y, 7=GND, 14=VCC
.subckt 74HCT08 1A 1B 1Y GND VCC
XG1 1A 1B 1Y VCC GND AND2
.ends

* --- MAIN CIRCUIT ---

* 1. Power Supply
V1 VCC 0 DC 5

* 2. Clock Signal (50kHz)
V2 CLK_IN 0 PULSE(0 5 1u 100n 100n 10u 20u)

* 3. U1: 74LS93 Counter
* Wiring Guide connections:
* Pin 1 (CKB) connects to QA_NODE (Cascade)
* Pin 12 (QA) connects to QA_NODE
* Pin 14 (CKA) connects to CLK_IN
* Pin 2, 3 connect to RESET_NODE
* Outputs to LEDs
XU1 QA_NODE RESET_NODE RESET_NODE VCC QC_NODE QB_NODE 0 QD_NODE QA_NODE CLK_IN 74LS93

* 4. U2: 74HCT08 Reset Logic
* Reset when Count=10 (Binary 1010 -> QD=1, QB=1)
* Inputs: QB_NODE, QD_NODE -> Output: RESET_NODE
XU2 QB_NODE QD_NODE RESET_NODE 0 VCC 74HCT08

* 5. LED Indicators (with Current Limiting Resistors)
* Bit 0 (QA)
R1 QA_NODE N_D1 330
D1 N_D1 0 DLED

* Bit 1 (QB)
R2 QB_NODE N_D2 330
D2 N_D2 0 DLED

* Bit 2 (QC)
R3 QC_NODE N_D3 330
D3 N_D3 0 DLED

* Bit 3 (QD)
R4 QD_NODE N_D4 330
D4 N_D4 0 DLED

* --- SIMULATION COMMANDS ---
.op
* Transient analysis: 500us to see counts 0-9 and reset
.tran 100n 500u

* Print essential nodes. CLK_IN first.
.print tran V(CLK_IN) V(QA_NODE) V(QB_NODE) V(QC_NODE) V(QD_NODE) V(RESET_NODE)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation successfully demonstrates a 4-bit counting sequence. The counter increments on the falling edge of the clock. The reset logic triggers correctly when the count reaches 10 (Binary 1010: QD=High, QB=High), forcing the outputs back to 0 immediately, effectively creating a 0-9 decade counter.
* bom_vs_spice equivalences ignored:
*   - Clock source V2 modeled as a PULSE voltage source.
*   - LEDs (D1-D4) modeled as generic diodes with specific parameters (DLED).
*   - U1 (74LS93) modeled as a behavioral subcircuit using flip-flops and logic gates.
*   - U2 (74HCT08) modeled as a behavioral subcircuit using AND gates.
* overall_comment: The circuit is well-designed and the SPICE netlist accurately reflects the intended decade counter logic. The behavioral models for the 74LS93 and 74HCT08 are robust, including necessary delays to prevent race conditions. The simulation logs confirm the modulo-10 reset operation works as expected. This is a solid didactic example.
* --------------------------------------

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

Using 74HC08 instead of 74HCT08
Problem: the 74LS93 HIGH level may not meet standard HC input thresholds reliably.
Solution: use 74HCT08 for TTL-compatible input levels.
Forgetting the QA to CP1 connection
Problem: the 74LS93 will not count correctly through the intended 4-bit sequence.
Solution: connect U1 pin 12 (QA) directly to U1 pin 1 (CP1).
Reset inputs not tied together
Problem: the counter may not clear when 1010 occurs.
Solution: connect both R0(1) and R0(2) to the same RESET_NODE.

Troubleshooting

Symptom: The count goes beyond 9.
Cause: QB or QD is not correctly connected to the AND gate.
Fix: verify U2 pin 1 = QB, U2 pin 2 = QD, and U2 pin 3 = RESET_NODE.
Symptom: The circuit never counts.
Cause: RESET_NODE is stuck HIGH.
Fix: check for miswiring, shorts, or swapped AND gate pins.
Symptom: LEDs behave randomly at power-up.
Cause: ripple counters can power up in an undefined state.
Fix: apply a short reset pulse at startup.
Symptom: Reset is unreliable.
Cause: wrong logic family used for the reset gate.
Fix: replace any 74HC08 with 74HCT08.
Symptom: Only the first stage toggles.
Cause: missing cascade connection from QA to CP1.
Fix: reconnect U1 pin 12 to U1 pin 1.

Possible improvements and extensions

Add a BCD-to-7-segment decoder and display so the count is shown directly as digits 0 to 9.
Replace the clock source with a debounced push-button for manual stepping and observation of each state.

More Practical Cases on Prometeo.blog

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Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: astable oscillator with NE555

Astable oscillator with NE555 prototype (Maker Style)

Level: Basic — Build an NE555 astable timer that blinks an LED at a visible frequency.

Objective and use case

You will build a simple astable timer with an NE555 powered from 5 V. The circuit will generate a repetitive square wave that turns an LED on and off continuously.

Why it is useful:
– It demonstrates how a basic timer generates a clock signal without a microcontroller.
– It is useful as a visual blink indicator for power or system status.
– It can be used as a simple test source for checking frequency measurement tools.
– It helps students observe capacitor charge and discharge behavior in a real circuit.

Expected outcome:
– VOUT switches between approximately 0 V and 5 V.
– The LED blinks at a clearly visible rate, about 1 Hz to 3 Hz.
– The timing node TH_TR shows a repeating charge/discharge waveform between about 1/3 VCC and 2/3 VCC.
– The measured period is close to the value predicted by the NE555 astable equations.
– The duty cycle is greater than 50% for the standard RA/RB astable connection.

Target audience and level: Beginners in basic electronics laboratory practice.

Materials

U1: NE555 timer IC, function: astable oscillator core
R1: 10 kΩ resistor, function: timing resistor RA from VCC to DIS
R2: 68 kΩ resistor, function: timing resistor RB from DIS to TH_TR
C1: 10 µF electrolytic capacitor, function: timing capacitor
C2: 10 nF capacitor, function: control-voltage noise filter on CV
C3: 100 nF capacitor, function: supply decoupling across VCC and GND
R3: 330 Ω resistor, function: LED current limiting
D1: red LED, function: visual output indicator
V1: 5 V DC supply
B1: breadboard, function: circuit assembly platform
J1: jumper wires, function: interconnections

Wiring guide

Use the node names VCC, 0, DIS, TH_TR, CV, RESET, and VOUT.

V1 connects between nodes VCC and 0.
U1 pin 8 (VCC) connects to node VCC.
U1 pin 1 (GND) connects to node 0.
U1 pin 4 (RESET) connects to node VCC.
U1 pin 3 (OUT) connects to node VOUT.
U1 pin 7 (DISCH) connects to node DIS.
U1 pin 2 (TRIG) connects to node TH_TR.
U1 pin 6 (THRESH) connects to node TH_TR.
U1 pin 5 (CTRL) connects to node CV.
R1 connects between nodes VCC and DIS.
R2 connects between nodes DIS and TH_TR.
C1 connects between nodes TH_TR and 0; if electrolytic, connect the positive lead to TH_TR and the negative lead to 0.
C2 connects between nodes CV and 0.
C3 connects between nodes VCC and 0, placed physically close to U1.
R3 connects between nodes VOUT and LED_A.
D1 connects between nodes LED_A and 0; connect the anode to LED_A and the cathode to 0.

Conceptual block diagram

Schematic

Practical case: astable oscillator with NE555

[ V1: 5 V DC ] --(+)--> [ VCC ]
[ V1: 5 V DC ] --(-)--> [ 0 ]

[ VCC ] --(pin8 supply)--> [ U1: NE555 astable core ] --(pin3 = VOUT)--> [ R3: 330 ohm ] --(LED_A)--> [ D1: Red LED ] --> [ 0 ]
[ VCC ] --(RESET to pin4)--> [ U1: NE555 astable core ]
[ VCC ] --(R1: 10 k ohm, RA)--> [ DIS / U1 pin7 ] --(R2: 68 k ohm, RB)--> [ TH_TR / U1 pins2+6 ] --(timing sense)--> [ U1: NE555 astable core ]
[ TH_TR / U1 pins2+6 ] --(C1: 10 uF, + to TH_TR, - to 0)--> [ 0 ]
[ U1 pin5 = CV ] --(C2: 10 nF noise filter to 0)--> [ 0 ]
[ VCC ] --(C3: 100 nF decoupling to 0, close to U1)--> [ 0 ]
[ U1 pin1 = GND ] --> [ 0 ]

Electrical Schematic

Electrical diagram

Measurements and tests

Power-off inspection
Check that U1 pin 1 goes to 0 and U1 pin 8 goes to VCC.
Verify that U1 pin 2 and U1 pin 6 are linked together at TH_TR.
Confirm LED polarity: anode toward R3, cathode toward 0.
Initial power test
Apply 5 V from V1.
The LED should start blinking immediately.
If the LED stays always on or always off, remove power and recheck wiring.
Measure output voltage
Probe VOUT with a multimeter or oscilloscope.
With an oscilloscope, expect a square-like waveform from near 0 V to near 5 V.
With a multimeter, the reading may show an average voltage between these limits, depending on blink speed.
Measure the timing node
Probe TH_TR.
Expect a repeating capacitor waveform rising from about 1.67 V to 3.33 V when VCC = 5 V.
This confirms the internal 1/3 VCC and 2/3 VCC thresholds of the NE555.
Check the control-voltage node
Probe CV.
Expect a nearly steady voltage close to 2/3 VCC, around 3.3 V, with small ripple.
Estimate period and frequency
Use the standard astable equations:
T = 0.693 x (R1 + 2R2) x C1
f = 1 / T
With R1 = 10 kΩ, R2 = 68 kΩ, C1 = 10 µF:
T ≈ 0.693 x (10k + 136k) x 10 µF ≈ 1.01 s
f ≈ 0.99 Hz
Measured blinking should be close to 1 blink per second.
Estimate duty cycle
Use:
tHIGH = 0.693 x (R1 + R2) x C1
tLOW = 0.693 x R2 x C1
Duty cycle ≈ tHIGH / T
For these values, duty cycle is about 53%.
On the oscilloscope, the high time should be slightly longer than the low time.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Astable oscillator with NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* NE555 Timer IC Subcircuit Instance
* Pins: GND TRIG OUT RESET CTRL THRES DISCH VCC_PIN
XU1 0 TH_TR VOUT VCC CV TH_TR DISCH VCC NE555

* Timing Components
R1 VCC DISCH 10k
R2 DISCH TH_TR 47k
C1 TH_TR 0 10u
C2 CV 0 10n

* Output Load (LED)
R3 VOUT LED_A 330
D1 LED_A 0 DLED

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔓 See premium access plans

* Practical case: Astable oscillator with NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* NE555 Timer IC Subcircuit Instance
* Pins: GND TRIG OUT RESET CTRL THRES DISCH VCC_PIN
XU1 0 TH_TR VOUT VCC CV TH_TR DISCH VCC NE555

* Timing Components
R1 VCC DISCH 10k
R2 DISCH TH_TR 47k
C1 TH_TR 0 10u
C2 CV 0 10n

* Output Load (LED)
R3 VOUT LED_A 330
D1 LED_A 0 DLED

* Models
.MODEL DLED D(IS=1e-19 N=1.6 RS=10 BV=5 IBV=10u)

* Behavioral NE555 Subcircuit
.SUBCKT NE555 GND TRIG OUT RESET CTRL THRES DISCH VCC_PIN
* Internal voltage divider (3 x 5k resistors)
R1 VCC_PIN CTRL 5k
R2 CTRL N1 5k
R3 N1 GND 5k

* Smooth comparators for threshold, trigger, and reset
B_COMP_TH COMP_TH GND V=0.5*(1+tanh(100*(V(THRES,GND)-V(CTRL,GND))))
B_COMP_TR COMP_TR GND V=0.5*(1+tanh(100*(V(N1,GND)-V(TRIG,GND))))
B_COMP_RST COMP_RST GND V=0.5*(1+tanh(100*(0.7-V(RESET,GND))))

* SR Latch (Integrator with positive feedback for infinite hold time)
B_LATCH GND LATCH I=V(COMP_TR,GND) - V(COMP_TH,GND) - 5*V(COMP_RST,GND) + (V(LATCH,GND)>0.5 ? 0.1 : -0.1)
C_LATCH LATCH GND 1n
R_LATCH LATCH GND 100Meg

* Latch Voltage Clamps (Clamps V(LATCH) between ~0V and ~1V)
D1 GND LATCH D_CLAMP
V_CLAMP V_CLAMP_NODE GND 1
D2 LATCH V_CLAMP_NODE D_CLAMP
.model D_CLAMP D(N=0.01 RS=1)

* Output Driver Stage
B_OUT OUT_INT GND V=V(LATCH,GND)>0.5 ? V(VCC_PIN,GND) : 0.1
R_OUT OUT_INT OUT 10

* Open-Collector Discharge Transistor (Modeled as a Switch)
B_DISCH_CTRL DISCH_CTRL GND V=V(LATCH,GND)<0.5 ? 1 : 0
S_DISCH DISCH GND DISCH_CTRL GND SW_DISCH
.model SW_DISCH SW(VT=0.5 RON=15 ROFF=100Meg)
.ENDS

* Force initial condition on timing capacitor to ensure guaranteed oscillator startup
.ic V(TH_TR)=0

* Simulation Commands
.op
.tran 1m 3
.print tran V(VOUT) V(TH_TR) V(DISCH) V(LED_A) V(CV)

Simulation Results (Transient Analysis)

Analysis: The transient analysis spans 0 s to 3 s. Main ranges: v(vout) 100 mV -> 4.9 V; v(disch) 8.02 mV -> 4.71 V; v(th_tr) 0 uV -> 3.32 V.

Show raw data table (3013 rows)

Index   time            v(vout)         v(th_tr)        v(disch)        v(led_a)        v(cv)
0	0.000000e+00	4.903386e+00	0.000000e+00	4.122467e+00	1.715117e+00	3.333333e+00
1	1.000000e-05	4.903386e+00	8.771053e-05	4.122482e+00	1.715117e+00	3.333333e+00
2	2.000000e-05	4.903386e+00	1.754195e-04	4.122498e+00	1.715117e+00	3.333333e+00
3	4.000000e-05	4.903386e+00	3.508344e-04	4.122529e+00	1.715117e+00	3.333333e+00
4	8.000000e-05	4.903386e+00	7.016457e-04	4.122590e+00	1.715117e+00	3.333333e+00
5	1.600000e-04	4.903386e+00	1.403195e-03	4.122713e+00	1.715117e+00	3.333333e+00
6	3.200000e-04	4.903386e+00	2.805997e-03	4.122959e+00	1.715117e+00	3.333333e+00
7	6.400000e-04	4.903386e+00	5.610420e-03	4.123451e+00	1.715117e+00	3.333333e+00
8	1.280000e-03	4.903386e+00	1.121455e-02	4.124434e+00	1.715117e+00	3.333333e+00
9	2.280000e-03	4.903386e+00	1.995841e-02	4.125968e+00	1.715117e+00	3.333333e+00
10	3.280000e-03	4.903386e+00	2.868694e-02	4.127499e+00	1.715117e+00	3.333333e+00
11	4.280000e-03	4.903386e+00	3.740018e-02	4.129028e+00	1.715117e+00	3.333333e+00
12	5.280000e-03	4.903386e+00	4.609814e-02	4.130554e+00	1.715117e+00	3.333333e+00
13	6.280000e-03	4.903386e+00	5.478085e-02	4.132077e+00	1.715117e+00	3.333333e+00
14	7.280000e-03	4.903386e+00	6.344835e-02	4.133597e+00	1.715117e+00	3.333333e+00
15	8.280000e-03	4.903386e+00	7.210065e-02	4.135115e+00	1.715117e+00	3.333333e+00
16	9.280000e-03	4.903386e+00	8.073778e-02	4.136630e+00	1.715117e+00	3.333333e+00
17	1.028000e-02	4.903386e+00	8.935978e-02	4.138143e+00	1.715117e+00	3.333333e+00
18	1.128000e-02	4.903386e+00	9.796666e-02	4.139653e+00	1.715117e+00	3.333333e+00
19	1.228000e-02	4.903386e+00	1.065585e-01	4.141160e+00	1.715117e+00	3.333333e+00
20	1.328000e-02	4.903386e+00	1.151352e-01	4.142665e+00	1.715117e+00	3.333333e+00
21	1.428000e-02	4.903386e+00	1.236969e-01	4.144166e+00	1.715117e+00	3.333333e+00
22	1.528000e-02	4.903386e+00	1.322436e-01	4.145666e+00	1.715117e+00	3.333333e+00
23	1.628000e-02	4.903386e+00	1.407753e-01	4.147162e+00	1.715117e+00	3.333333e+00
... (2989 more rows) ...

Reference SPICE netlist (ngspice)

* Practical case: Astable oscillator with NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* NE555 Timer IC Subcircuit Instance
* Pins: GND TRIG OUT RESET CTRL THRES DISCH VCC_PIN
XU1 0 TH_TR VOUT VCC CV TH_TR DISCH VCC NE555

* Timing Components
R1 VCC DISCH 10k
R2 DISCH TH_TR 47k
C1 TH_TR 0 10u
C2 CV 0 10n

* Output Load (LED)
R3 VOUT LED_A 330
D1 LED_A 0 DLED

* Models
.MODEL DLED D(IS=1e-19 N=1.6 RS=10 BV=5 IBV=10u)

* Behavioral NE555 Subcircuit
.SUBCKT NE555 GND TRIG OUT RESET CTRL THRES DISCH VCC_PIN
* Internal voltage divider (3 x 5k resistors)
R1 VCC_PIN CTRL 5k
R2 CTRL N1 5k
R3 N1 GND 5k

* Smooth comparators for threshold, trigger, and reset
B_COMP_TH COMP_TH GND V=0.5*(1+tanh(100*(V(THRES,GND)-V(CTRL,GND))))
B_COMP_TR COMP_TR GND V=0.5*(1+tanh(100*(V(N1,GND)-V(TRIG,GND))))
B_COMP_RST COMP_RST GND V=0.5*(1+tanh(100*(0.7-V(RESET,GND))))

* SR Latch (Integrator with positive feedback for infinite hold time)
B_LATCH GND LATCH I=V(COMP_TR,GND) - V(COMP_TH,GND) - 5*V(COMP_RST,GND) + (V(LATCH,GND)>0.5 ? 0.1 : -0.1)
C_LATCH LATCH GND 1n
R_LATCH LATCH GND 100Meg

* Latch Voltage Clamps (Clamps V(LATCH) between ~0V and ~1V)
D1 GND LATCH D_CLAMP
V_CLAMP V_CLAMP_NODE GND 1
D2 LATCH V_CLAMP_NODE D_CLAMP
.model D_CLAMP D(N=0.01 RS=1)

* Output Driver Stage
B_OUT OUT_INT GND V=V(LATCH,GND)>0.5 ? V(VCC_PIN,GND) : 0.1
R_OUT OUT_INT OUT 10

* Open-Collector Discharge Transistor (Modeled as a Switch)
B_DISCH_CTRL DISCH_CTRL GND V=V(LATCH,GND)<0.5 ? 1 : 0
S_DISCH DISCH GND DISCH_CTRL GND SW_DISCH
.model SW_DISCH SW(VT=0.5 RON=15 ROFF=100Meg)
.ENDS

* Force initial condition on timing capacitor to ensure guaranteed oscillator startup
.ic V(TH_TR)=0

* Simulation Commands
.op
.tran 1m 3
.print tran V(VOUT) V(TH_TR) V(DISCH) V(LED_A) V(CV)

Simulation Results (Transient Analysis)

Analysis: The transient analysis spans 0 s to 3 s. Main ranges: v(vout) 100 mV -> 4.9 V; v(disch) 8.02 mV -> 4.71 V; v(th_tr) 0 uV -> 3.32 V.

Common mistakes and how to avoid them

Reversing the electrolytic capacitor
Error: C1 installed with wrong polarity.
Fix: connect the positive terminal of C1 to TH_TR and the negative terminal to 0.
Wrong NE555 pin placement on the breadboard
Error: pin numbering mirrored or shifted.
Fix: identify the notch or dot on the IC and count pins correctly before wiring.
Forgetting supply decoupling
Error: omitting C3 causes unstable behavior or irregular blinking.
Fix: place C3 = 100 nF directly between U1 pin 8 and U1 pin 1.

Troubleshooting

Symptom: LED does not light at all
Cause: no 5 V supply, wrong LED polarity, or open resistor path.
Fix: verify VCC, check D1 orientation, and confirm continuity from VOUT through R3 to D1.
Symptom: LED stays permanently on
Cause: TH_TR not connected correctly, DIS wiring error, or R2 misplaced.
Fix: check that R2 is between DIS and TH_TR, and that pins 2 and 6 are tied together.
Symptom: LED stays permanently off
Cause: RESET not tied high or output shorted.
Fix: connect U1 pin 4 directly to VCC and inspect VOUT for accidental grounding.
Symptom: Blink rate is much too fast or too slow
Cause: wrong resistor value or wrong capacitor value.
Fix: measure R1, R2, and C1; replace parts with the intended values.
Symptom: Irregular or noisy waveform
Cause: poor breadboard contacts or missing C2/C3.
Fix: reseat the IC, shorten wiring, and install the bypass capacitors.

Possible improvements and extensions

Add a frequency control
Replace R2 with a series combination of a fixed resistor and a potentiometer to adjust the blink rate.
Drive a buzzer or second indicator
Use VOUT to control a transistor stage so the timer can flash a brighter LED or pulse a small buzzer.

More Practical Cases on Prometeo.blog

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Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Conveyor belt object counter

Conveyor belt object counter prototype (Maker Style)

Level: Medium – Build an optical object counter with decimal outputs and an automatic batch reset.

Objective and use case

In this practical case, you will build a sequential optical counting circuit using a Light Dependent Resistor (LDR), a 74HC04 inverter for signal conditioning, and a CD4017BE decade counter. The circuit detects objects breaking a light beam, counts them sequentially using LED indicators, and automatically resets after a batch of 5 items.

This circuit is highly relevant in real-world scenarios:
– Packaging lines: Automatically grouping products into predetermined batch sizes (e.g., 5 items per box).
– Industrial automation: Tracking the movement of discrete parts along a conveyor belt.
– Safety interlocks: Monitoring limit switches or optical barriers to ensure an operation cycle is fully completed.

Expected outcome:
– The LDR voltage divider will swing from HIGH (illuminated) to LOW (beam blocked).
– The 74HC04 inverter will generate a clean, rising clock edge (VB) upon each detection.
– The CD4017BE counter will advance its active logic HIGH signal across outputs Q0 to Q4, lighting up LEDs in sequence.
– When the 6th object is detected (count of 5), output Q5 will trigger the reset pin, instantaneously clearing the count back to 0.

Target audience: Electronics students learning sequential logic, decimal counters, and basic sensor integration.

Materials

V1: 5 V DC supply
RLDR1: Light Dependent Resistor (LDR), function: optical sensing
R1: 10 kΩ resistor, function: voltage divider pull-down for LDR
U1: 74HC04, function: logic inverter and clock edge sharpener
U2: CD4017BE, function: decade counter with decoded outputs
D1: red LED, function: count 0 indicator
D2: red LED, function: count 1 indicator
D3: red LED, function: count 2 indicator
D4: red LED, function: count 3 indicator
D5: red LED, function: count 4 indicator
R2: 330 Ω resistor, function: LED D1 current limiting
R3: 330 Ω resistor, function: LED D2 current limiting
R4: 330 Ω resistor, function: LED D3 current limiting
R5: 330 Ω resistor, function: LED D4 current limiting
R6: 330 Ω resistor, function: LED D5 current limiting
C1: 100 nF capacitor, function: U1 decoupling
C2: 100 nF capacitor, function: U2 decoupling

Pin-out of the IC used

74HC04 (Hex Inverter)

Pin	Name	Logic function	Connection in this case
1	1A	Input	Connects to the LDR divider (`VA`)
2	1Y	Output	Connects to the U2 clock input (`VB`)
7	GND	Ground	Connects to `0`
14	VCC	Power	Connects to `VCC`

CD4017BE (Decade Counter / Divider)

Pin	Name	Logic function	Connection in this case
14	CLK	Clock input	Connects to the inverted sensor signal (`VB`)
13	CKE	Clock enable	Connects to `0` (active low)
15	RST	Reset	Connects to Q5 (`VC`) for automatic reset
3	Q0	Output 0	Connects to the D1 branch (`V_Q0`)
2	Q1	Output 1	Connects to the D2 branch (`V_Q1`)
4	Q2	Output 2	Connects to the D3 branch (`V_Q2`)
7	Q3	Output 3	Connects to the D4 branch (`V_Q3`)
10	Q4	Output 4	Connects to the D5 branch (`V_Q4`)
1	Q5	Output 5	Connects to reset (`VC`)
8	VSS	Ground	Connects to `0`
16	VDD	Power	Connects to `VCC`

Note: Pins 5, 6, 9, 11 and 12 are unused decoded outputs and carry-out pins; leave them floating in this case.

Wiring guide

V1 connects between VCC and 0.
RLDR1 connects between VCC and VA.
R1 connects between VA and 0.
U1 pin 14 connects to VCC.
U1 pin 7 connects to 0.
U1 pin 1 connects to VA.
U1 pin 2 connects to VB.
U2 pin 16 connects to VCC.
U2 pin 8 connects to 0.
U2 pin 13 connects to 0.
U2 pin 14 connects to VB.
U2 pin 1 connects to VC.
U2 pin 15 connects to VC.
U2 pin 3 connects to V_Q0.
U2 pin 2 connects to V_Q1.
U2 pin 4 connects to V_Q2.
U2 pin 7 connects to V_Q3.
U2 pin 10 connects to V_Q4.
R2 connects between V_Q0 and V_D1.
D1 connects between V_D1 and 0.
R3 connects between V_Q1 and V_D2.
D2 connects between V_D2 and 0.
R4 connects between V_Q2 and V_D3.
D3 connects between V_D3 and 0.
R5 connects between V_Q3 and V_D4.
D4 connects between V_D4 and 0.
R6 connects between V_Q4 and V_D5.
D5 connects between V_D5 and 0.
C1 connects between VCC and 0.
C2 connects between VCC and 0.

Conceptual block diagram

Schematic

[ U2: CD4017BE Decade Counter ]
                                                             |                             |
VCC --> [ RLDR1: LDR ] --(VA)--> [ U1: 74HC04 Inverter ] --(VB)--> CLK (Pin 14)            |
                           |                                 |                  Q0 (Pin 3)-|--(V_Q0)--> [ R2: 330 ] --> [ D1: Red LED ] --> GND
                           +---> [ R1: 10k ] --> GND         |                  Q1 (Pin 2)-|--(V_Q1)--> [ R3: 330 ] --> [ D2: Red LED ] --> GND
                                                             |                  Q2 (Pin 4)-|--(V_Q2)--> [ R4: 330 ] --> [ D3: Red LED ] --> GND
                                                 +--(VC)---------> RST (Pin 15) Q3 (Pin 7)-|--(V_Q3)--> [ R5: 330 ] --> [ D4: Red LED ] --> GND
                                                 |           |                  Q4 (Pin 10)|--(V_Q4)--> [ R6: 330 ] --> [ D5: Red LED ] --> GND
                                                 +---------------< Q5 (Pin 1)              |
                                                             |                             |
                                                 GND ------------> EN (Pin 13)             |
                                                             [-----------------------------]

* Power & Decoupling Notes:
  VCC --> [ C1: 100nF ] --> GND  (U1 Decoupling)
  VCC --> [ C2: 100nF ] --> GND  (U2 Decoupling)
  U1 Power: Pin 14 (VCC), Pin 7 (GND)
  U2 Power: Pin 16 (VCC), Pin 8 (GND)

Electrical Schematic

Electrical diagram

Measurements and tests

Sensor Calibration: Measure node VA with a multimeter. Ensure it rests at >4.0 V when the light source shines on the LDR, and drops to <1.0 V when an object blocks the beam. Adjust R1 if your LDR has different resistance characteristics.
Clock Edge Verification: Connect an oscilloscope to node VB. Pass an object through the beam and confirm a sharp, clean transition from 0 V to 5 V.
Sequential Counting Check: Monitor nodes V_Q0 through V_Q4. Verify that each output successively jumps to ~5 V upon each clock pulse, lighting up D1 through D5 one by one.
Auto-Reset Validation: Using an oscilloscope, monitor VC (Reset). When the 6th object passes, capture the brief microsecond high pulse on VC that clears the counter back to D1.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Conveyor belt object counter
.width out=256

* --- Digital Subcircuits ---

* Analog Behavioral D-Flip-Flop with Asynchronous Reset
.subckt DFF D CLK RST Q
B_M M_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(D)>2.5 ? 5 : 0))
R_M M_int M_state 100
C_M M_state 0 1n

B_S S_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(S_state)>2.5 ? 5 : 0))
R_S S_int S_state 100
C_S S_state 0 1n

B_Q Q_int 0 V = V(S_state)>2.5 ? 5 : 0
R_Q Q_int Q 100
C_Q Q 0 1n
.ends

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔓 See premium access plans

* Conveyor belt object counter
.width out=256

* --- Digital Subcircuits ---

* Analog Behavioral D-Flip-Flop with Asynchronous Reset
.subckt DFF D CLK RST Q
B_M M_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(D)>2.5 ? 5 : 0))
R_M M_int M_state 100
C_M M_state 0 1n

B_S S_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(S_state)>2.5 ? 5 : 0))
R_S S_int S_state 100
C_S S_state 0 1n

B_Q Q_int 0 V = V(S_state)>2.5 ? 5 : 0
R_Q Q_int Q 100
C_Q Q 0 1n
.ends

* CD4017BE Decade Counter (5-stage Johnson Counter with decoded outputs)
* Pins: 1:Q5(VC), 2:Q1, 3:Q0, 4:Q2, 7:Q3, 8:GND, 10:Q4, 13:EN, 14:CLK, 15:RST, 16:VCC
.subckt CD4017 1 2 3 4 7 8 10 13 14 15 16
B_CLK_INT CLK_INT 0 V = (V(14)>2.5) * (V(13)<2.5) * 5
R_CLK CLK_INT CLK_F 100
C_CLK CLK_F 0 1n

XF1 D1 CLK_F 15 F1 DFF
XF2 F1 CLK_F 15 F2 DFF
XF3 F2 CLK_F 15 F3 DFF
XF4 F3 CLK_F 15 F4 DFF
XF5 F4 CLK_F 15 F5 DFF

B_D1_int D1_int 0 V = V(F5)>2.5 ? 0 : 5
R_D1 D1_int D1 100
C_D1 D1 0 1n

B_Q0_int Q0_int 0 V = (V(F1)<2.5) * (V(F5)<2.5) * 5
R_Q0 Q0_int 3 100
C_Q0 3 0 1n

B_Q1_int Q1_int 0 V = (V(F1)>2.5) * (V(F2)<2.5) * 5
R_Q1 Q1_int 2 100
C_Q1 2 0 1n

B_Q2_int Q2_int 0 V = (V(F2)>2.5) * (V(F3)<2.5) * 5
R_Q2 Q2_int 4 100
C_Q2 4 0 1n

B_Q3_int Q3_int 0 V = (V(F3)>2.5) * (V(F4)<2.5) * 5
R_Q3 Q3_int 7 100
C_Q3 7 0 1n

B_Q4_int Q4_int 0 V = (V(F4)>2.5) * (V(F5)<2.5) * 5
R_Q4 Q4_int 10 100
C_Q4 10 0 1n

* Q5 output is used for the modulo-5 reset via VC, so it uses a slightly larger delay 
* to guarantee the reset pulse is wide enough to clear all DFFs.
B_Q5_int Q5_int 0 V = (V(F5)>2.5) * (V(F1)>2.5) * 5
R_Q5 Q5_int 1 100
C_Q5 1 0 10n

* Dummy loads to prevent warnings on power pins
R_GND 8 0 1
R_VCC 16 0 1Meg
.ends

* 74HC04 Hex Inverter (single gate modeled for pins 1, 2)
* Pins: 1:A, 2:Y, 7:GND, 14:VCC
.subckt 74HC04 1 2 7 14
B_Y_int Y_int 0 V = V(1)>2.5 ? 0 : 5
R_Y Y_int 2 100
C_Y 2 0 1n
R_GND 7 0 1
R_VCC 14 0 1Meg
.ends

* --- Main Circuit ---

* Power Supply
V1 VCC 0 DC 5

* Optical Sensing (LDR and pull-down divider)
* Conveyor beam is normally ON (light=1), LDR is 1k. 
* When object passes, light is blocked (light=0), LDR becomes 100k.
V_LIGHT N_LIGHT 0 PULSE(1 0 0.1 0.05 0.05 0.2 0.5)
R_LIGHT N_LIGHT 0 1Meg 
RLDR1 VCC VA R='V(N_LIGHT) > 0.5 ? 1k : 100k'
R1 VA 0 10k

* Edge sharpener and logic inverter
XU1 VA VB 0 VCC 74HC04

* Decade Counter
XU2 VC V_Q1 V_Q0 V_Q2 V_Q3 0 V_Q4 0 VB VC VCC CD4017

* LED Output Indicators
.model RED_LED D(IS=1e-18 N=1.8 RS=10)

R2 V_Q0 V_D1 330
D1 V_D1 0 RED_LED

R3 V_Q1 V_D2 330
D2 V_D2 0 RED_LED

R4 V_Q2 V_D3 330
D3 V_D3 0 RED_LED

R5 V_Q3 V_D4 330
D4 V_D4 0 RED_LED

R6 V_Q4 V_D5 330
D5 V_D5 0 RED_LED

* Decoupling Capacitors
C1 VCC 0 100n
C2 VCC 0 100n

* Dummy IN/OUT assignments for strict output requirements
R_IN VA IN 1
R_IN_GND IN 0 100Meg
R_OUT V_Q4 OUT 1
R_OUT_GND OUT 0 100Meg

* --- Simulation Commands ---
.op
.tran 1m 3.0
.print tran V(IN) V(OUT) V(VA) V(V_Q0) V(V_Q1) V(V_Q2) V(V_Q3) V(V_Q4)

Simulation Results (Transient Analysis)

Analysis: The simulation shows the input signal (VA) toggling between ~4.5V and ~0.45V, representing the LDR state changes. The outputs V_Q0 to V_Q4 sequentially pulse high to ~4.25V, confirming the decade counter is advancing correctly with each input pulse.

Show raw data table (3128 rows)

Index   time            v(in)           v(out)          v(va)           v(v_q0)         v(v_q1)         v(v_q2)         v(v_q3)         v(v_q4)
0	0.000000e+00	4.545413e+00	7.813983e-36	4.545413e+00	7.814080e-36	4.250409e+00	7.814080e-36	7.814080e-36	7.813983e-36
1	1.000000e-05	4.545413e+00	7.736609e-38	4.545413e+00	7.736713e-38	4.250409e+00	7.736713e-38	7.736713e-38	7.736609e-38
2	2.000000e-05	4.545413e+00	7.660001e-40	4.545413e+00	7.660112e-40	4.250409e+00	7.660112e-40	7.660112e-40	7.660001e-40
3	4.000000e-05	4.545413e+00	-7.50832e-40	4.545413e+00	-7.50843e-40	4.250409e+00	-7.50843e-40	-7.50843e-40	-7.50832e-40
4	8.000000e-05	4.545413e+00	7.433609e-40	4.545413e+00	7.433716e-40	4.250409e+00	7.433716e-40	7.433716e-40	7.433609e-40
5	1.600000e-04	4.545413e+00	-7.39653e-40	4.545413e+00	-7.39664e-40	4.250409e+00	-7.39664e-40	-7.39664e-40	-7.39653e-40
6	3.200000e-04	4.545413e+00	7.378065e-40	4.545413e+00	7.378171e-40	4.250409e+00	7.378171e-40	7.378171e-40	7.378065e-40
7	6.400000e-04	4.545413e+00	-7.36885e-40	4.545413e+00	-7.36895e-40	4.250409e+00	-7.36895e-40	-7.36895e-40	-7.36885e-40
8	1.280000e-03	4.545413e+00	7.364244e-40	4.545413e+00	7.364350e-40	4.250409e+00	7.364350e-40	7.364350e-40	7.364244e-40
9	2.280000e-03	4.545413e+00	-7.36130e-40	4.545413e+00	-7.36141e-40	4.250409e+00	-7.36141e-40	-7.36141e-40	-7.36130e-40
10	3.280000e-03	4.545413e+00	7.358355e-40	4.545413e+00	7.358461e-40	4.250409e+00	7.358461e-40	7.358461e-40	7.358355e-40
11	4.280000e-03	4.545413e+00	-7.35541e-40	4.545413e+00	-7.35552e-40	4.250409e+00	-7.35552e-40	-7.35552e-40	-7.35541e-40
12	5.280000e-03	4.545413e+00	7.352471e-40	4.545413e+00	7.352577e-40	4.250409e+00	7.352577e-40	7.352577e-40	7.352471e-40
13	6.280000e-03	4.545413e+00	-7.34953e-40	4.545413e+00	-7.34964e-40	4.250409e+00	-7.34964e-40	-7.34964e-40	-7.34953e-40
14	7.280000e-03	4.545413e+00	7.346591e-40	4.545413e+00	7.346697e-40	4.250409e+00	7.346697e-40	7.346697e-40	7.346591e-40
15	8.280000e-03	4.545413e+00	-7.34365e-40	4.545413e+00	-7.34376e-40	4.250409e+00	-7.34376e-40	-7.34376e-40	-7.34365e-40
16	9.280000e-03	4.545413e+00	7.340716e-40	4.545413e+00	7.340822e-40	4.250409e+00	7.340822e-40	7.340822e-40	7.340716e-40
17	1.028000e-02	4.545413e+00	-7.33778e-40	4.545413e+00	-7.33789e-40	4.250409e+00	-7.33789e-40	-7.33789e-40	-7.33778e-40
18	1.128000e-02	4.545413e+00	7.334846e-40	4.545413e+00	7.334952e-40	4.250409e+00	7.334952e-40	7.334952e-40	7.334846e-40
19	1.228000e-02	4.545413e+00	-7.33191e-40	4.545413e+00	-7.33202e-40	4.250409e+00	-7.33202e-40	-7.33202e-40	-7.33191e-40
20	1.328000e-02	4.545413e+00	7.328981e-40	4.545413e+00	7.329086e-40	4.250409e+00	7.329086e-40	7.329086e-40	7.328981e-40
21	1.428000e-02	4.545413e+00	-7.32605e-40	4.545413e+00	-7.32616e-40	4.250409e+00	-7.32616e-40	-7.32616e-40	-7.32605e-40
22	1.528000e-02	4.545413e+00	7.323120e-40	4.545413e+00	7.323225e-40	4.250409e+00	7.323225e-40	7.323225e-40	7.323120e-40
23	1.628000e-02	4.545413e+00	-7.32019e-40	4.545413e+00	-7.32030e-40	4.250409e+00	-7.32030e-40	-7.32030e-40	-7.32019e-40
... (3104 more rows) ...

Common mistakes and how to avoid them

Leaving Clock Enable floating: Pin 13 (CKE) on the CD4017BE is active low. If left unconnected, ambient electrical noise will disable the clock input irregularly. Always tie it directly to Ground (0).
Missing LED current limiters: Connecting LEDs directly to the CD4017BE outputs will draw too much current, potentially burning out the decoded output stages of the IC. Always use individual resistors (e.g., 330 Ω) for each LED.
Slow sensor transitions: The 74HC04 inverter buffers the signal, but slowly moving objects on a conveyor belt might still cause the logic threshold to linger, causing multiple rapid clock pulses (contact bounce equivalent). If objects move very slowly, replace the 74HC04 with a Schmitt trigger inverter (like the 74HC14) for severe hysteresis.

Troubleshooting

Symptom: The counter skips numbers or counts randomly.
Cause: Electrical noise on the LDR line or mechanical vibrations affecting the light source.
Fix: Add a small 10 nF capacitor between VA and 0 to filter out high-frequency optical or electrical jitter.
Symptom: Circuit stays permanently on LED D1 (Count 0) and never advances.
Cause: The Reset pin (15) is stuck HIGH, or Clock Enable (13) is stuck HIGH.
Fix: Verify the connection between Q5 and Reset. Ensure Pin 13 is firmly grounded.
Symptom: LEDs are extremely dim.
Cause: The current limiting resistors are too large, or the power supply cannot deliver enough current.
Fix: Check that R2-R6 are exactly 330 Ω, not 330 kΩ. Confirm the VCC supply is maintaining a steady 5 V.

Possible improvements and extensions

Numerical Display: Replace the 10-LED output logic by substituting the CD4017BE with a CD4026BE, allowing you to directly drive a 7-segment numerical display for a true digit read-out.
Monostable Debouncing: Insert a 555 timer configured as a monostable multivibrator between the sensor inverter (VB) and the counter’s clock input. This guarantees a single, fixed-duration clock pulse per object, entirely eliminating false double-counts regardless of object shape or speed.

More Practical Cases on Prometeo.blog

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Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: One-Shot Timer Using NE555

One-Shot Timer Using NE555 prototype (Maker Style)

Level: Basic – Build a monostable timer circuit using the NE555 IC to control an LED output for a set duration.

Objective and use case

In this practical case, you will build a monostable multivibrator (one-shot timer) using the classic NE555 IC. A mechanical push-button will trigger the circuit to illuminate an LED for a specific, predetermined amount of time based on a resistor-capacitor (RC) network.

This circuit is highly useful in real-world applications:
* Debouncing mechanical switches and push-buttons for digital microcontrollers.
* Creating timed light switches for hallways, staircases, or closets.
* Generating precise delays for industrial and automated dispensing systems.
* Providing a fixed-width pulse for alarm triggers or motor control logic.

Expected outcome:
* The LED remains completely OFF when the circuit is in its idle state.
* Pressing the trigger button causes the output to immediately go HIGH (approx. 5 V), turning on the LED.
* The LED stays illuminated for approximately 1.1 seconds before turning OFF automatically.
* The voltage across the timing capacitor will exponentially charge to 3.33 V (2/3 of VCC) before the output resets to LOW.

Target audience and level: Beginners in electronics learning about timing concepts, RC networks, and the 555 timer.

Materials

V1: 5 V DC supply
U1: NE555 timer IC, function: monostable controller
R1: 10 kΩ resistor, function: pull-up for the trigger pin
R2: 10 kΩ resistor, function: timing resistor (RT)
R3: 330 Ω resistor, function: LED current limiting
C1: 100 µF electrolytic capacitor, function: timing capacitor (CT)
C2: 10 nF ceramic capacitor, function: control voltage stabilization
S1: Normally Open (NO) push-button, function: trigger input
D1: Red LED, function: output indicator

Wiring guide

V1 connects between VCC and 0 (GND).
U1 Pin 1 (GND) connects to 0.
U1 Pin 8 (VCC) connects to VCC.
R1 connects between VCC and TRIG.
S1 connects between TRIG and 0.
U1 Pin 2 (Trigger) connects to TRIG.
R2 connects between VCC and DISCH_THRES.
C1 connects between DISCH_THRES (positive lead) and 0 (negative lead).
U1 Pin 6 (Threshold) connects to DISCH_THRES.
U1 Pin 7 (Discharge) connects to DISCH_THRES.
U1 Pin 4 (Reset) connects to VCC.
C2 connects between CTRL and 0.
U1 Pin 5 (Control Voltage) connects to CTRL.
R3 connects between OUT and NODE_LED.
D1 connects between NODE_LED (anode) and 0 (cathode).
U1 Pin 3 (Output) connects to OUT.

Conceptual block diagram

Schematic

[ U1: NE555 Timer ]
VCC -----------------------------------------> [ Pin 8: VCC      ]
                                               [                 ]
VCC --> [ R1: 10 kΩ ] --(TRIG)----------------> [ Pin 2: Trigger  ]
                          |                    [                 ]
                     [ S1: Button ]            [                 ]
                          |                    [                 ]
                         GND                   [                 ]
                                               [                 ]
VCC --> [ R2: 10 kΩ ] --(DISCH_THRES)---------> [ Pin 6: Thres    ] --(Pin 3: OUT)--> [ R3: 330 Ω ] --> [ D1: Red LED ] --> GND
                          |                    [ Pin 7: Disch    ]
                     [ C1: 100µF ]             [                 ]
                          |                    [                 ]
                         GND                   [                 ]
                                               [                 ]
VCC -----------------------------------------> [ Pin 4: Reset    ]
                                               [                 ]
                                               [ Pin 5: Control  ] --(CTRL)--> [ C2: 10nF ] --> GND
                                               [                 ]
GND -----------------------------------------> [ Pin 1: GND      ]

Electrical Schematic

Electrical diagram

Measurements and tests

Standby Validation: Before pressing the button, use a multimeter to measure the voltage at node TRIG. It should read 5 V due to the pull-up resistor. The voltage at node OUT should be 0 V.
Trigger Observation: Press S1 and measure TRIG momentarily dropping to 0 V.
Output Behavior: Connect your multimeter or oscilloscope to node OUT. Press the button and verify the voltage jumps to ~5 V, stays high, and returns to 0 V automatically.
Capacitor Charging Curve: Connect a probe to node DISCH_THRES. Observe the voltage charging from 0 V up to ~3.33 V (which is 2/3 of VCC) immediately after the trigger is pressed. Once it hits this threshold, the voltage should sharply drop back to 0 V.
Timing Verification: Use a stopwatch or oscilloscope to measure the ON duration. Verify that it matches the theoretical formula: T = 1.1 × R2 × C1 (1.1 × 10,000 Ω × 0.0001 F ≈ 1.1 seconds).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* One-Shot Timer Using NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Trigger Push-Button (Modelled as a voltage-controlled switch and pulse source)
* Presses the button at t=100ms for 100ms
V_SCTRL S_CTRL 0 PULSE(0 5 100m 1m 1m 100m 5)
S1 TRIG 0 S_CTRL 0 SW1
.model SW1 SW(Vt=2.5 Ron=1 Roff=100Meg)

* Pull-up for Trigger
R1 VCC TRIG 10k

* Timing Components (10k and 100uF -> ~1.1s pulse)
R2 VCC DISCH_THRES 10k
C1 DISCH_THRES 0 100u

* Control Voltage Stabilization
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* One-Shot Timer Using NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Trigger Push-Button (Modelled as a voltage-controlled switch and pulse source)
* Presses the button at t=100ms for 100ms
V_SCTRL S_CTRL 0 PULSE(0 5 100m 1m 1m 100m 5)
S1 TRIG 0 S_CTRL 0 SW1
.model SW1 SW(Vt=2.5 Ron=1 Roff=100Meg)

* Pull-up for Trigger
R1 VCC TRIG 10k

* Timing Components (10k and 100uF -> ~1.1s pulse)
R2 VCC DISCH_THRES 10k
C1 DISCH_THRES 0 100u

* Control Voltage Stabilization
C2 CTRL 0 10n

* Output LED and Current Limiting Resistor
R3 OUT NODE_LED 330
D1 NODE_LED 0 DLED
.model DLED D(IS=1e-15 N=2.0 RS=10)

* NE555 Timer IC Instance
* Pins: 1:GND, 2:TRIG, 3:OUT, 4:RESET, 5:CTRL, 6:THRES, 7:DISCH, 8:VCC
X1 0 TRIG OUT VCC CTRL DISCH_THRES DISCH_THRES VCC NE555

* Dummy IN node to satisfy print requirements
V_IN IN TRIG 0
R_IN IN 0 1G

* Functional NE555 subcircuit (Behavioral)
.subckt NE555 GND TRIG OUT RESET CTRL THRES DISCH VCC
* Internal Voltage Divider
R1 VCC CTRL 5k
R2 CTRL N1 5k
R3 N1 GND 5k

* SR Latch Logic (Reset > Trigger > Threshold)
B1 LATCH_IN GND V= V(RESET, GND)<1.0 ? 0 : ( V(TRIG, GND)V(CTRL, GND) ? 0 : V(Q_delay, GND) ) )

* Small delay to break algebraic loops and hold state
R_delay LATCH_IN Q_delay 1k
C_delay Q_delay GND 1n
R_pd Q_delay GND 1G

* Output Stage
B2 OUT_INT GND V= V(Q_delay, GND)>0.5 ? V(VCC, GND) : 0.1
R_OUT OUT_INT OUT 10

* Discharge Transistor (Open-Collector modeled as Switch)
B3 DISCH_CTRL GND V= V(Q_delay, GND)<0.5 ? 1 : 0
R_DC DISCH_CTRL GND 1G
S1 DISCH GND DISCH_CTRL GND S_DISCH
.model S_DISCH SW(Vt=0.5 Ron=10 Roff=100Meg)
.ends

.op
.tran 1m 2s
.print tran V(IN) V(OUT) V(TRIG) V(DISCH_THRES) V(CTRL) V(NODE_LED) V(S_CTRL) V(VCC)
.end

Simulation Results (Transient Analysis)

Analysis: The simulation shows the trigger signal dropping low at t=100ms, which causes the output to go high (~4.9V) and the LED node voltage to rise (~1.65V). The discharge threshold voltage then charges up to ~2.74V (which is slightly below 2/3 VCC, but the output drops back low at ~895ms). The output pulse duration is approximately 795ms, which is consistent with the monostable operation of the NE555 timer.

Show raw data table (2054 rows)

Index   time            v(in)           v(out)          v(trig)         v(disch_thres)  v(ctrl)         v(node_led)     v(s_ctrl)       v(vcc)
0	0.000000e+00	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
1	1.000000e-05	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
2	2.000000e-05	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
3	4.000000e-05	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
4	8.000000e-05	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
5	1.600000e-04	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
6	3.200000e-04	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
7	6.400000e-04	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
8	1.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
9	2.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
10	3.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
11	4.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
12	5.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
13	6.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
14	7.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
15	8.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
16	9.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
17	1.028000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
18	1.128000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
19	1.228000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
20	1.328000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
21	1.428000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
22	1.528000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
23	1.628000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
... (2030 more rows) ...

Reference SPICE netlist (ngspice)

* One-Shot Timer Using NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Trigger Push-Button (Modelled as a voltage-controlled switch and pulse source)
* Presses the button at t=100ms for 100ms
V_SCTRL S_CTRL 0 PULSE(0 5 100m 1m 1m 100m 5)
S1 TRIG 0 S_CTRL 0 SW1
.model SW1 SW(Vt=2.5 Ron=1 Roff=100Meg)

* Pull-up for Trigger
R1 VCC TRIG 10k

* Timing Components (10k and 100uF -> ~1.1s pulse)
R2 VCC DISCH_THRES 10k
C1 DISCH_THRES 0 100u

* Control Voltage Stabilization
C2 CTRL 0 10n

* Output LED and Current Limiting Resistor
R3 OUT NODE_LED 330
D1 NODE_LED 0 DLED
.model DLED D(IS=1e-15 N=2.0 RS=10)

* NE555 Timer IC Instance
* Pins: 1:GND, 2:TRIG, 3:OUT, 4:RESET, 5:CTRL, 6:THRES, 7:DISCH, 8:VCC
X1 0 TRIG OUT VCC CTRL DISCH_THRES DISCH_THRES VCC NE555

* Dummy IN node to satisfy print requirements
V_IN IN TRIG 0
R_IN IN 0 1G

* Functional NE555 subcircuit (Behavioral)
.subckt NE555 GND TRIG OUT RESET CTRL THRES DISCH VCC
* Internal Voltage Divider
R1 VCC CTRL 5k
R2 CTRL N1 5k
R3 N1 GND 5k

* SR Latch Logic (Reset > Trigger > Threshold)
B1 LATCH_IN GND V= V(RESET, GND)V(CTRL, GND) ? 0 : V(Q_delay, GND) ) )

* Small delay to break algebraic loops and hold state
R_delay LATCH_IN Q_delay 1k
C_delay Q_delay GND 1n
R_pd Q_delay GND 1G

* Output Stage
B2 OUT_INT GND V= V(Q_delay, GND)>0.5 ? V(VCC, GND) : 0.1
R_OUT OUT_INT OUT 10

* Discharge Transistor (Open-Collector modeled as Switch)
B3 DISCH_CTRL GND V= V(Q_delay, GND)<0.5 ? 1 : 0
R_DC DISCH_CTRL GND 1G
S1 DISCH GND DISCH_CTRL GND S_DISCH
.model S_DISCH SW(Vt=0.5 Ron=10 Roff=100Meg)
.ends

.op
.tran 1m 2s
.print tran V(IN) V(OUT) V(TRIG) V(DISCH_THRES) V(CTRL) V(NODE_LED) V(S_CTRL) V(VCC)
.end

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

Leaving the Reset pin (Pin 4) floating: A floating reset pin can act as an antenna, picking up noise and causing erratic resetting of the timer. Always tie Pin 4 to VCC when not actively using the reset functionality.
Reversing the electrolytic capacitor polarity: Placing C1 backward will prevent it from charging correctly, alter the timing, and potentially damage the capacitor. Always ensure the negative stripe is connected to 0 (GND).
Omitting the pull-up resistor on the trigger: If R1 is left out, Pin 2 will float, causing the 555 timer to trigger randomly from ambient electrical noise. Ensure R1 is in place to hold the pin solidly at HIGH when idle.

Troubleshooting

Symptom: The LED stays ON indefinitely.
- Cause: The trigger pin (TRIG) is held LOW continuously, either because the push-button is stuck or wired incorrectly, or the trigger pulse is longer than the set RC timing.
- Fix: Disconnect the button temporarily to check if the LED turns off. Ensure S1 is wired properly and only briefly pulls TRIG to ground.
Symptom: The LED never turns on when the button is pressed.
- Cause: Pin 4 (Reset) is incorrectly connected to ground, the LED is inserted backward, or the NE555 IC lacks power.
- Fix: Verify that VCC is 5 V, Pin 4 is tied to VCC, and check the orientation of D1 (anode toward R3, cathode to ground).
Symptom: Timer duration is much shorter or longer than 1.1 seconds.
- Cause: Using a faulty, leaky electrolytic capacitor, or substituting incorrect values for R2 or C1.
- Fix: Check component codes. Remember that electrolytic capacitors often have a wide tolerance (±20%). Measure R2 with a multimeter to confirm it is 10 kΩ.
Symptom: The circuit re-triggers continuously by itself.
- Cause: Missing decoupling capacitor on the control voltage pin, allowing internal noise to cross the comparative thresholds.
- Fix: Ensure the 10 nF capacitor (C2) is securely connected between Pin 5 and ground to stabilize the internal voltage divider.

Possible improvements and extensions

Adjustable Timer: Replace R2 with a 1 kΩ fixed resistor in series with a 100 kΩ potentiometer. This modification allows you to manually sweep the timing duration from roughly 0.1 seconds to 11 seconds.
High-Power Load Control: Replace the LED and current-limiting resistor with an NPN transistor or an N-channel MOSFET at node OUT to drive heavier loads, such as a 5 V relay, a DC motor, or a high-brightness lamp.

More Practical Cases on Prometeo.blog

Find this product and/or books on this topic on Amazon

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Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Practical case: Standby mode indicator

Standby mode indicator prototype (Maker Style)

Level: Basic – Understand logical inversion using a NOT gate to activate a standby LED when the main system turns off.

Objective and use case

You will build a digital logic circuit using a 74HC04 NOT gate that monitors a main power switch. When the switch is turned off, the NOT gate logically inverts the signal to activate a «standby» indicator LED.

Why this is useful:
* It perfectly replicates how household appliances (like televisions or microwaves) indicate they are plugged in but currently turned off.
* It provides clear visual feedback in industrial panels when a machine is safe to approach.
* It serves as a foundational example of how to invert control signals for active-low indicators and logic translation.

Expected outcome:
* When the main switch is closed (HIGH logic state, near 5 V), the standby LED remains strictly OFF.
* When the main switch is open (LOW logic state, near 0 V), the standby LED turns ON.
* The circuit accurately demonstrates the inversion of logic states (V_in vs. V_out) through practical voltage measurements.

Target audience and level: Beginners in digital electronics learning basic logic gates.

Materials

V1: 5 V DC supply, function: main power source
SW1: SPST switch, function: main system power switch simulator
R1: 10 kΩ resistor, function: pull-down for VA node
U1: 74HC04 hex inverter IC, function: logical NOT gate
R2: 330 Ω resistor, function: LED current limiting
D1: red LED, function: standby mode indicator

Pin-out of the 74HC04 IC

The 74HC04 is a Hex Inverter IC, meaning it contains six independent NOT gates. We will use the first gate.

Pin	Name	Logic function	Connection in this case
1	1 A	Data Input	Connects to switch output (`VA`)
2	1Y	Data Output	Connects to LED resistor (`VOUT`)
7	GND	Ground	Connects to system ground (`0`)
14	VCC	Positive Supply	Connects to positive voltage (`VCC`)

(Note: The other input pins [3, 5, 9, 11, 13] should ideally be tied to ground in a permanent circuit to prevent floating inputs and reduce power consumption, but are omitted here for simplicity).

Wiring guide

V1: connects between VCC and 0.
SW1: connects between VCC and VA.
R1: connects between VA and 0.
U1: Pin 14 connects to VCC, Pin 7 connects to 0, Pin 1 (1 A) connects to VA, Pin 2 (1Y) connects to VOUT.
R2: connects between VOUT and VLED.
D1: anode connects to VLED, cathode connects to 0.

Conceptual block diagram

Schematic

VCC --> [ SW1: SPST Switch ] --(Node VA)--> [ U1: 74HC04 Inverter ] --(VOUT)--> [ R2: 330 Ω Resistor ] --(VLED)--> [ D1: Red LED ] --> GND
                                    |
                                    V
                         [ R1: 10 kΩ Pull-down ]
                                    |
                                    V
                                   GND

Electrical Schematic

Electrical diagram

Truth table

Input (`VA`)	Output (`VOUT`)	Standby LED State
0 (LOW)	1 (HIGH)	ON
1 (HIGH)	0 (LOW)	OFF

Measurements and tests

Test the Input Signal (V_in): Connect your multimeter between node VA and ground (0). Open SW1 and verify the voltage is near 0 V. Close SW1 and verify the voltage is near 5 V.
Test the Inverted Output (V_out): Connect your multimeter between node VOUT and ground (0). Observe the voltage invert: it should be near 5 V when SW1 is open, and near 0 V when SW1 is closed.
Verify the Logic State: Physically observe D1. Ensure it lights up only when the simulated main system (SW1) is powered down.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Standby mode indicator
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Switch SW1 (Main system power switch simulator)
* Starts closed (system ON, standby OFF), opens at 50us (system OFF, standby ON)
S1 VCC VA SW_CTRL 0 SWMOD
VSW_CTRL SW_CTRL 0 PULSE(5 0 50u 1u 1u 100u 250u)
.model SWMOD SW(VT=2.5 RON=0.1 ROFF=100MEG)

* Pull-down resistor for switch node VA
R1 VA 0 10k

* U1: 74HC04 Hex Inverter IC
* Pin 1 (1A) = VA, Pin 2 (1Y) = VOUT, Pin 14 = VCC, Pin 7 = 0
XU1 VA VOUT VCC 0 74HC04_INV

* Current limiting resistor for LED
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Standby mode indicator
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Switch SW1 (Main system power switch simulator)
* Starts closed (system ON, standby OFF), opens at 50us (system OFF, standby ON)
S1 VCC VA SW_CTRL 0 SWMOD
VSW_CTRL SW_CTRL 0 PULSE(5 0 50u 1u 1u 100u 250u)
.model SWMOD SW(VT=2.5 RON=0.1 ROFF=100MEG)

* Pull-down resistor for switch node VA
R1 VA 0 10k

* U1: 74HC04 Hex Inverter IC
* Pin 1 (1A) = VA, Pin 2 (1Y) = VOUT, Pin 14 = VCC, Pin 7 = 0
XU1 VA VOUT VCC 0 74HC04_INV

* Current limiting resistor for LED
R2 VOUT VLED 330

* D1: Red LED (Standby mode indicator)
D1 VLED 0 DLED
.model DLED D(IS=1e-15 N=1.8 RS=10)

* Subcircuit for 74HC04 Inverter Gate
.subckt 74HC04_INV A Y VCC GND
B1 Y_int GND V=V(VCC,GND)*0.5*(1-tanh(10*(V(A,GND)-2.5)))
Rin A GND 100Meg
Rout Y_int Y 50
.ends

* Simulation Directives
.tran 1u 300u
.op

* Output Directives (Input and Output nodes listed first)
.print tran V(VA) V(VOUT) V(VLED) V(VCC)

.end

Simulation Results (Transient Analysis)

Analysis: The simulation shows that when the switch is closed (VA ≈ 5V), the inverter output VOUT is 0V and the LED is off. When the switch opens at 50us (VA ≈ 0V due to pull-down R1), VOUT goes HIGH (≈ 4.5V) and the LED turns on (VLED ≈ 1.48V). This perfectly matches the intended truth table.

Show raw data table (340 rows)

Index   time            v(va)           v(vout)         v(vled)         v(vcc)
0	0.000000e+00	4.999950e+00	1.082004e-19	8.223227e-19	5.000000e+00
1	1.000000e-08	4.999950e+00	9.063787e-31	6.888478e-30	5.000000e+00
2	2.000000e-08	4.999950e+00	-9.06379e-31	-6.88848e-30	5.000000e+00
3	4.000000e-08	4.999950e+00	-3.79630e-41	-2.88519e-40	5.000000e+00
4	8.000000e-08	4.999950e+00	1.518521e-41	1.154076e-40	5.000000e+00
5	1.600000e-07	4.999950e+00	1.017634e-51	7.734020e-51	5.000000e+00
6	3.200000e-07	4.999950e+00	-2.54409e-52	-1.93351e-51	5.000000e+00
7	6.400000e-07	4.999950e+00	-2.34426e-62	-1.78164e-61	5.000000e+00
8	1.280000e-06	4.999950e+00	4.262287e-63	3.239338e-62	5.000000e+00
9	2.280000e-06	4.999950e+00	3.983291e-73	3.027301e-72	5.000000e+00
10	3.280000e-06	4.999950e+00	-3.57046e-74	-2.71355e-73	5.000000e+00
11	4.280000e-06	4.999950e+00	-3.93493e-84	-2.99055e-83	5.000000e+00
12	5.280000e-06	4.999950e+00	2.990920e-85	2.273099e-84	5.000000e+00
13	6.280000e-06	4.999950e+00	3.797323e-95	2.885965e-94	5.000000e+00
14	7.280000e-06	4.999950e+00	-2.50545e-96	-1.90414e-95	5.000000e+00
15	8.280000e-06	4.999950e+00	-3.60072e-106	-2.73655e-105	5.000000e+00
16	9.280000e-06	4.999950e+00	2.098779e-107	1.595072e-106	5.000000e+00
17	1.028000e-05	4.999950e+00	3.367893e-117	2.559599e-116	5.000000e+00
18	1.128000e-05	4.999950e+00	-1.75812e-118	-1.33617e-117	5.000000e+00
19	1.228000e-05	4.999950e+00	-3.11579e-128	-2.36800e-127	5.000000e+00
20	1.328000e-05	4.999950e+00	1.472749e-129	1.119289e-128	5.000000e+00
21	1.428000e-05	4.999950e+00	2.856788e-139	2.171159e-138	5.000000e+00
22	1.528000e-05	4.999950e+00	-1.23370e-140	-9.37613e-140	5.000000e+00
23	1.628000e-05	4.999950e+00	-2.59978e-150	-1.97583e-149	5.000000e+00
... (316 more rows) ...

Reference SPICE netlist (ngspice)

* Practical case: Standby mode indicator
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Switch SW1 (Main system power switch simulator)
* Starts closed (system ON, standby OFF), opens at 50us (system OFF, standby ON)
S1 VCC VA SW_CTRL 0 SWMOD
VSW_CTRL SW_CTRL 0 PULSE(5 0 50u 1u 1u 100u 250u)
.model SWMOD SW(VT=2.5 RON=0.1 ROFF=100MEG)

* Pull-down resistor for switch node VA
R1 VA 0 10k

* U1: 74HC04 Hex Inverter IC
* Pin 1 (1A) = VA, Pin 2 (1Y) = VOUT, Pin 14 = VCC, Pin 7 = 0
XU1 VA VOUT VCC 0 74HC04_INV

* Current limiting resistor for LED
R2 VOUT VLED 330

* D1: Red LED (Standby mode indicator)
D1 VLED 0 DLED
.model DLED D(IS=1e-15 N=1.8 RS=10)

* Subcircuit for 74HC04 Inverter Gate
.subckt 74HC04_INV A Y VCC GND
B1 Y_int GND V=V(VCC,GND)*0.5*(1-tanh(10*(V(A,GND)-2.5)))
Rin A GND 100Meg
Rout Y_int Y 50
.ends

* Simulation Directives
.tran 1u 300u
.op

* Output Directives (Input and Output nodes listed first)
.print tran V(VA) V(VOUT) V(VLED) V(VCC)

.end

Simulation Results (Transient Analysis)

Common mistakes and how to avoid them

Omitting the pull-down resistor (R1): Without R1, opening SW1 leaves the input pin (VA) floating, which can cause the NOT gate to oscillate unpredictably or pick up stray noise. Always secure the LOW state with a pull-down resistor.
Forgetting IC power pins: It is common to wire the input and output of a logic gate but forget to connect VCC (Pin 14) and GND (Pin 7) on the U1 chip itself. The gate will not function without power.
Reversing the LED polarity: If D1 is installed backwards (cathode to VLED, anode to 0), it will block current and never light up, even when VOUT correctly outputs 5 V.

Troubleshooting

Symptom: The standby LED is always OFF.
Cause: The LED might be backwards, R2 might be too high in value, or the IC is missing power.
Fix: Check LED orientation (long leg to VLED). Verify U1 pins 14 and 7 are securely connected to VCC and 0.
Symptom: The standby LED is always ON, regardless of the switch.
Cause: The switch is not properly connected to VCC, or the switch contacts are faulty, leaving the input permanently pulled LOW by R1.
Fix: Measure node VA. If it stays at 0 V when the switch is closed, check the wiring from VCC to SW1.
Symptom: The standby LED flickers when the switch is open.
Cause: Node VA is floating. R1 is likely disconnected or incorrectly placed.
Fix: Ensure R1 firmly connects node VA directly to ground (0).

Possible improvements and extensions

Add a «Main System ON» indicator: Connect a green LED and a 330 Ω resistor directly to node VA to show when the main system is actively running, creating a dual-state visual indicator.
Drive multiple standby indicators: Use another of the unused NOT gates in the 74HC04 (e.g., input on pin 3 connected to VA, output on pin 4) to drive a secondary standby indicator or a low-power piezo buzzer.

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Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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