Practical case: 0-9 counter with TTL-compatible reset

0-9 counter with TTL-compatible reset prototype (Maker Style)

Level: Medium — Build a decimal counter that advances from 0 to 9 and resets automatically using a TTL-compatible AND gate.

Objective and use case

You will build a decimal counter based on a 74LS93 ripple counter and a 74HCT08 AND gate. The circuit counts from 0000 to 1001 and automatically resets when 1010 appears.

This is useful for:
– Simple event counters with a decimal display interface
– Clock divider stages for timing experiments
– Learning how asynchronous reset works in ripple counters
– Testing TTL-to-CMOS/HCT logic compatibility in mixed logic designs

Expected outcome:
– QA, QB, QC, and QD show a binary count sequence from 0 to 9
– RESET_NODE goes HIGH only when QB = 1 and QD = 1
– The counter clears immediately when state 1010 is reached
– LEDs on the four outputs visibly repeat the decimal cycle
– Logic supply remains at +5 V, with TTL-compatible levels between the 74LS93 and 74HCT08

Target audience and level: Students and technicians with basic digital electronics experience.

Materials

  • U1: 74LS93 4-bit ripple counter, function: binary count generation
  • U2: 74HCT08 quad 2-input AND gate, function: TTL-compatible reset detection
  • V1: 5 V DC supply, function: power for the logic circuit
  • X1: clock source 0-5 V square wave, function: CLK_IN signal
  • D1: red LED, function: QA indicator
  • D2: red LED, function: QB indicator
  • D3: red LED, function: QC indicator
  • D4: red LED, function: QD indicator
  • R1: 330 Ω resistor, function: current limiting for D1
  • R2: 330 Ω resistor, function: current limiting for D2
  • R3: 330 Ω resistor, function: current limiting for D3
  • R4: 330 Ω resistor, function: current limiting for D4
  • C1: 100 nF capacitor, function: local decoupling for U1
  • C2: 100 nF capacitor, function: local decoupling for U2

Pin-out of the IC used

74LS93

Pin Name Logic function Connection in this case
5 VCC +5 V supply VCC
10 GND Ground 0
14 CP0 Clock input A CLK_IN
1 CP1 Clock input B Connected to QA for cascade
2 R0(1) Asynchronous reset input RESET_NODE
3 R0(2) Asynchronous reset input RESET_NODE
12 QA LSB output QA, LED D1, and feedback to CP1
9 QB Counter output QB, LED D2, and reset detect input
8 QC Counter output QC, LED D3
11 QD MSB output QD, LED D4, and reset detect input

74HCT08

Pin Name Logic function Connection in this case
14 VCC +5 V supply VCC
7 GND Ground 0
1 1 A AND input A QB
2 1B AND input B QD
3 1Y AND output RESET_NODE

Wiring guide

  • V1 connects between VCC and 0.
  • C1 connects between VCC and 0, placed close to U1.

  • C2 connects between VCC and 0, placed close to U2.

  • U1 pin 5 connects to VCC.

  • U1 pin 10 connects to 0.
  • U1 pin 14 connects to CLK_IN.
  • U1 pin 1 connects to node QA.
  • U1 pin 2 connects to RESET_NODE.
  • U1 pin 3 connects to RESET_NODE.
  • U1 pin 12 connects to node QA.
  • U1 pin 9 connects to node QB.
  • U1 pin 8 connects to node QC.

  • U1 pin 11 connects to node QD.

  • U2 pin 14 connects to VCC.

  • U2 pin 7 connects to 0.
  • U2 pin 1 connects to node QB.
  • U2 pin 2 connects to node QD.

  • U2 pin 3 connects to node RESET_NODE.

  • R1 connects between QA and node LED1_A.

  • D1 connects between LED1_A and 0.
  • R2 connects between QB and node LED2_A.
  • D2 connects between LED2_A and 0.
  • R3 connects between QC and node LED3_A.
  • D3 connects between LED3_A and 0.
  • R4 connects between QD and node LED4_A.
  • D4 connects between LED4_A and 0.

Use the 74HCT08, not the 74HC08, because the reset gate is driven by 74LS93 TTL outputs and must accept TTL-compatible HIGH levels reliably.

Conceptual block diagram

Conceptual block diagram — CONTADOR 0-9 counter with reset
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Practical case: 0-9 counter with TTL-compatible reset (74LS93 + 74HCT08)

[ X1: CLK_IN 0-5 V square ] --> [ U1: 74LS93 4-bit Ripple Counter (CP0 pin14) ]
(Internal to U1: QA (pin12) --> CP1 (pin1) for divide-by-10 configuration)

U1 Q outputs to indicators (loads on the right):
[ U1: QA (pin12) ] --> [ R1: 330 Ω ] --> [ D1: Red LED ] --> GND
[ U1: QB (pin9)  ] --> [ R2: 330 Ω ] --> [ D2: Red LED ] --> GND
[ U1: QC (pin8)  ] --> [ R3: 330 Ω ] --> [ D3: Red LED ] --> GND
[ U1: QD (pin11) ] --> [ R4: 330 Ω ] --> [ D4: Red LED ] --> GND

Reset detection (separate branches; TTL-compatible gate):
[ Tap: U1.QB (pin9) ] -->
[ Tap: U1.QD (pin11) ] --> [ U2: 74HCT08 AND (pins 1,2→3) ] --(RESET_NODE)--> (to U1 Async Reset R0(1),R0(2) pins 2 & 3)

Power and decoupling (for completeness):
[ V1: +5 V ] --> [ U1: VCC pin5 ]          ; return GND --> (U1 GND pin10)
[ V1: +5 V ] --> [ U2: VCC pin14 ]         ; return GND --> (U2 GND pin7)
[ C1: 100 nF ] between U1 VCC and GND (place close to U1)
[ C2: 100 nF ] between U2 VCC and GND (place close to U2)
Electrical Schematic

Electrical diagram

Electrical diagram for case: Practical case: 0-9 counter with TTL-compatible reset
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Truth table

This table corresponds to the AND gate used for reset detection.

QB QD RESET_NODE
0 0 0
0 1 0
1 0 0
1 1 1

Measurements and tests

  1. Power-off continuity check
  2. Verify VCC is not shorted to 0.
  3. Confirm U1 reset pins 2 and 3 are tied together at RESET_NODE.

  4. Confirm U1 pin 1 is connected to QA.

  5. Power-on static check

  6. Apply +5 V.
  7. Check that U1 and U2 both receive correct supply voltage.

  8. With no clock applied, outputs may start in an unknown state; a brief manual reset to RESET_NODE = HIGH should force QA QB QC QD = 0000.

  9. Clock verification

  10. Measure CLK_IN with an oscilloscope.
  11. Use a slow frequency such as 1 Hz to 10 Hz for visual LED observation.

  12. Confirm the clock swings approximately from 0 V to 5 V.

  13. Counter sequence check

  14. Measure QA, QB, QC, and QD.
  15. Verify the sequence:
    • 0000
    • 0001
    • 0010
    • 0011
    • 0100
    • 0101
    • 0110
    • 0111
    • 1000
    • 1001

  16. The next attempted state is 1010, but it must reset immediately to 0000.

  17. Reset-node validation

  18. Measure RESET_NODE.
  19. It should remain LOW for counts 0000 through 1001.

  20. It should pulse HIGH when QB = 1 and QD = 1, which corresponds to detection of 1010.

  21. LED observation

  22. D1 must toggle at the highest visible rate.
  23. D2 toggles at half the QA rate.
  24. D3 and D4 toggle progressively slower.
  25. The visible pattern must repeat every 10 clock pulses.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Decade counter 0-9 with reset (Corrected)
.width out=256
* Fixed Impedance and Timing issues for 74LS93 ripple counter
* Ngspice compliant netlist

* --- COMPONENT MODELS ---
* Generic Red LED Model
.model DLED D(IS=1e-14 N=1.7 RS=10 BV=5 IBV=10u CJO=10p)

* --- LOGIC GATE SUBCIRCUITS (Behavioral with Low Impedance Output) ---
* IMPORTANT: Output Impedance reduced to 50 ohms to drive LEDs and avoid loading effects.
* Delays (C1=10p) maintained for convergence and latch feedback.

* Inverter (Standard Delay ~500ps)
.subckt INV A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Decade counter 0-9 with reset (Corrected)
.width out=256
* Fixed Impedance and Timing issues for 74LS93 ripple counter
* Ngspice compliant netlist

* --- COMPONENT MODELS ---
* Generic Red LED Model
.model DLED D(IS=1e-14 N=1.7 RS=10 BV=5 IBV=10u CJO=10p)

* --- LOGIC GATE SUBCIRCUITS (Behavioral with Low Impedance Output) ---
* IMPORTANT: Output Impedance reduced to 50 ohms to drive LEDs and avoid loading effects.
* Delays (C1=10p) maintained for convergence and latch feedback.

* Inverter (Standard Delay ~500ps)
.subckt INV A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* Fast Inverter (Minimal Delay ~5ps) - Used for Clock Edge logic to prevent races
.subckt INV_FAST A Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 / (1 + exp(20 * (V(A) - 2.5))))
R1 Y_int Y 50
C1 Y 0 0.1p
.ends

* 2-Input NAND
.subckt NAND2 A B Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) ))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* 3-Input NAND
.subckt NAND3 A B C Y VCC GND
B1 Y_int 0 V = V(VCC) * (1 - ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) * (1/(1+exp(-20*(V(C)-2.5)))) ))
R1 Y_int Y 50
C1 Y 0 10p
.ends

* 2-Input AND
.subckt AND2 A B Y VCC GND
B1 Y_int 0 V = V(VCC) * ( (1/(1+exp(-20*(V(A)-2.5)))) * (1/(1+exp(-20*(V(B)-2.5)))) )
R1 Y_int Y 50
C1 Y 0 10p
.ends

* --- FLIP-FLOP SUBCIRCUIT ---
* T-FlipFlop: Negative Edge Triggered with Active High Clear
* Uses INV_FAST for clock inversion to ensure Master-Slave non-overlap (Race Fix).
.subckt TFF_NEG_CLR CLK CLR Q QBAR VCC GND
* Invert Clear
XINV_CLR CLR CLR_BAR VCC GND INV

* Invert Clock FAST (Avoids race where both Master and Slave are transparent)
XINV_CLK CLK CLK_BAR VCC GND INV_FAST

* -- Master Latch (Tracks D=QBAR when CLK=1) --
XG1 QBAR CLK M_SET_BAR VCC GND NAND2
XG2 Q CLK CLR_BAR M_RST_BAR VCC GND NAND3
XL1 M_SET_BAR M_QBAR M_Q VCC GND NAND2
XL2 M_RST_BAR M_Q CLR_BAR M_QBAR VCC GND NAND3

* -- Slave Latch (Tracks Master when CLK=0 -> CLK_BAR=1) --
* Uses CLK_BAR which is delayed only slightly less than gates, ensuring clean handover.
XG3 M_Q CLK_BAR S_SET_BAR VCC GND NAND2
XG4 M_QBAR CLK_BAR S_RST_BAR VCC GND NAND2
XL3 S_SET_BAR QBAR Q VCC GND NAND2
XL4 S_RST_BAR Q CLR_BAR QBAR VCC GND NAND3
.ends

* --- IC SUBCIRCUITS ---

* U1: 74LS93 4-Bit Binary Counter
* Pinout mapping adjusted to match standard 14-pin DIP in netlist order:
* 1=IN_B, 2=R0(1), 3=R0(2), 5=VCC, 8=QC, 9=QB, 10=GND, 11=QD, 12=QA, 14=IN_A
.subckt 74LS93 IN_B R0_1 R0_2 VCC QC QB GND QD QA IN_A
* Internal Reset Logic: Reset if R0_1 AND R0_2 are High
XAND_RST R0_1 R0_2 RESET VCC GND AND2

* Section 1: 1-bit counter (Input A -> QA)
XFFA IN_A RESET QA QA_BAR VCC GND TFF_NEG_CLR

* Section 2: 3-bit ripple counter (Input B -> QB -> QC -> QD)
XFFB IN_B RESET QB QB_BAR VCC GND TFF_NEG_CLR
XFFC QB RESET QC QC_BAR VCC GND TFF_NEG_CLR
XFFD QC RESET QD QD_BAR VCC GND TFF_NEG_CLR
.ends

* U2: 74HCT08 Quad 2-Input AND Gate
* HCT input thresholds are TTL-compatible, so 74LS93 HIGH outputs
* reliably drive the reset-detect gate in a real classroom build.
* Pins: 1=1A, 2=1B, 3=1Y, 7=GND, 14=VCC
.subckt 74HCT08 1A 1B 1Y GND VCC
XG1 1A 1B 1Y VCC GND AND2
.ends

* --- MAIN CIRCUIT ---

* 1. Power Supply
V1 VCC 0 DC 5

* 2. Clock Signal (50kHz)
V2 CLK_IN 0 PULSE(0 5 1u 100n 100n 10u 20u)

* 3. U1: 74LS93 Counter
* Wiring Guide connections:
* Pin 1 (CKB) connects to QA_NODE (Cascade)
* Pin 12 (QA) connects to QA_NODE
* Pin 14 (CKA) connects to CLK_IN
* Pin 2, 3 connect to RESET_NODE
* Outputs to LEDs
XU1 QA_NODE RESET_NODE RESET_NODE VCC QC_NODE QB_NODE 0 QD_NODE QA_NODE CLK_IN 74LS93

* 4. U2: 74HCT08 Reset Logic
* Reset when Count=10 (Binary 1010 -> QD=1, QB=1)
* Inputs: QB_NODE, QD_NODE -> Output: RESET_NODE
XU2 QB_NODE QD_NODE RESET_NODE 0 VCC 74HCT08

* 5. LED Indicators (with Current Limiting Resistors)
* Bit 0 (QA)
R1 QA_NODE N_D1 330
D1 N_D1 0 DLED

* Bit 1 (QB)
R2 QB_NODE N_D2 330
D2 N_D2 0 DLED

* Bit 2 (QC)
R3 QC_NODE N_D3 330
D3 N_D3 0 DLED

* Bit 3 (QD)
R4 QD_NODE N_D4 330
D4 N_D4 0 DLED

* --- SIMULATION COMMANDS ---
.op
* Transient analysis: 500us to see counts 0-9 and reset
.tran 100n 500u

* Print essential nodes. CLK_IN first.
.print tran V(CLK_IN) V(QA_NODE) V(QB_NODE) V(QC_NODE) V(QD_NODE) V(RESET_NODE)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation successfully demonstrates a 4-bit counting sequence. The counter increments on the falling edge of the clock. The reset logic triggers correctly when the count reaches 10 (Binary 1010: QD=High, QB=High), forcing the outputs back to 0 immediately, effectively creating a 0-9 decade counter.
* bom_vs_spice equivalences ignored:
*   - Clock source V2 modeled as a PULSE voltage source.
*   - LEDs (D1-D4) modeled as generic diodes with specific parameters (DLED).
*   - U1 (74LS93) modeled as a behavioral subcircuit using flip-flops and logic gates.
*   - U2 (74HCT08) modeled as a behavioral subcircuit using AND gates.
* overall_comment: The circuit is well-designed and the SPICE netlist accurately reflects the intended decade counter logic. The behavioral models for the 74LS93 and 74HCT08 are robust, including necessary delays to prevent race conditions. The simulation logs confirm the modulo-10 reset operation works as expected. This is a solid didactic example.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The simulation successfully demonstrates a 4-bit counting sequence. The counter increments on the falling edge of the clock. The reset logic triggers correctly when the count reaches 10 (Binary 1010: QD=High, QB=High), forcing the outputs back to 0 immediately, effectively creating a 0-9 decade counter.
Show raw data table (6785 rows) 
Index   time            v(clk_in)       v(qa_node)      v(qb_node)      v(qc_node)      v(qd_node)      v(reset_node)
0	0.000000e+00	0.000000e+00	-7.27413e-30	4.514570e+00	-7.27413e-30	-7.27411e-30	9.643749e-22
1	1.000000e-09	0.000000e+00	-6.24961e-30	4.514570e+00	-6.24960e-30	-6.24960e-30	9.643749e-22
2	2.000000e-09	0.000000e+00	-4.31599e-30	4.514570e+00	-4.31599e-30	-4.31599e-30	9.643749e-22
3	4.000000e-09	0.000000e+00	-8.63940e-32	4.514570e+00	-8.63867e-32	-8.63940e-32	9.643749e-22
4	8.000000e-09	0.000000e+00	6.051302e-30	4.514570e+00	6.051309e-30	6.051302e-30	9.643749e-22
5	1.600000e-08	0.000000e+00	8.619372e-30	4.514570e+00	8.619381e-30	8.619372e-30	9.643749e-22
6	3.200000e-08	0.000000e+00	4.420001e-30	4.514570e+00	4.420001e-30	4.419984e-30	9.643749e-22
7	6.400000e-08	0.000000e+00	-8.88725e-31	4.514570e+00	-8.88725e-31	-8.88708e-31	9.643749e-22
8	1.280000e-07	0.000000e+00	-1.16882e-30	4.514570e+00	-1.16881e-30	-1.16884e-30	9.643749e-22
9	2.280000e-07	0.000000e+00	-1.70113e-31	4.514570e+00	-1.70131e-31	-1.70113e-31	9.643749e-22
10	3.280000e-07	0.000000e+00	1.102262e-31	4.514570e+00	1.101893e-31	1.102078e-31	9.643749e-22
11	4.280000e-07	0.000000e+00	-2.09740e-32	4.514570e+00	-2.09440e-32	-2.09556e-32	9.643749e-22
12	5.280000e-07	0.000000e+00	3.730926e-32	4.514570e+00	3.729081e-32	3.729081e-32	9.643749e-22
13	6.280000e-07	0.000000e+00	-4.04764e-32	4.514570e+00	-4.04464e-32	-4.04395e-32	9.643749e-22
14	7.280000e-07	0.000000e+00	3.793658e-32	4.514570e+00	3.789968e-32	3.791813e-32	9.643749e-22
15	8.280000e-07	0.000000e+00	-3.71737e-32	4.514570e+00	-3.71437e-32	-3.71552e-32	9.643749e-22
16	9.280000e-07	0.000000e+00	3.658968e-32	4.514570e+00	3.657123e-32	3.658968e-32	9.643749e-22
17	1.000000e-06	0.000000e+00	-3.53679e-32	4.514570e+00	-3.53610e-32	-3.53496e-32	9.643749e-22
18	1.010000e-06	5.000000e-01	-2.79091e-33	4.514570e+00	-2.80820e-33	-2.79091e-33	9.643749e-22
19	1.030000e-06	1.500000e+00	1.602683e-33	4.514570e+00	1.585385e-33	1.602683e-33	9.643749e-22
20	1.048757e-06	2.437856e+00	4.312441e+00	4.514570e+00	-1.25584e-33	-1.27306e-33	9.643749e-22
21	1.062135e-06	3.106726e+00	4.691659e+00	4.514570e+00	1.096887e-33	1.103161e-33	9.643749e-22
22	1.071814e-06	3.590675e+00	4.366639e+00	4.514570e+00	-8.23695e-34	-8.33794e-34	9.643749e-22
23	1.080871e-06	4.043525e+00	4.636207e+00	4.514570e+00	6.872047e-34	7.032322e-34	9.643749e-22
... (6761 more rows) ...

Common mistakes and how to avoid them

  1. Using 74HC08 instead of 74HCT08
  2. Problem: the 74LS93 HIGH level may not meet standard HC input thresholds reliably.

  3. Solution: use 74HCT08 for TTL-compatible input levels.

  4. Forgetting the QA to CP1 connection

  5. Problem: the 74LS93 will not count correctly through the intended 4-bit sequence.

  6. Solution: connect U1 pin 12 (QA) directly to U1 pin 1 (CP1).

  7. Reset inputs not tied together

  8. Problem: the counter may not clear when 1010 occurs.
  9. Solution: connect both R0(1) and R0(2) to the same RESET_NODE.

Troubleshooting

  • Symptom: The count goes beyond 9.
  • Cause: QB or QD is not correctly connected to the AND gate.

  • Fix: verify U2 pin 1 = QB, U2 pin 2 = QD, and U2 pin 3 = RESET_NODE.

  • Symptom: The circuit never counts.

  • Cause: RESET_NODE is stuck HIGH.

  • Fix: check for miswiring, shorts, or swapped AND gate pins.

  • Symptom: LEDs behave randomly at power-up.

  • Cause: ripple counters can power up in an undefined state.

  • Fix: apply a short reset pulse at startup.

  • Symptom: Reset is unreliable.

  • Cause: wrong logic family used for the reset gate.

  • Fix: replace any 74HC08 with 74HCT08.

  • Symptom: Only the first stage toggles.

  • Cause: missing cascade connection from QA to CP1.
  • Fix: reconnect U1 pin 12 to U1 pin 1.

Possible improvements and extensions

  • Add a BCD-to-7-segment decoder and display so the count is shown directly as digits 0 to 9.
  • Replace the clock source with a debounced push-button for manual stepping and observation of each state.

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Quick Quiz

Question 1: What is the main purpose of adding the 74HCT08 to the 74LS93 counter circuit?




Question 2: Which count sequence should the outputs QA, QB, QC, and QD display before repeating?




Question 3: At which binary state should the counter reset automatically?




Question 4: When does RESET_NODE go HIGH in this design?




Question 5: What supply voltage is specified for the logic circuit?




Question 6: Why is the 74HCT08 suitable in this mixed-logic circuit?




Question 7: What is the role of the 74LS93 in the circuit?




Question 8: What is the function of the four LEDs connected to QA, QB, QC, and QD?




Question 9: What type of reset behavior is being demonstrated in this counter?




Question 10: Which application is mentioned as a use case for this decimal counter?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Conveyor belt object counter

Conveyor belt object counter prototype (Maker Style)

Level: Medium – Build an optical object counter with decimal outputs and an automatic batch reset.

Objective and use case

In this practical case, you will build a sequential optical counting circuit using a Light Dependent Resistor (LDR), a 74HC04 inverter for signal conditioning, and a CD4017BE decade counter. The circuit detects objects breaking a light beam, counts them sequentially using LED indicators, and automatically resets after a batch of 5 items.

This circuit is highly relevant in real-world scenarios:
– Packaging lines: Automatically grouping products into predetermined batch sizes (e.g., 5 items per box).
– Industrial automation: Tracking the movement of discrete parts along a conveyor belt.
– Safety interlocks: Monitoring limit switches or optical barriers to ensure an operation cycle is fully completed.

Expected outcome:
– The LDR voltage divider will swing from HIGH (illuminated) to LOW (beam blocked).
– The 74HC04 inverter will generate a clean, rising clock edge (VB) upon each detection.
– The CD4017BE counter will advance its active logic HIGH signal across outputs Q0 to Q4, lighting up LEDs in sequence.
– When the 6th object is detected (count of 5), output Q5 will trigger the reset pin, instantaneously clearing the count back to 0.

Target audience: Electronics students learning sequential logic, decimal counters, and basic sensor integration.

Materials

  • V1: 5 V DC supply
  • RLDR1: Light Dependent Resistor (LDR), function: optical sensing
  • R1: 10 kΩ resistor, function: voltage divider pull-down for LDR
  • U1: 74HC04, function: logic inverter and clock edge sharpener
  • U2: CD4017BE, function: decade counter with decoded outputs
  • D1: red LED, function: count 0 indicator
  • D2: red LED, function: count 1 indicator
  • D3: red LED, function: count 2 indicator
  • D4: red LED, function: count 3 indicator
  • D5: red LED, function: count 4 indicator
  • R2: 330 Ω resistor, function: LED D1 current limiting
  • R3: 330 Ω resistor, function: LED D2 current limiting
  • R4: 330 Ω resistor, function: LED D3 current limiting
  • R5: 330 Ω resistor, function: LED D4 current limiting
  • R6: 330 Ω resistor, function: LED D5 current limiting
  • C1: 100 nF capacitor, function: U1 decoupling
  • C2: 100 nF capacitor, function: U2 decoupling

Pin-out of the IC used

74HC04 (Hex Inverter)

Pin Name Logic function Connection in this case
1 1A Input Connects to the LDR divider (VA)
2 1Y Output Connects to the U2 clock input (VB)
7 GND Ground Connects to 0
14 VCC Power Connects to VCC

CD4017BE (Decade Counter / Divider)

Pin Name Logic function Connection in this case
14 CLK Clock input Connects to the inverted sensor signal (VB)
13 CKE Clock enable Connects to 0 (active low)
15 RST Reset Connects to Q5 (VC) for automatic reset
3 Q0 Output 0 Connects to the D1 branch (V_Q0)
2 Q1 Output 1 Connects to the D2 branch (V_Q1)
4 Q2 Output 2 Connects to the D3 branch (V_Q2)
7 Q3 Output 3 Connects to the D4 branch (V_Q3)
10 Q4 Output 4 Connects to the D5 branch (V_Q4)
1 Q5 Output 5 Connects to reset (VC)
8 VSS Ground Connects to 0
16 VDD Power Connects to VCC

Note: Pins 5, 6, 9, 11 and 12 are unused decoded outputs and carry-out pins; leave them floating in this case.

Wiring guide

  • V1 connects between VCC and 0.
  • RLDR1 connects between VCC and VA.
  • R1 connects between VA and 0.
  • U1 pin 14 connects to VCC.
  • U1 pin 7 connects to 0.
  • U1 pin 1 connects to VA.
  • U1 pin 2 connects to VB.
  • U2 pin 16 connects to VCC.
  • U2 pin 8 connects to 0.
  • U2 pin 13 connects to 0.
  • U2 pin 14 connects to VB.
  • U2 pin 1 connects to VC.
  • U2 pin 15 connects to VC.
  • U2 pin 3 connects to V_Q0.
  • U2 pin 2 connects to V_Q1.
  • U2 pin 4 connects to V_Q2.
  • U2 pin 7 connects to V_Q3.
  • U2 pin 10 connects to V_Q4.
  • R2 connects between V_Q0 and V_D1.
  • D1 connects between V_D1 and 0.
  • R3 connects between V_Q1 and V_D2.
  • D2 connects between V_D2 and 0.
  • R4 connects between V_Q2 and V_D3.
  • D3 connects between V_D3 and 0.
  • R5 connects between V_Q3 and V_D4.
  • D4 connects between V_D4 and 0.
  • R6 connects between V_Q4 and V_D5.
  • D5 connects between V_D5 and 0.
  • C1 connects between VCC and 0.
  • C2 connects between VCC and 0.

Conceptual block diagram

Conceptual block diagram — 74HC04 Decimal counter
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

[ U2: CD4017BE Decade Counter ]
                                                             |                             |
VCC --> [ RLDR1: LDR ] --(VA)--> [ U1: 74HC04 Inverter ] --(VB)--> CLK (Pin 14)            |
                           |                                 |                  Q0 (Pin 3)-|--(V_Q0)--> [ R2: 330 ] --> [ D1: Red LED ] --> GND
                           +---> [ R1: 10k ] --> GND         |                  Q1 (Pin 2)-|--(V_Q1)--> [ R3: 330 ] --> [ D2: Red LED ] --> GND
                                                             |                  Q2 (Pin 4)-|--(V_Q2)--> [ R4: 330 ] --> [ D3: Red LED ] --> GND
                                                 +--(VC)---------> RST (Pin 15) Q3 (Pin 7)-|--(V_Q3)--> [ R5: 330 ] --> [ D4: Red LED ] --> GND
                                                 |           |                  Q4 (Pin 10)|--(V_Q4)--> [ R6: 330 ] --> [ D5: Red LED ] --> GND
                                                 +---------------< Q5 (Pin 1)              |
                                                             |                             |
                                                 GND ------------> EN (Pin 13)             |
                                                             [-----------------------------]

* Power & Decoupling Notes:
  VCC --> [ C1: 100nF ] --> GND  (U1 Decoupling)
  VCC --> [ C2: 100nF ] --> GND  (U2 Decoupling)
  U1 Power: Pin 14 (VCC), Pin 7 (GND)
  U2 Power: Pin 16 (VCC), Pin 8 (GND)
Electrical Schematic

Electrical diagram

Electrical diagram for case: Conveyor belt object counter
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the 7-day pass or the monthly membership you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Measurements and tests

  1. Sensor Calibration: Measure node VA with a multimeter. Ensure it rests at >4.0 V when the light source shines on the LDR, and drops to <1.0 V when an object blocks the beam. Adjust R1 if your LDR has different resistance characteristics.
  2. Clock Edge Verification: Connect an oscilloscope to node VB. Pass an object through the beam and confirm a sharp, clean transition from 0 V to 5 V.
  3. Sequential Counting Check: Monitor nodes V_Q0 through V_Q4. Verify that each output successively jumps to ~5 V upon each clock pulse, lighting up D1 through D5 one by one.
  4. Auto-Reset Validation: Using an oscilloscope, monitor VC (Reset). When the 6th object passes, capture the brief microsecond high pulse on VC that clears the counter back to D1.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Conveyor belt object counter
.width out=256

* --- Digital Subcircuits ---

* Analog Behavioral D-Flip-Flop with Asynchronous Reset
.subckt DFF D CLK RST Q
B_M M_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(D)>2.5 ? 5 : 0))
R_M M_int M_state 100
C_M M_state 0 1n

B_S S_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(S_state)>2.5 ? 5 : 0))
R_S S_int S_state 100
C_S S_state 0 1n

B_Q Q_int 0 V = V(S_state)>2.5 ? 5 : 0
R_Q Q_int Q 100
C_Q Q 0 1n
.ends

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Conveyor belt object counter
.width out=256

* --- Digital Subcircuits ---

* Analog Behavioral D-Flip-Flop with Asynchronous Reset
.subckt DFF D CLK RST Q
B_M M_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(D)>2.5 ? 5 : 0))
R_M M_int M_state 100
C_M M_state 0 1n

B_S S_int 0 V = V(RST)>2.5 ? 0 : (V(CLK)>2.5 ? (V(M_state)>2.5 ? 5 : 0) : (V(S_state)>2.5 ? 5 : 0))
R_S S_int S_state 100
C_S S_state 0 1n

B_Q Q_int 0 V = V(S_state)>2.5 ? 5 : 0
R_Q Q_int Q 100
C_Q Q 0 1n
.ends

* CD4017BE Decade Counter (5-stage Johnson Counter with decoded outputs)
* Pins: 1:Q5(VC), 2:Q1, 3:Q0, 4:Q2, 7:Q3, 8:GND, 10:Q4, 13:EN, 14:CLK, 15:RST, 16:VCC
.subckt CD4017 1 2 3 4 7 8 10 13 14 15 16
B_CLK_INT CLK_INT 0 V = (V(14)>2.5) * (V(13)<2.5) * 5
R_CLK CLK_INT CLK_F 100
C_CLK CLK_F 0 1n

XF1 D1 CLK_F 15 F1 DFF
XF2 F1 CLK_F 15 F2 DFF
XF3 F2 CLK_F 15 F3 DFF
XF4 F3 CLK_F 15 F4 DFF
XF5 F4 CLK_F 15 F5 DFF

B_D1_int D1_int 0 V = V(F5)>2.5 ? 0 : 5
R_D1 D1_int D1 100
C_D1 D1 0 1n

B_Q0_int Q0_int 0 V = (V(F1)<2.5) * (V(F5)<2.5) * 5
R_Q0 Q0_int 3 100
C_Q0 3 0 1n

B_Q1_int Q1_int 0 V = (V(F1)>2.5) * (V(F2)<2.5) * 5
R_Q1 Q1_int 2 100
C_Q1 2 0 1n

B_Q2_int Q2_int 0 V = (V(F2)>2.5) * (V(F3)<2.5) * 5
R_Q2 Q2_int 4 100
C_Q2 4 0 1n

B_Q3_int Q3_int 0 V = (V(F3)>2.5) * (V(F4)<2.5) * 5
R_Q3 Q3_int 7 100
C_Q3 7 0 1n

B_Q4_int Q4_int 0 V = (V(F4)>2.5) * (V(F5)<2.5) * 5
R_Q4 Q4_int 10 100
C_Q4 10 0 1n

* Q5 output is used for the modulo-5 reset via VC, so it uses a slightly larger delay 
* to guarantee the reset pulse is wide enough to clear all DFFs.
B_Q5_int Q5_int 0 V = (V(F5)>2.5) * (V(F1)>2.5) * 5
R_Q5 Q5_int 1 100
C_Q5 1 0 10n

* Dummy loads to prevent warnings on power pins
R_GND 8 0 1
R_VCC 16 0 1Meg
.ends

* 74HC04 Hex Inverter (single gate modeled for pins 1, 2)
* Pins: 1:A, 2:Y, 7:GND, 14:VCC
.subckt 74HC04 1 2 7 14
B_Y_int Y_int 0 V = V(1)>2.5 ? 0 : 5
R_Y Y_int 2 100
C_Y 2 0 1n
R_GND 7 0 1
R_VCC 14 0 1Meg
.ends

* --- Main Circuit ---

* Power Supply
V1 VCC 0 DC 5

* Optical Sensing (LDR and pull-down divider)
* Conveyor beam is normally ON (light=1), LDR is 1k. 
* When object passes, light is blocked (light=0), LDR becomes 100k.
V_LIGHT N_LIGHT 0 PULSE(1 0 0.1 0.05 0.05 0.2 0.5)
R_LIGHT N_LIGHT 0 1Meg 
RLDR1 VCC VA R='V(N_LIGHT) > 0.5 ? 1k : 100k'
R1 VA 0 10k

* Edge sharpener and logic inverter
XU1 VA VB 0 VCC 74HC04

* Decade Counter
XU2 VC V_Q1 V_Q0 V_Q2 V_Q3 0 V_Q4 0 VB VC VCC CD4017

* LED Output Indicators
.model RED_LED D(IS=1e-18 N=1.8 RS=10)

R2 V_Q0 V_D1 330
D1 V_D1 0 RED_LED

R3 V_Q1 V_D2 330
D2 V_D2 0 RED_LED

R4 V_Q2 V_D3 330
D3 V_D3 0 RED_LED

R5 V_Q3 V_D4 330
D4 V_D4 0 RED_LED

R6 V_Q4 V_D5 330
D5 V_D5 0 RED_LED

* Decoupling Capacitors
C1 VCC 0 100n
C2 VCC 0 100n

* Dummy IN/OUT assignments for strict output requirements
R_IN VA IN 1
R_IN_GND IN 0 100Meg
R_OUT V_Q4 OUT 1
R_OUT_GND OUT 0 100Meg

* --- Simulation Commands ---
.op
.tran 1m 3.0
.print tran V(IN) V(OUT) V(VA) V(V_Q0) V(V_Q1) V(V_Q2) V(V_Q3) V(V_Q4)

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The simulation shows the input signal (VA) toggling between ~4.5V and ~0.45V, representing the LDR state changes. The outputs V_Q0 to V_Q4 sequentially pulse high to ~4.25V, confirming the decade counter is advancing correctly with each input pulse.
Show raw data table (3128 rows) 
Index   time            v(in)           v(out)          v(va)           v(v_q0)         v(v_q1)         v(v_q2)         v(v_q3)         v(v_q4)
0	0.000000e+00	4.545413e+00	7.813983e-36	4.545413e+00	7.814080e-36	4.250409e+00	7.814080e-36	7.814080e-36	7.813983e-36
1	1.000000e-05	4.545413e+00	7.736609e-38	4.545413e+00	7.736713e-38	4.250409e+00	7.736713e-38	7.736713e-38	7.736609e-38
2	2.000000e-05	4.545413e+00	7.660001e-40	4.545413e+00	7.660112e-40	4.250409e+00	7.660112e-40	7.660112e-40	7.660001e-40
3	4.000000e-05	4.545413e+00	-7.50832e-40	4.545413e+00	-7.50843e-40	4.250409e+00	-7.50843e-40	-7.50843e-40	-7.50832e-40
4	8.000000e-05	4.545413e+00	7.433609e-40	4.545413e+00	7.433716e-40	4.250409e+00	7.433716e-40	7.433716e-40	7.433609e-40
5	1.600000e-04	4.545413e+00	-7.39653e-40	4.545413e+00	-7.39664e-40	4.250409e+00	-7.39664e-40	-7.39664e-40	-7.39653e-40
6	3.200000e-04	4.545413e+00	7.378065e-40	4.545413e+00	7.378171e-40	4.250409e+00	7.378171e-40	7.378171e-40	7.378065e-40
7	6.400000e-04	4.545413e+00	-7.36885e-40	4.545413e+00	-7.36895e-40	4.250409e+00	-7.36895e-40	-7.36895e-40	-7.36885e-40
8	1.280000e-03	4.545413e+00	7.364244e-40	4.545413e+00	7.364350e-40	4.250409e+00	7.364350e-40	7.364350e-40	7.364244e-40
9	2.280000e-03	4.545413e+00	-7.36130e-40	4.545413e+00	-7.36141e-40	4.250409e+00	-7.36141e-40	-7.36141e-40	-7.36130e-40
10	3.280000e-03	4.545413e+00	7.358355e-40	4.545413e+00	7.358461e-40	4.250409e+00	7.358461e-40	7.358461e-40	7.358355e-40
11	4.280000e-03	4.545413e+00	-7.35541e-40	4.545413e+00	-7.35552e-40	4.250409e+00	-7.35552e-40	-7.35552e-40	-7.35541e-40
12	5.280000e-03	4.545413e+00	7.352471e-40	4.545413e+00	7.352577e-40	4.250409e+00	7.352577e-40	7.352577e-40	7.352471e-40
13	6.280000e-03	4.545413e+00	-7.34953e-40	4.545413e+00	-7.34964e-40	4.250409e+00	-7.34964e-40	-7.34964e-40	-7.34953e-40
14	7.280000e-03	4.545413e+00	7.346591e-40	4.545413e+00	7.346697e-40	4.250409e+00	7.346697e-40	7.346697e-40	7.346591e-40
15	8.280000e-03	4.545413e+00	-7.34365e-40	4.545413e+00	-7.34376e-40	4.250409e+00	-7.34376e-40	-7.34376e-40	-7.34365e-40
16	9.280000e-03	4.545413e+00	7.340716e-40	4.545413e+00	7.340822e-40	4.250409e+00	7.340822e-40	7.340822e-40	7.340716e-40
17	1.028000e-02	4.545413e+00	-7.33778e-40	4.545413e+00	-7.33789e-40	4.250409e+00	-7.33789e-40	-7.33789e-40	-7.33778e-40
18	1.128000e-02	4.545413e+00	7.334846e-40	4.545413e+00	7.334952e-40	4.250409e+00	7.334952e-40	7.334952e-40	7.334846e-40
19	1.228000e-02	4.545413e+00	-7.33191e-40	4.545413e+00	-7.33202e-40	4.250409e+00	-7.33202e-40	-7.33202e-40	-7.33191e-40
20	1.328000e-02	4.545413e+00	7.328981e-40	4.545413e+00	7.329086e-40	4.250409e+00	7.329086e-40	7.329086e-40	7.328981e-40
21	1.428000e-02	4.545413e+00	-7.32605e-40	4.545413e+00	-7.32616e-40	4.250409e+00	-7.32616e-40	-7.32616e-40	-7.32605e-40
22	1.528000e-02	4.545413e+00	7.323120e-40	4.545413e+00	7.323225e-40	4.250409e+00	7.323225e-40	7.323225e-40	7.323120e-40
23	1.628000e-02	4.545413e+00	-7.32019e-40	4.545413e+00	-7.32030e-40	4.250409e+00	-7.32030e-40	-7.32030e-40	-7.32019e-40
... (3104 more rows) ...

Common mistakes and how to avoid them

  1. Leaving Clock Enable floating: Pin 13 (CKE) on the CD4017BE is active low. If left unconnected, ambient electrical noise will disable the clock input irregularly. Always tie it directly to Ground (0).
  2. Missing LED current limiters: Connecting LEDs directly to the CD4017BE outputs will draw too much current, potentially burning out the decoded output stages of the IC. Always use individual resistors (e.g., 330 Ω) for each LED.
  3. Slow sensor transitions: The 74HC04 inverter buffers the signal, but slowly moving objects on a conveyor belt might still cause the logic threshold to linger, causing multiple rapid clock pulses (contact bounce equivalent). If objects move very slowly, replace the 74HC04 with a Schmitt trigger inverter (like the 74HC14) for severe hysteresis.

Troubleshooting

  • Symptom: The counter skips numbers or counts randomly.
  • Cause: Electrical noise on the LDR line or mechanical vibrations affecting the light source.
  • Fix: Add a small 10 nF capacitor between VA and 0 to filter out high-frequency optical or electrical jitter.
  • Symptom: Circuit stays permanently on LED D1 (Count 0) and never advances.
  • Cause: The Reset pin (15) is stuck HIGH, or Clock Enable (13) is stuck HIGH.
  • Fix: Verify the connection between Q5 and Reset. Ensure Pin 13 is firmly grounded.
  • Symptom: LEDs are extremely dim.
  • Cause: The current limiting resistors are too large, or the power supply cannot deliver enough current.
  • Fix: Check that R2-R6 are exactly 330 Ω, not 330 kΩ. Confirm the VCC supply is maintaining a steady 5 V.

Possible improvements and extensions

  1. Numerical Display: Replace the 10-LED output logic by substituting the CD4017BE with a CD4026BE, allowing you to directly drive a 7-segment numerical display for a true digit read-out.
  2. Monostable Debouncing: Insert a 555 timer configured as a monostable multivibrator between the sensor inverter (VB) and the counter’s clock input. This guarantees a single, fixed-duration clock pulse per object, entirely eliminating false double-counts regardless of object shape or speed.

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Quick Quiz

Question 1: What is the primary function of the LDR in this circuit?




Question 2: Which component is used for signal conditioning and generating a clean clock edge?




Question 3: What happens to the LDR voltage divider when the light beam is blocked?




Question 4: What is the role of the CD4017BE in this project?




Question 5: After how many items does the circuit automatically reset the batch?




Question 6: What happens when the 6th object is detected by the circuit?




Question 7: What type of clock edge does the 74HC04 inverter generate upon each detection?




Question 8: What type of signal does the CD4017BE advance across its outputs (Q0 to Q4) during counting?




Question 9: Which of the following is listed as a real-world use case for this circuit?




Question 10: What does the circuit use to indicate the sequential count?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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