Practical case: Alarm Lockout Logic with NAND

Alarm Lockout Logic with NAND prototype (Maker Style)

Level: Basic – Build an active-high alarm indicator using 74HC00 NAND gates to understand universal logic and signal inversion.

Objective and use case

You will build a digital logic circuit where an alarm sensor and an enable switch must both be triggered to turn on a warning LED, implemented entirely with a single 74HC00 NAND gate chip.

This circuit is highly useful for demonstrating fundamental digital concepts:
* It demonstrates the concept of «universal gates,» showing how a NAND gate can be wired as a NOT gate (inverter) to achieve an AND logic function.
* It illustrates how an «enable» signal works, which is an industry standard method to authorize or safely block system operations.
* It provides hands-on practice with handling CMOS logic levels and configuring pull-down networks for reliable switch operation.

Expected outcome:
* The intermediate signal (the output of the first NAND gate) will output a logic LOW (0 V) only when both inputs are HIGH (5 V).
* The final output will be logic HIGH (5 V) and will light the LED strictly when both the Alarm and Enable inputs are HIGH.
* You will practically verify the combined truth table of a NAND and a NOT gate.

Target audience: Beginners in digital electronics learning how to manipulate logic gates.

Materials

  • V1: 5 V DC supply
  • SW1: SPST switch, function: Alarm trigger
  • SW2: SPST switch, function: Enable signal
  • R1: 10 kΩ resistor, function: pull-down for ALARM node
  • R2: 10 kΩ resistor, function: pull-down for ENABLE node
  • R3: 330 Ω resistor, function: LED current limiting
  • U1: 74HC00 Quad 2-Input NAND Gate, function: logic evaluation and inversion
  • D1: Red LED, function: Alarm indicator

Pin-out of the IC used

74HC00 (Quad 2-Input NAND Gate)

Pin Name Logic function Connection in this case
1 1 A Input 1 of NAND A Node ALARM (from SW1)
2 1B Input 2 of NAND A Node ENABLE (from SW2)
3 1Y Output of NAND A Node INTERMEDIATE
4 2 A Input 1 of NAND B Node INTERMEDIATE
5 2B Input 2 of NAND B Node INTERMEDIATE
6 2Y Output of NAND B Node VOUT
7 GND Ground Node 0
14 VCC Supply Voltage Node VCC

(Note: The 74HC00 contains four independent NAND gates. In this circuit, we use gates A and B. Unused inputs on gates C and D should be tied to ground).

Wiring guide

  • V1: connects between VCC and 0.
  • SW1: connects between VCC and ALARM.
  • R1: connects between ALARM and 0.
  • SW2: connects between VCC and ENABLE.
  • R2: connects between ENABLE and 0.
  • U1 Pin 14 (VCC): connects to VCC.
  • U1 Pin 7 (GND): connects to 0.
  • U1 Pin 1 (1 A): connects to ALARM.
  • U1 Pin 2 (1B): connects to ENABLE.
  • U1 Pin 3 (1Y): connects to INTERMEDIATE.
  • U1 Pin 4 (2 A): connects to INTERMEDIATE.
  • U1 Pin 5 (2B): connects to INTERMEDIATE.
  • U1 Pin 6 (2Y): connects to VOUT.
  • D1: Anode connects to VOUT, Cathode connects to NODE_LED.
  • R3: connects between NODE_LED and 0.
  • Safety connection: Connect pins 9, 10, 12, and 13 of U1 to 0 (GND) to prevent unused gates from floating.

Conceptual block diagram

Conceptual block diagram — PIN Alarm Blocking Logic
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

VCC --> [ SW1 ] --(ALARM)--> [ U1: Pin 1 (1 A) ]
           |                      |
         [ R1 ]                   |
           |                 [ U1: Gate 1 (NAND) ] --(INTERMEDIATE)--> [ U1: Pins 4,5 (2 A,2B) ]
          GND                     |                                         |
                                  |                                    [ U1: Gate 2 (NAND) ] --(VOUT)--> [ D1: LED ] --(NODE_LED)--> [ R3 ] --> GND
VCC --> [ SW2 ] --(ENABLE)-> [ U1: Pin 2 (1B) ]
           |
         [ R2 ]
           |
          GND

* Power & Safety Connections:
VCC --> [ U1: Pin 14 (VCC) ]
GND <-- [ U1: Pin 7 (GND) ]
GND <-- [ U1: Pins 9, 10, 12, 13 (Unused) ]
Electrical Schematic

Truth table

Alarm (SW1) Enable (SW2) Intermediate Node (1Y) Output Node (2Y) LED State
0 0 1 0 OFF
0 1 1 0 OFF
1 0 1 0 OFF
1 1 0 1 ON

Measurements and tests

  1. Use a multimeter to verify the power supply is exactly 5 V across the VCC and 0 nodes.
  2. Probe the ALARM and ENABLE nodes relative to 0. Verify they read exactly 0 V when their respective switches are open, and 5 V when closed.
  3. Probe the INTERMEDIATE node. It should read ~5 V when either or both switches are open, and drop to ~0 V strictly when both switches are closed.
  4. Probe the VOUT node. It should always display the exact opposite logic level of the INTERMEDIATE node.
  5. Visually confirm that the LED turns on if and only if both switches are toggled to the closed (active) position.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Alarm Lockout Logic with NAND

* Main DC Supply
V1 VCC 0 DC 5

* Control signals to simulate user pressing the switches (Testing Truth Table)
V_ctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
V_ctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)

* SW1: SPST switch (Alarm trigger)
S1 VCC ALARM ctrl1 0 SW_MODEL

* SW2: SPST switch (Enable signal)
S2 VCC ENABLE ctrl2 0 SW_MODEL
.model SW_MODEL SW(VT=2.5 VH=0.5 RON=0.1 ROFF=100MEG)

* Pull-down resistors for logic inputs
R1 ALARM 0 10k
R2 ENABLE 0 10k

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

* Alarm Lockout Logic with NAND

* Main DC Supply
V1 VCC 0 DC 5

* Control signals to simulate user pressing the switches (Testing Truth Table)
V_ctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
V_ctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)

* SW1: SPST switch (Alarm trigger)
S1 VCC ALARM ctrl1 0 SW_MODEL

* SW2: SPST switch (Enable signal)
S2 VCC ENABLE ctrl2 0 SW_MODEL
.model SW_MODEL SW(VT=2.5 VH=0.5 RON=0.1 ROFF=100MEG)

* Pull-down resistors for logic inputs
R1 ALARM 0 10k
R2 ENABLE 0 10k

* U1: 74HC00 Quad 2-Input NAND Gate
* Pinout: 1:1A, 2:1B, 3:1Y, 4:2A, 5:2B, 6:2Y, 7:GND, 8:3Y, 9:3A, 10:3B, 11:4Y, 12:4A, 13:4B, 14:VCC
XU1 ALARM ENABLE INTERMEDIATE INTERMEDIATE INTERMEDIATE VOUT 0 NC8 0 0 NC11 0 0 VCC HC00_DIP14

* D1: Red LED (Alarm indicator)
D1 VOUT NODE_LED DLED
.model DLED D(IS=1e-20 N=2.2 RS=15)

* R3: LED current limiting resistor
R3 NODE_LED 0 330

* Subcircuit for 74HC00 (Quad 2-Input NAND Gate)
.subckt HC00_DIP14 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Gate 1
B1 3_int 7 V=V(14)*(1-(1/(1+exp(-50*(V(1)-2.5))))*(1/(1+exp(-50*(V(2)-2.5)))))
R1 3_int 3 50
* Gate 2
B2 6_int 7 V=V(14)*(1-(1/(1+exp(-50*(V(4)-2.5))))*(1/(1+exp(-50*(V(5)-2.5)))))
R2 6_int 6 50
* Gate 3
B3 8_int 7 V=V(14)*(1-(1/(1+exp(-50*(V(9)-2.5))))*(1/(1+exp(-50*(V(10)-2.5)))))
R3 8_int 8 50
* Gate 4
B4 11_int 7 V=V(14)*(1-(1/(1+exp(-50*(V(12)-2.5))))*(1/(1+exp(-50*(V(13)-2.5)))))
R4 11_int 11 50
.ends

* Analysis directives
.tran 1u 500u
.print tran V(ALARM) V(ENABLE) V(VOUT) V(NODE_LED)
.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The transient simulation shows the output node (VOUT) and LED node (NODE_LED) going high (approx 4.66V and 2.22V respectively) only when both ALARM and ENABLE inputs are high (approx 5V). When either or both inputs are low, the output is near 0V. This matches the intended AND logic behavior created by using two NAND gates in series.
Show raw data table (691 rows) 
Index   time            v(alarm)        v(enable)       v(vout)         v(node_led)
0	0.000000e+00	4.999500e-04	4.999500e-04	1.047185e-47	-6.91142e-47
1	1.000000e-08	4.999500e-04	4.999500e-04	7.268458e-64	-4.79767e-63
2	2.000000e-08	4.999500e-04	4.999500e-04	-7.26994e-64	4.797672e-63
3	4.000000e-08	4.999500e-04	4.999500e-04	-7.41841e-68	-2.28156e-77
4	8.000000e-08	4.999500e-04	4.999500e-04	-7.41841e-68	-2.51468e-77
5	1.600000e-07	4.999500e-04	4.999500e-04	-7.41841e-68	-2.44808e-77
6	3.200000e-07	4.999500e-04	4.999500e-04	-7.41841e-68	-2.44808e-77
7	3.750000e-07	4.999500e-04	4.999500e-04	-7.41841e-68	-2.44808e-77
8	4.712500e-07	4.999500e-04	4.999500e-04	-7.41841e-68	-2.44808e-77
9	4.978906e-07	4.999500e-04	4.999500e-04	-7.41841e-68	-2.44808e-77
10	5.445117e-07	4.999500e-04	4.999500e-04	-7.41841e-68	-2.44808e-77
11	5.574158e-07	4.999500e-04	4.999500e-04	-7.41841e-68	-2.44808e-77
12	5.799979e-07	4.999500e-04	4.999500e-04	-7.41841e-68	-2.44808e-77
13	6.049995e-07	4.999950e+00	4.999950e+00	4.662865e+00	2.225088e+00
14	6.550027e-07	4.999950e+00	4.999950e+00	4.662939e+00	2.224602e+00
15	7.550091e-07	4.999950e+00	4.999950e+00	4.662792e+00	2.225571e+00
16	9.550219e-07	4.999950e+00	4.999950e+00	4.662792e+00	2.225574e+00
17	1.000000e-06	4.999950e+00	4.999950e+00	4.662786e+00	2.225611e+00
18	1.040003e-06	4.999950e+00	4.999950e+00	4.662786e+00	2.225611e+00
19	1.120008e-06	4.999950e+00	4.999950e+00	4.662786e+00	2.225611e+00
20	1.280018e-06	4.999950e+00	4.999950e+00	4.662786e+00	2.225611e+00
21	1.600038e-06	4.999950e+00	4.999950e+00	4.662786e+00	2.225611e+00
22	2.240079e-06	4.999950e+00	4.999950e+00	4.662786e+00	2.225611e+00
23	3.240079e-06	4.999950e+00	4.999950e+00	4.662786e+00	2.225611e+00
... (667 more rows) ...


Reference SPICE netlist (ngspice)

* Alarm Lockout Logic with NAND

* Main DC Supply
V1 VCC 0 DC 5

* Control signals to simulate user pressing the switches (Testing Truth Table)
V_ctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
V_ctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)

* SW1: SPST switch (Alarm trigger)
S1 VCC ALARM ctrl1 0 SW_MODEL

* SW2: SPST switch (Enable signal)
S2 VCC ENABLE ctrl2 0 SW_MODEL
.model SW_MODEL SW(VT=2.5 VH=0.5 RON=0.1 ROFF=100MEG)

* Pull-down resistors for logic inputs
R1 ALARM 0 10k
R2 ENABLE 0 10k

* U1: 74HC00 Quad 2-Input NAND Gate
* Pinout: 1:1A, 2:1B, 3:1Y, 4:2A, 5:2B, 6:2Y, 7:GND, 8:3Y, 9:3A, 10:3B, 11:4Y, 12:4A, 13:4B, 14:VCC
XU1 ALARM ENABLE INTERMEDIATE INTERMEDIATE INTERMEDIATE VOUT 0 NC8 0 0 NC11 0 0 VCC HC00_DIP14

* D1: Red LED (Alarm indicator)
D1 VOUT NODE_LED DLED
.model DLED D(IS=1e-20 N=2.2 RS=15)

* R3: LED current limiting resistor
R3 NODE_LED 0 330

* Subcircuit for 74HC00 (Quad 2-Input NAND Gate)
.subckt HC00_DIP14 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Gate 1
B1 3_int 7 V=V(14)*(1-(1/(1+exp(-50*(V(1)-2.5))))*(1/(1+exp(-50*(V(2)-2.5)))))
R1 3_int 3 50
* Gate 2
B2 6_int 7 V=V(14)*(1-(1/(1+exp(-50*(V(4)-2.5))))*(1/(1+exp(-50*(V(5)-2.5)))))
R2 6_int 6 50
* Gate 3
B3 8_int 7 V=V(14)*(1-(1/(1+exp(-50*(V(9)-2.5))))*(1/(1+exp(-50*(V(10)-2.5)))))
R3 8_int 8 50
* Gate 4
B4 11_int 7 V=V(14)*(1-(1/(1+exp(-50*(V(12)-2.5))))*(1/(1+exp(-50*(V(13)-2.5)))))
R4 11_int 11 50
.ends

* Analysis directives
.tran 1u 500u
.print tran V(ALARM) V(ENABLE) V(VOUT) V(NODE_LED)
.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The transient simulation shows the output node (VOUT) and LED node (NODE_LED) going high (approx 4.66V and 2.22V respectively) only when both ALARM and ENABLE inputs are high (approx 5V). When either or both inputs are low, the output is near 0V. This matches the intended AND logic behavior created by using two NAND gates in series.

Common mistakes and how to avoid them

  1. Leaving unused inputs floating: CMOS chips like the 74HC00 are highly sensitive to static and ambient noise. Unused gate inputs (pins 9, 10, 12, 13) must be explicitly tied to ground (0) or VCC.
  2. Omitting the pull-down resistors: Without R1 and R2, the input pins will float when the switches are open, leading to unpredictable, flickering behavior in the LED. Always ensure the 10 kΩ pull-downs are securely connected to ground.
  3. Connecting the LED without a series resistor: Connecting D1 directly between VOUT and 0 will draw excessive current, potentially destroying the LED and burning out the output stage of the 74HC00 chip. R3 is mandatory.


Troubleshooting

  • Symptom: The LED never turns off, regardless of switch positions.
  • Cause: One of the input pull-down resistors is loose, causing the chip to read a false HIGH, or the intermediate node isn’t wired correctly to both inputs of the second gate.
  • Fix: Verify connections for R1 and R2 to ground. Ensure U1 Pin 3 routes precisely to both Pin 4 and Pin 5.
  • Symptom: The LED brightness flickers when a hand is moved near the circuit.
  • Cause: A floating input is acting as an antenna and picking up environmental noise.
  • Fix: Check that all unused inputs on the IC are tied to ground, and ensure R1 and R2 are seated firmly in the breadboard.
  • Symptom: The IC becomes hot to the touch.
  • Cause: The power supply is connected backwards, or the output node is shorted directly to ground or VCC.
  • Fix: Disconnect power immediately. Verify that U1 Pin 14 goes strictly to +5 V and Pin 7 goes strictly to Ground.

Possible improvements and extensions

  1. Master Override switch: Introduce a third switch and utilize one of the spare NAND gates (e.g., Gate C) to create a «Master Override» that forces the LED off regardless of the Alarm and Enable signals.
  2. Add a delay circuit: Incorporate an RC network (a resistor and a capacitor) between one of the switches and its input pin. This requires the switch to be held closed for a specific duration before the logic gate registers a HIGH signal, preventing false alarms.

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Quick Quiz

Question 1: What is the main objective of the circuit described in the article?




Question 2: Which logic gate chip is used exclusively in this project?




Question 3: How is the AND logic function achieved in this circuit using only NAND gates?




Question 4: What is the purpose of the 'enable' signal in this system?




Question 5: What is the expected voltage of the intermediate signal (output of the first NAND gate) when both inputs are HIGH?




Question 6: Under what condition will the final output light the warning LED?




Question 7: Why are pull-down networks used in this circuit?




Question 8: What logic family's levels does this project provide hands-on practice with?




Question 9: What combined truth table will you practically verify in this project?




Question 10: What is the difficulty level of this project?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Open door alarm with inhibition

Open door alarm with inhibition prototype (Maker Style)

Level: Basic – Design a logic circuit using a 74HC00 NAND gate to trigger an LED alarm only when the door is open and the system is enabled.

Objective and use case

What you will build is a basic security system logic controller using the universal 74HC00 NAND chip. The circuit processes two discrete inputs (a door sensor and an enable switch) to activate a visual alarm strictly when the system is armed and a breach occurs.

Why it is useful:
* It demonstrates how multiple NAND gates can be combined to form an AND logic gate.
* It illustrates the concept of a hardware «enable/inhibit» signal commonly used in industrial and digital electronics.
* It provides practical experience in interfacing mechanical switches with digital CMOS inputs without floating states.

Expected outcome:
* When the door switch is open (Logic 1) AND the enable switch is closed (Logic 1), the LED turns ON.
* If the enable switch is open (Logic 0), the alarm remains inhibited (LED OFF) regardless of the door state.
* Logic High (VCC) and Logic Low (0 V) voltages can be clearly measured at the switch output nodes.
* The intermediate logic signal between the two NAND gates will correctly show the inverted state of the final output.

Target audience and level: Electronics beginners learning digital logic and combinational circuits.

Materials

  • V1: 5 V DC supply, function: main circuit power
  • SW1: SPST switch, function: door sensor (closed = logic 0, open = logic 1)
  • SW2: SPST switch, function: system enable (inhibited = logic 0, armed = logic 1)
  • R1: 10 kΩ resistor, function: pull-down for SW1 at node DOOR
  • R2: 10 kΩ resistor, function: pull-down for SW2 at node EN
  • R3: 330 Ω resistor, function: LED current limiting
  • U1: 74HC00 quad 2-input NAND gate, function: logic processing
  • D1: red LED, function: visual alarm indicator

Pin-out of the IC used

IC used: 74HC00 (Quad 2-Input NAND Gate)

Pin Name Logic function Connection in this case
1 1 A Input A of Gate 1 Node DOOR (from SW1)
2 1B Input B of Gate 1 Node EN (from SW2)
3 1Y Output of Gate 1 Node NAND_OUT
4 2 A Input A of Gate 2 Node NAND_OUT (tied to 2B)
5 2B Input B of Gate 2 Node NAND_OUT (tied to 2 A)
6 2Y Output of Gate 2 Node ALARM
7 GND Ground reference Node 0
14 VCC Positive supply Node VCC

(Note: Unused input pins 9, 10, 12, and 13 should be tied to ground in physical builds to prevent CMOS oscillation.)

Wiring guide

  • V1: connects between VCC (positive) and 0 (GND).
  • SW1: connects between VCC and DOOR.
  • R1: connects between DOOR and 0.
  • SW2: connects between VCC and EN.
  • R2: connects between EN and 0.
  • U1:
  • Pin 1 connects to DOOR.
  • Pin 2 connects to EN.
  • Pin 3 connects to NAND_OUT.
  • Pin 4 connects to NAND_OUT.
  • Pin 5 connects to NAND_OUT.
  • Pin 6 connects to ALARM.
  • Pin 7 connects to 0.
  • Pin 14 connects to VCC.
  • R3: connects between ALARM and LED_IN.
  • D1: anode connects to LED_IN, cathode connects to 0.

Conceptual block diagram

Conceptual block diagram — NAND1 NAND gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

VCC --> [ SW1: Door Sensor ] --+--(DOOR)----->+
                               |              |
                         [ R1: 10 kΩ ]         v
                               |        [ U1: NAND1 ] --(NAND_OUT)--> [ U1: NAND2 ] --(ALARM)--> [ R3: 330 Ω ] --(LED_IN)--> [ D1: Red LED ] --> GND
                              GND       [ Pins 1,2->3 ]               [ Pins 4,5->6 ]
                                              ^
                                              |
VCC --> [ SW2: Sys Enable ] ---+--(EN)------->+
                               |
                         [ R2: 10 kΩ ]
                               |
                              GND
Electrical Schematic

Truth table

DOOR (SW1) EN (SW2) NAND_OUT (Pin 3) ALARM (Pin 6) LED Status
0 (Low) 0 (Low) 1 (High) 0 (Low) OFF
0 (Low) 1 (High) 1 (High) 0 (Low) OFF
1 (High) 0 (Low) 1 (High) 0 (Low) OFF
1 (High) 1 (High) 0 (Low) 1 (High) ON (Alarm Active)

Measurements and tests

  1. Supply Validation: Measure the voltage between VCC and 0. Ensure it is a stable 5 V.
  2. Input States: Use a multimeter to measure nodes DOOR and EN with respect to ground (0). Verify they read 0 V when the switch is open and 5 V when the switch is closed.
  3. Intermediate Logic: Close both SW1 and SW2. Measure node NAND_OUT. It should drop to 0 V (Logic Low) only when both switches are closed.
  4. Final Output: Measure node ALARM. It should read 5 V (Logic High) only when both switches are closed, confirming that U1B correctly inverted the signal from U1 A.
  5. Load Check: Verify the voltage drop across D1 is roughly 1.8 V to 2.2 V when illuminated.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Open door alarm with inhibition
.width out=256

* Main Power Supply
V1 VCC 0 DC 5

* Door Sensor (SW1) - Modeled as a voltage-controlled switch with a pulse source
V_ctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
S1 VCC DOOR ctrl1 0 mySW
R1 DOOR 0 10k

* System Enable (SW2) - Modeled as a voltage-controlled switch with a slower pulse source
V_ctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)
S2 VCC EN ctrl2 0 mySW
R2 EN 0 10k

* 74HC00 Quad 2-input NAND gate
* Wiring: 1->DOOR, 2->EN, 3->NAND_OUT, 4->NAND_OUT, 5->NAND_OUT, 6->ALARM, 7->0, 14->VCC
XU1 DOOR EN NAND_OUT NAND_OUT NAND_OUT ALARM 0 VCC 74HC00

* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

* Practical case: Open door alarm with inhibition
.width out=256

* Main Power Supply
V1 VCC 0 DC 5

* Door Sensor (SW1) - Modeled as a voltage-controlled switch with a pulse source
V_ctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
S1 VCC DOOR ctrl1 0 mySW
R1 DOOR 0 10k

* System Enable (SW2) - Modeled as a voltage-controlled switch with a slower pulse source
V_ctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)
S2 VCC EN ctrl2 0 mySW
R2 EN 0 10k

* 74HC00 Quad 2-input NAND gate
* Wiring: 1->DOOR, 2->EN, 3->NAND_OUT, 4->NAND_OUT, 5->NAND_OUT, 6->ALARM, 7->0, 14->VCC
XU1 DOOR EN NAND_OUT NAND_OUT NAND_OUT ALARM 0 VCC 74HC00

* Alarm LED indicator
R3 ALARM LED_IN 330
D1 LED_IN 0 DLED

* Models and Subcircuits
.model mySW SW(Ron=1 Roff=100Meg Vt=2.5)
.model DLED D(IS=1e-15 N=2 RS=10)

* 74HC00 Subcircuit implementation (using robust continuous B-sources for logic)
.subckt 74HC00 1 2 3 4 5 6 7 14
* Gate 1 (Pins 1, 2 -> 3)
B1 3 7 V = 5 * (1 - (1 / (1 + exp(-50*(V(1,7)-2.5)))) * (1 / (1 + exp(-50*(V(2,7)-2.5)))))
* Gate 2 (Pins 4, 5 -> 6)
B2 6 7 V = 5 * (1 - (1 / (1 + exp(-50*(V(4,7)-2.5)))) * (1 / (1 + exp(-50*(V(5,7)-2.5)))))
* Dummy loads to prevent floating pins
R1 1 7 100Meg
R2 2 7 100Meg
R3 4 7 100Meg
R4 5 7 100Meg
R5 14 7 100Meg
.ends

* Analysis Directives
.op
.tran 1u 300u
.print tran V(DOOR) V(EN) V(ALARM) V(LED_IN)
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The simulation results show that when both DOOR and EN are high (approx 5V), ALARM goes high (5V) and LED_IN reaches about 1.65V, indicating the LED is ON. When either DOOR or EN is low (approx 0V), ALARM is low (0V) and LED_IN is 0V, indicating the LED is OFF. This perfectly matches the intended truth table for the alarm with inhibition.
Show raw data table (412 rows) 
Index   time            v(door)         v(en)           v(alarm)        v(led_in)
0	0.000000e+00	4.999000e-04	4.999000e-04	-7.41841e-68	4.091162e-30
1	1.000000e-08	4.999000e-04	4.999000e-04	-7.41841e-68	2.688961e-41
2	2.000000e-08	4.999000e-04	4.999000e-04	-7.41841e-68	-2.68896e-41
3	4.000000e-08	4.999000e-04	4.999000e-04	-7.41841e-68	-8.83675e-52
4	8.000000e-08	4.999000e-04	4.999000e-04	-7.41841e-68	3.534698e-52
5	1.600000e-07	4.999000e-04	4.999000e-04	-7.41841e-68	1.858568e-62
6	3.200000e-07	4.999000e-04	4.999000e-04	-7.41841e-68	-4.64651e-63
7	3.562500e-07	4.999000e-04	4.999000e-04	-7.41841e-68	-7.41842e-68
8	4.196875e-07	4.999000e-04	4.999000e-04	-7.41841e-68	-7.41841e-68
9	4.372461e-07	4.999000e-04	4.999000e-04	-7.41841e-68	-7.41841e-68
10	4.679736e-07	4.999000e-04	4.999000e-04	-7.41841e-68	-7.41841e-68
11	5.019934e-07	4.999500e+00	4.999500e+00	5.000000e+00	1.651140e+00
12	5.700330e-07	4.999500e+00	4.999500e+00	5.000000e+00	1.651062e+00
13	7.061121e-07	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
14	9.782703e-07	4.999500e+00	4.999500e+00	5.000000e+00	1.650725e+00
15	1.000000e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
16	1.043459e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
17	1.130378e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
18	1.304216e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
19	1.651892e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
20	2.347244e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
21	3.347244e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
22	4.347244e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
23	5.347244e-06	4.999500e+00	4.999500e+00	5.000000e+00	1.650721e+00
... (388 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Open door alarm with inhibition
.width out=256

* Main Power Supply
V1 VCC 0 DC 5

* Door Sensor (SW1) - Modeled as a voltage-controlled switch with a pulse source
V_ctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
S1 VCC DOOR ctrl1 0 mySW
R1 DOOR 0 10k

* System Enable (SW2) - Modeled as a voltage-controlled switch with a slower pulse source
V_ctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)
S2 VCC EN ctrl2 0 mySW
R2 EN 0 10k

* 74HC00 Quad 2-input NAND gate
* Wiring: 1->DOOR, 2->EN, 3->NAND_OUT, 4->NAND_OUT, 5->NAND_OUT, 6->ALARM, 7->0, 14->VCC
XU1 DOOR EN NAND_OUT NAND_OUT NAND_OUT ALARM 0 VCC 74HC00

* Alarm LED indicator
R3 ALARM LED_IN 330
D1 LED_IN 0 DLED

* Models and Subcircuits
.model mySW SW(Ron=1 Roff=100Meg Vt=2.5)
.model DLED D(IS=1e-15 N=2 RS=10)

* 74HC00 Subcircuit implementation (using robust continuous B-sources for logic)
.subckt 74HC00 1 2 3 4 5 6 7 14
* Gate 1 (Pins 1, 2 -> 3)
B1 3 7 V = 5 * (1 - (1 / (1 + exp(-50*(V(1,7)-2.5)))) * (1 / (1 + exp(-50*(V(2,7)-2.5)))))
* Gate 2 (Pins 4, 5 -> 6)
B2 6 7 V = 5 * (1 - (1 / (1 + exp(-50*(V(4,7)-2.5)))) * (1 / (1 + exp(-50*(V(5,7)-2.5)))))
* Dummy loads to prevent floating pins
R1 1 7 100Meg
R2 2 7 100Meg
R3 4 7 100Meg
R4 5 7 100Meg
R5 14 7 100Meg
.ends

* Analysis Directives
.op
.tran 1u 300u
.print tran V(DOOR) V(EN) V(ALARM) V(LED_IN)
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The simulation results show that when both DOOR and EN are high (approx 5V), ALARM goes high (5V) and LED_IN reaches about 1.65V, indicating the LED is ON. When either DOOR or EN is low (approx 0V), ALARM is low (0V) and LED_IN is 0V, indicating the LED is OFF. This perfectly matches the intended truth table for the alarm with inhibition.

Common mistakes and how to avoid them

  • Floating CMOS inputs: Forgetting the pull-down resistors (R1, R2) will leave the inputs floating when the switches are open, causing unpredictable LED blinking and excessive IC current draw. Always ensure mechanical switches are paired with pull-up or pull-down resistors.
  • Leaving unused gates floating: The 74HC00 contains four gates. Leaving the inputs of gates 3 and 4 disconnected can cause high-frequency oscillations. Tie pins 8, 9, 12, and 13 to ground (0).
  • Misunderstanding NAND logic for NOT: To use a NAND gate as an inverter (NOT gate), you must tie both inputs together (as done on pins 4 and 5). Supplying the signal to only one pin while leaving the other floating will result in faulty logic.


Troubleshooting

  • Symptom: The LED never turns on.
  • Cause: D1 might be inserted backward (reverse polarity), or R3 is too large.
  • Fix: Check that the long leg (anode) of D1 faces ALARM and the flat side (cathode) goes to 0. Verify R3 is 330 Ω, not 330 kΩ.
  • Symptom: The LED turns on as soon as one switch is closed, ignoring the other.
  • Cause: A wiring error on the 74HC00 inputs, or an input pin is shorted to VCC.
  • Fix: Check continuity on pins 1 and 2. Ensure they are isolated from each other and correctly routed to DOOR and EN.
  • Symptom: The circuit is highly sensitive to hand movements nearby.
  • Cause: Floating inputs. The pull-down resistors are either disconnected or not making good contact on the breadboard.
  • Fix: Verify R1 and R2 are securely connected between the switch signal nodes and ground.

Possible improvements and extensions

  • Active Buzzer Integration: Add a 5 V active buzzer in parallel with the LED (and its resistor) so the alarm provides both visual and auditory feedback.
  • Flashing Alarm: Use the two remaining NAND gates in the 74HC00 along with a resistor and capacitor to build an astable multivibrator, making the LED blink repeatedly when the alarm is triggered instead of staying solid.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the main objective of the circuit described in the text?




Question 2: Which specific logic chip is used as the core of this circuit?




Question 3: Under what exact condition does the LED alarm turn ON?




Question 4: What logic function is created by combining multiple NAND gates in this project?




Question 5: How does the circuit handle mechanical switches connected to digital CMOS inputs?




Question 6: What happens if the enable switch is open (Logic 0)?




Question 7: What concept commonly used in industrial electronics does this project illustrate?




Question 8: What logic level represents an open door in this circuit?




Question 9: What will the intermediate logic signal between the two NAND gates show?




Question 10: What voltages can be clearly measured at the switch output nodes?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Emergency stop system

Emergency stop system prototype (Maker Style)

Level: Basic – Use the low-level output of a NAND gate to stop a process if two sensors detect danger simultaneously.

Objective and use case

In this practical case, you will build a digital safety interlock circuit using a 74HC00 NAND gate. The system evaluates two independent danger sensors and triggers an active-low relay to halt a process only when both sensors detect a critical condition.

Why it is useful:
* Industrial safety: Halting heavy machinery if two separate safety guards are simultaneously bypassed or opened.
* Process control: Triggering an emergency shutdown in a chemical plant if both pressure and temperature exceed critical thresholds.
* Redundant validation: Preventing false alarms from shutting down a system by requiring two independent sensors to agree before taking action.

Expected outcome:
* When both sensors read a HIGH logic level (indicating danger), the NAND gate output will drop to a LOW logic level (~0 V).
* The 0 V signal will trigger an active-low relay module, engaging the emergency stop.
* If either or both sensors read a LOW logic level (safe condition), the NAND output remains HIGH (~5 V), keeping the relay inactive and the process running.

Target audience and level: Beginners in digital electronics and industrial logic control.

Materials

  • V1: 5 V DC power supply
  • SW1: SPST switch, function: danger sensor 1
  • SW2: SPST switch, function: danger sensor 2
  • R1: 10 kΩ resistor, function: pull-down for SW1
  • R2: 10 kΩ resistor, function: pull-down for SW2
  • U1: 74HC00 Quad 2-Input NAND gate IC
  • RLY1: 5 V Active-low relay module, function: process emergency stop

Pin-out of the IC used

We will use the 74HC00 (Quad 2-Input NAND gate).

Pin Name Logic function Connection in this case
1 1 A Input 1 of Gate 1 Node VA (from SW1)
2 1B Input 2 of Gate 1 Node VB (from SW2)
3 1Y Output of Gate 1 Node VOUT (to RLY1 IN)
7 GND Ground Node 0
14 VCC Power Supply Node VCC

Wiring guide

  • V1: connects between node VCC and node 0 (GND).
  • SW1: connects between node VCC and node VA.
  • R1: connects between node VA and node 0.
  • SW2: connects between node VCC and node VB.
  • R2: connects between node VB and node 0.
  • U1: Pin 14 connects to node VCC; Pin 7 connects to node 0.
  • U1: Pin 1 connects to node VA.
  • U1: Pin 2 connects to node VB.
  • U1: Pin 3 connects to node VOUT.
  • RLY1: VCC pin connects to node VCC, GND pin connects to node 0, and the signal/IN pin connects to node VOUT.

Conceptual block diagram

Conceptual block diagram — 74HC00 NAND gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

POWER SUPPLY:
[ V1: 5 V DC Power Supply ] --(VCC)
                           --(GND)

SENSOR 1 INPUT PATH:
VCC --> [ SW1: Danger Sensor 1 ] --(Node VA)--> [ U1: 74HC00 NAND (Pin 1) ]
[ Node VA ] --> [ R1: 10 kΩ Pull-down ] --> GND

SENSOR 2 INPUT PATH:
VCC --> [ SW2: Danger Sensor 2 ] --(Node VB)--> [ U1: 74HC00 NAND (Pin 2) ]
[ Node VB ] --> [ R2: 10 kΩ Pull-down ] --> GND

LOGIC TO EMERGENCY STOP PATH:
[ U1: 74HC00 NAND (Pin 3) ] --(Node VOUT)--> [ RLY1: Relay Module (IN) ]

IC & MODULE POWER CONNECTIONS:
VCC --> [ U1: 74HC00 NAND (Pin 14) ]
GND <-- [ U1: 74HC00 NAND (Pin 7) ]

VCC --> [ RLY1: Relay Module (VCC) ]
GND <-- [ RLY1: Relay Module (GND) ]
Electrical Schematic

Truth table

Note: The relay module in this case is active-low, meaning it triggers the emergency stop when it receives a 0.

SW1 (Node VA) SW2 (Node VB) VOUT (NAND Output) Relay State (Active-Low) Process Status
0 (Safe) 0 (Safe) 1 (HIGH) OFF Running
0 (Safe) 1 (Danger) 1 (HIGH) OFF Running
1 (Danger) 0 (Safe) 1 (HIGH) OFF Running
1 (Danger) 1 (Danger) 0 (LOW) ON (Triggered) STOPPED

Measurements and tests

  1. Input Logic States: Using a digital multimeter, measure the DC voltage at nodes VA and VB with respect to node 0. Verify they read ~0 V when the switches are open, and ~5 V when closed.
  2. Output Voltage Level: Measure node VOUT. Confirm it sits near 5 V during normal operation (when one or zero switches are closed).
  3. System Activation: Close both SW1 and SW2 simultaneously. Measure node VOUT to ensure it drops to ~0 V.
  4. Relay Actuation: Listen for the audible «click» of the relay (or observe its onboard indicator LED) precisely when VOUT drops to 0 V, confirming the emergency stop command has been physically executed.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Emergency stop system
.width out=256

* Main 5V DC power supply
V1 VCC 0 DC 5

* SW1 (Danger sensor 1) and its pull-down resistor
S1 VCC VA ctrl1 0 sw_mod
Vctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
R1 VA 0 10k

* SW2 (Danger sensor 2) and its pull-down resistor
S2 VCC VB ctrl2 0 sw_mod
Vctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)
R2 VB 0 10k

* U1: 74HC00 Quad 2-Input NAND gate IC (Using pins 1, 2, 3, 7, 14)
XU1 VA VB VOUT VCC 0 NAND_74HC00

* RLY1: 5V Active-low relay module
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

* Practical case: Emergency stop system
.width out=256

* Main 5V DC power supply
V1 VCC 0 DC 5

* SW1 (Danger sensor 1) and its pull-down resistor
S1 VCC VA ctrl1 0 sw_mod
Vctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
R1 VA 0 10k

* SW2 (Danger sensor 2) and its pull-down resistor
S2 VCC VB ctrl2 0 sw_mod
Vctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)
R2 VB 0 10k

* U1: 74HC00 Quad 2-Input NAND gate IC (Using pins 1, 2, 3, 7, 14)
XU1 VA VB VOUT VCC 0 NAND_74HC00

* RLY1: 5V Active-low relay module
XRLY1 VOUT VCC 0 RELAY_MOD

* --- Subcircuits ---

.subckt NAND_74HC00 INA INB OUT VCC GND
* Behavioral NAND gate using continuous sigmoid functions for robust convergence
B1 OUT_int 0 V = 5 * (1 - (1/(1+exp(-20*(V(INA)-2.5)))) * (1/(1+exp(-20*(V(INB)-2.5)))))
R1 OUT_int OUT 100
C1 OUT 0 10p
.ends

.subckt RELAY_MOD IN VCC GND
* Simple resistive model for the relay module to satisfy load requirements
R_in IN GND 10k
R_vcc VCC GND 1k
.ends

* --- Models ---
.model sw_mod SW(Vt=2.5 Ron=0.1 Roff=100Meg)

* --- Analysis Directives ---
.tran 1u 300u
.print tran V(VA) V(VB)
.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The ngspice transient analysis shows nodes VA and VB toggling between approximately 0V and 5V, consistent with the PULSE sources driving the switches. This correctly simulates the different combinations of the danger sensors (SW1 and SW2) being triggered or safe.
Show raw data table (501 rows) 
Index   time            v(va)           v(vb)
0	0.000000e+00	4.999500e-04	4.999500e-04
1	1.000000e-08	4.999500e-04	4.999500e-04
2	2.000000e-08	4.999500e-04	4.999500e-04
3	4.000000e-08	4.999500e-04	4.999500e-04
4	8.000000e-08	4.999500e-04	4.999500e-04
5	1.600000e-07	4.999500e-04	4.999500e-04
6	3.200000e-07	4.999500e-04	4.999500e-04
7	3.562500e-07	4.999500e-04	4.999500e-04
8	4.196875e-07	4.999500e-04	4.999500e-04
9	4.372461e-07	4.999500e-04	4.999500e-04
10	4.679736e-07	4.999500e-04	4.999500e-04
11	4.795524e-07	4.999500e-04	4.999500e-04
12	4.902290e-07	4.999500e-04	4.999500e-04
13	5.023412e-07	4.999950e+00	4.999950e+00
14	5.111724e-07	4.999950e+00	4.999950e+00
15	5.196372e-07	4.999950e+00	4.999950e+00
16	5.247062e-07	4.999950e+00	4.999950e+00
17	5.271308e-07	4.999950e+00	4.999950e+00
18	5.277087e-07	4.999950e+00	4.999950e+00
19	5.280739e-07	4.999950e+00	4.999950e+00
20	5.285244e-07	4.999950e+00	4.999950e+00
21	5.292184e-07	4.999950e+00	4.999950e+00
22	5.299733e-07	4.999950e+00	4.999950e+00
23	5.306602e-07	4.999950e+00	4.999950e+00
... (477 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Emergency stop system
.width out=256

* Main 5V DC power supply
V1 VCC 0 DC 5

* SW1 (Danger sensor 1) and its pull-down resistor
S1 VCC VA ctrl1 0 sw_mod
Vctrl1 ctrl1 0 PULSE(0 5 0 1u 1u 50u 100u)
R1 VA 0 10k

* SW2 (Danger sensor 2) and its pull-down resistor
S2 VCC VB ctrl2 0 sw_mod
Vctrl2 ctrl2 0 PULSE(0 5 0 1u 1u 100u 200u)
R2 VB 0 10k

* U1: 74HC00 Quad 2-Input NAND gate IC (Using pins 1, 2, 3, 7, 14)
XU1 VA VB VOUT VCC 0 NAND_74HC00

* RLY1: 5V Active-low relay module
XRLY1 VOUT VCC 0 RELAY_MOD

* --- Subcircuits ---

.subckt NAND_74HC00 INA INB OUT VCC GND
* Behavioral NAND gate using continuous sigmoid functions for robust convergence
B1 OUT_int 0 V = 5 * (1 - (1/(1+exp(-20*(V(INA)-2.5)))) * (1/(1+exp(-20*(V(INB)-2.5)))))
R1 OUT_int OUT 100
C1 OUT 0 10p
.ends

.subckt RELAY_MOD IN VCC GND
* Simple resistive model for the relay module to satisfy load requirements
R_in IN GND 10k
R_vcc VCC GND 1k
.ends

* --- Models ---
.model sw_mod SW(Vt=2.5 Ron=0.1 Roff=100Meg)

* --- Analysis Directives ---
.tran 1u 300u
.print tran V(VA) V(VB)
.op
.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The ngspice transient analysis shows nodes VA and VB toggling between approximately 0V and 5V, consistent with the PULSE sources driving the switches. This correctly simulates the different combinations of the danger sensors (SW1 and SW2) being triggered or safe.

Common mistakes and how to avoid them

  • Floating inputs: Forgetting the pull-down resistors (R1 and R2). Without them, the logic gate inputs will float and pick up ambient noise, causing the relay to trigger randomly.
  • Misunderstanding active-low logic: Expecting the relay to trigger when the output is 5 V. In this case, the NAND output drops to 0 V upon detecting mutual danger, which perfectly matches an active-low relay module. Ensure your relay module is truly active-low.
  • Omitting IC power connections: Forgetting to wire pins 14 (VCC) and 7 (GND) of the 74HC00. The IC will not process logic without power, and may behave erratically if powered parasitically through its input pins.


Troubleshooting

  • Symptom: The relay never clicks, even when both switches are closed.
    • Cause: The 74HC00 output pin cannot sink enough current, or the relay module is active-high instead of active-low.
    • Fix: Ensure you are using a relay module (with a built-in driver transistor) rather than a bare mechanical relay. Verify the module’s trigger logic (some have a jumper to select active-high vs. active-low).
  • Symptom: The relay chatters rapidly or triggers randomly without human interaction.
    • Cause: Floating inputs at node VA or VB.
    • Fix: Double-check that R1 and R2 are properly seated in the breadboard and connected directly to GND (node 0).
  • Symptom: The relay is always ON, and the process is permanently stopped.
    • Cause: The NAND output is permanently stuck at 0 V. This can happen if both inputs are shorted to VCC, or if the logic gate is damaged.
    • Fix: Measure VA and VB. If they are reading 0 V but VOUT is still 0 V, replace the 74HC00 IC.

Possible improvements and extensions

  • Hardware debouncing: Add a 1 µF capacitor across each switch to prevent contact bounce from generating rapid, unintended logic transitions during the millisecond the switch is toggled.
  • Visual status indicators: Connect an LED and a 330 Ω current-limiting resistor to node VOUT to provide a clear visual indicator on a control panel when the system is in a safe state (LED ON) versus an emergency state (LED OFF).

More Practical Cases on Prometeo.blog

Find this product and/or books on this topic on Amazon

Go to Amazon

As an Amazon Associate, I earn from qualifying purchases. If you buy through this link, you help keep this project running.

Quick Quiz

Question 1: What is the main objective of the circuit described in the article?




Question 2: Which specific IC is used in this project?




Question 3: When will the active-low relay be triggered to halt the process?




Question 4: What logic level from the sensors indicates a 'danger' condition?




Question 5: What is the output of the NAND gate when both sensors read a HIGH logic level?




Question 6: What happens to the process if either or both sensors read a LOW logic level (safe condition)?




Question 7: Why is redundant validation useful in this circuit?




Question 8: What is an example of industrial safety mentioned in the text?




Question 9: What type of relay module is used for the process emergency stop?




Question 10: What is the difficulty level of this practical case?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Practical case: Logic inverter using NAND gate

Logic inverter using NAND gate prototype (Maker Style)

Level: Basic – Demonstrate the universality of the NAND gate by configuring it as a basic NOT gate.

Objective and use case

In this practical case, you will build a digital inverter (NOT gate) using a standard 74HC00 NAND gate by shorting its inputs together.

Understanding this configuration is highly useful for several reasons:
* BOM Optimization: It reduces the number of unique integrated circuits needed in a design; if you have spare NAND gates on a board, you do not need to add a dedicated NOT gate chip.
* Logic Universality: It practically proves that NAND gates are «universal,» meaning any logic function can be constructed using only NAND gates.
* Circuit Simplification: It helps streamline routing on printed circuit boards by repurposing nearby unused gates instead of running traces to a different IC.

Expected outcome:
* When the input switch provides a logic LOW (0 V) to the shorted inputs, the output will go HIGH (approx. 5 V), turning on the indicator LED.
* When the input switch provides a logic HIGH (5 V) to the shorted inputs, the output will go LOW (0 V), turning off the indicator LED.
* The circuit will perfectly replicate the behavior of a standard 74HC04 NOT gate.

Target audience: Electronics beginners learning fundamental Boolean algebra and digital hardware implementation.

Materials

  • V1: 5 V DC supply
  • U1: 74HC00 Quad 2-Input NAND Gate
  • SW1: SPST toggle switch or push button, function: input state selector
  • R1: 10 kΩ resistor, function: pull-down for node VA
  • R2: 330 Ω resistor, function: current limiting for the output LED
  • D1: Red LED, function: VOUT state indicator

Pin-out of the IC used

IC: 74HC00 (Quad 2-Input NAND gate)

Pin Name Logic function Connection in this case
1 1 A Input A of Gate 1 Node VA (shorted to 1B)
2 1B Input B of Gate 1 Node VA (shorted to 1 A)
3 1Y Output of Gate 1 Node VOUT
7 GND Ground Node 0
14 VCC Positive Power Supply Node VCC

(Note: Pins 4, 5, 9, 10, 12, 13 are unused inputs in this specific exercise and should ideally be tied to Ground in a final physical circuit to prevent CMOS floating input issues).

Wiring guide

  • V1: Connects between node VCC (+5 V) and node 0 (GND).
  • U1 VCC/GND: Connect pin 14 to node VCC and pin 7 to node 0.
  • SW1: Connects between node VCC and node VA.
  • R1: Connects between node VA and node 0 (ensures a definitive LOW when the switch is open).
  • U1 Inputs: Connect pin 1 (1 A) to node VA and connect pin 2 (1B) to node VA. This ties both inputs of the first NAND gate together.
  • U1 Output: Pin 3 (1Y) provides the inverted signal and connects to node VOUT.
  • R2: Connects between node VOUT and the anode of D1.
  • D1: Connects the cathode to node 0.

Conceptual block diagram

Conceptual block diagram — 74HC00 NAND gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

VCC --> [ SW1: Switch ] --(Node VA)--> [ U1: 74HC00 NAND (Pins 1 & 2) ] --(VOUT)--> [ R2: 330 Ω ] --> [ D1: Red LED ] --> GND
                               |
                          [ R1: 10 kΩ ]
                               |
                              GND
Electrical Schematic

Truth table

Input (VA) Output (VOUT) LED State (D1)
0 (LOW) 1 (HIGH) ON
1 (HIGH) 0 (LOW) OFF

Measurements and tests

  1. Input Voltage Measurement: Use a multimeter to measure the voltage at node VA with respect to node 0. Verify that it reads ~0 V when SW1 is open, and ~5 V when SW1 is closed.
  2. Output Voltage Measurement: Move the multimeter probe to node VOUT. Confirm that it reads ~5 V when VA is 0 V, and reads ~0 V when VA is 5 V.
  3. Functional Verification: Toggle the switch multiple times. Ensure D1 behaves inversely to the physical action of the switch (e.g., if pressing the button sends a HIGH signal, the LED should turn off when pressed).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Logic inverter using NAND gate

* Power Supply
V1 VCC 0 DC 5V

* Switch SW1 (VCC to VA)
* Modeled as a voltage-controlled switch to simulate user interaction
S_SW1 VCC VA SW_CTRL 0 sw_mod
.model sw_mod SW(vt=2.5 vh=0.2 ron=0.1 roff=100Meg)
V_SW_CTRL SW_CTRL 0 PULSE(0 5 10u 1u 1u 100u 200u)

* Pull-down resistor R1
R1 VA 0 10k

* U1: 74HC00 Quad 2-Input NAND Gate (using 1 gate)
* Pin 14: VCC, Pin 7: 0
* Pin 1: VA, Pin 2: VA, Pin 3: VOUT
XU1 VA VA VOUT VCC 0 NAND2_74HC00

* R2: Current limiting resistor
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

* Practical case: Logic inverter using NAND gate

* Power Supply
V1 VCC 0 DC 5V

* Switch SW1 (VCC to VA)
* Modeled as a voltage-controlled switch to simulate user interaction
S_SW1 VCC VA SW_CTRL 0 sw_mod
.model sw_mod SW(vt=2.5 vh=0.2 ron=0.1 roff=100Meg)
V_SW_CTRL SW_CTRL 0 PULSE(0 5 10u 1u 1u 100u 200u)

* Pull-down resistor R1
R1 VA 0 10k

* U1: 74HC00 Quad 2-Input NAND Gate (using 1 gate)
* Pin 14: VCC, Pin 7: 0
* Pin 1: VA, Pin 2: VA, Pin 3: VOUT
XU1 VA VA VOUT VCC 0 NAND2_74HC00

* R2: Current limiting resistor
R2 VOUT N1 330

* D1: Red LED
D1 N1 0 DLED

* Models
.model DLED D(IS=1e-15 N=1.8 RS=10)

* Subcircuit for NAND Gate
.subckt NAND2_74HC00 1A 1B 1Y VCC GND
RinA 1A GND 1G
RinB 1B GND 1G
Rvcc VCC GND 100Meg
B1 Y_int GND V = 5 * (1 - (1/(1+exp(-50*(V(1A)-2.5)))) * (1/(1+exp(-50*(V(1B)-2.5)))))
Rout Y_int 1Y 50
.ends

* Analysis
.tran 1u 600u
.print tran V(VA) V(VOUT) V(N1) I(V1)
.op

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The transient simulation shows that when the input VA is LOW (~0V), the output VOUT is HIGH (~4.54V) and the LED node N1 is at ~1.48V (LED ON). When VA goes HIGH (~5V), VOUT goes LOW (~0V) and N1 goes to ~0V (LED OFF). This perfectly matches the expected logic inverter behavior.
Show raw data table (704 rows) 
Index   time            v(va)           v(vout)         v(n1)           v1#branch
0	0.000000e+00	4.999400e-04	4.537182e+00	1.482582e+00	-9.99950e-08
1	1.000000e-08	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
2	2.000000e-08	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
3	4.000000e-08	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
4	8.000000e-08	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
5	1.600000e-07	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
6	3.200000e-07	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
7	6.400000e-07	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
8	1.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
9	2.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
10	3.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
11	4.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
12	5.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
13	6.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
14	7.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
15	8.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
16	9.280000e-06	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
17	1.000000e-05	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
18	1.010000e-05	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
19	1.030000e-05	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
20	1.034750e-05	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
21	1.043062e-05	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
22	1.045363e-05	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
23	1.049390e-05	4.999400e-04	4.537182e+00	1.482580e+00	-9.99950e-08
... (680 more rows) ...


Reference SPICE netlist (ngspice)

* Practical case: Logic inverter using NAND gate

* Power Supply
V1 VCC 0 DC 5V

* Switch SW1 (VCC to VA)
* Modeled as a voltage-controlled switch to simulate user interaction
S_SW1 VCC VA SW_CTRL 0 sw_mod
.model sw_mod SW(vt=2.5 vh=0.2 ron=0.1 roff=100Meg)
V_SW_CTRL SW_CTRL 0 PULSE(0 5 10u 1u 1u 100u 200u)

* Pull-down resistor R1
R1 VA 0 10k

* U1: 74HC00 Quad 2-Input NAND Gate (using 1 gate)
* Pin 14: VCC, Pin 7: 0
* Pin 1: VA, Pin 2: VA, Pin 3: VOUT
XU1 VA VA VOUT VCC 0 NAND2_74HC00

* R2: Current limiting resistor
R2 VOUT N1 330

* D1: Red LED
D1 N1 0 DLED

* Models
.model DLED D(IS=1e-15 N=1.8 RS=10)

* Subcircuit for NAND Gate
.subckt NAND2_74HC00 1A 1B 1Y VCC GND
RinA 1A GND 1G
RinB 1B GND 1G
Rvcc VCC GND 100Meg
B1 Y_int GND V = 5 * (1 - (1/(1+exp(-50*(V(1A)-2.5)))) * (1/(1+exp(-50*(V(1B)-2.5)))))
Rout Y_int 1Y 50
.ends

* Analysis
.tran 1u 600u
.print tran V(VA) V(VOUT) V(N1) I(V1)
.op

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)
Analysis: The transient simulation shows that when the input VA is LOW (~0V), the output VOUT is HIGH (~4.54V) and the LED node N1 is at ~1.48V (LED ON). When VA goes HIGH (~5V), VOUT goes LOW (~0V) and N1 goes to ~0V (LED OFF). This perfectly matches the expected logic inverter behavior.

Common mistakes and how to avoid them

  • Leaving CMOS inputs floating: The 74HC00 is a CMOS IC. If you fail to use the pull-down resistor R1, opening SW1 will leave inputs 1 A and 1B floating, leading to erratic output switching and high power consumption. Always use a pull-up or pull-down resistor.
  • Forgetting the LED current limiting resistor: Connecting D1 directly between VOUT and 0 without R2 will draw excessive current, potentially destroying both the LED and the output stage of the 74HC00 IC.
  • Incorrectly shorting inputs: Mistakenly shorting an input to an output (e.g., bridging pins 2 and 3 instead of 1 and 2) will create a feedback loop or logic contention, preventing the circuit from functioning.


Troubleshooting

  • Symptom: The LED never turns on.
    • Cause: The LED (D1) might be inserted backwards, or the IC is unpowered.
    • Fix: Check the polarity of the LED (anode to R2, cathode to 0). Measure the voltage between pins 14 and 7 to confirm the IC is receiving 5 V.
  • Symptom: The LED is always on, regardless of the switch position.
    • Cause: The switch is miswired, or the pull-up/pull-down configuration is incorrect (e.g., node VA is stuck LOW).
    • Fix: Verify that SW1 applies 5 V to node VA when activated. Check R1 for a solid connection to Ground.
  • Symptom: The IC becomes extremely hot.
    • Cause: Power supply is reversed or there is a dead short at the output.
    • Fix: Immediately disconnect power. Verify that pin 14 goes to VCC and pin 7 goes to 0. Ensure R2 is present in the output path.

Possible improvements and extensions

  • Add an Input Indicator: Connect a second LED and resistor directly to node VA. This allows you to visually compare the input state and output state side-by-side (when one LED is ON, the other will be OFF).
  • Build an AND Gate: Cascade this newly built inverter into a second NAND gate. Connect the output of a standard NAND gate to the shorted inputs of your NAND-based NOT gate to create a functional AND gate, further demonstrating universal logic.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the main objective of the practical case described in the article?




Question 2: Which specific integrated circuit is mentioned for building the digital inverter?




Question 3: How is the NAND gate configured to act as a NOT gate?




Question 4: What does the term 'Logic Universality' mean in the context of NAND gates?




Question 5: How does using a NAND gate as a NOT gate help with BOM (Bill of Materials) optimization?




Question 6: What is the expected output when the input switch provides a logic LOW (0 V) to the shorted inputs?




Question 7: What happens to the indicator LED when a logic HIGH (5 V) is provided to the inputs?




Question 8: How does repurposing unused NAND gates benefit printed circuit board (PCB) design?




Question 9: What logic level corresponds to approximately 5 V in this practical case?




Question 10: What behavior does the configured 74HC00 circuit perfectly replicate?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Dual Safety Motor Activation

Dual Safety Motor Activation prototype (Maker Style)

Level: Basic — Implement a system where a motor runs only when two buttons are pressed simultaneously.

Objective and use case

In this session, you will build a safety logic circuit using a 74HC00 (Quad 2-input NAND gate) to control a DC motor. The motor will only activate when two separate pushbuttons are engaged at the same time, mimicking a «two-hand control» safety device.

Why it is useful:
* Industrial Safety: Prevents operators from reaching into a hydraulic press or cutting machine while it is moving.
* Accident Prevention: Ensures both hands are occupied on the controls during the dangerous phase of operation.
* Logic Composition: Demonstrates how to create an AND function using universal NAND gates.

Expected outcome:
* Idle State: Logic output is LOW (0 V); Motor is OFF.
* Single Press: Logic output remains LOW (0 V); Motor remains OFF.
* Dual Press: Logic output becomes HIGH (5 V); Relay engages; Motor runs.
* Current Handling: The logic gate drives a transistor, which safely switches the high-current relay coil.

Target audience and level:
Basic electronics students and hobbyists interested in digital logic applications.

Materials

  • V1: 5 V DC voltage source, function: Logic and relay coil power supply.
  • V2: 12 V DC voltage source, function: Motor power supply.
  • U1: 74HC00, function: Quad 2-input NAND gate IC.
  • S1: Pushbutton (normally open), function: Left-hand safety switch.
  • S2: Pushbutton (normally open), function: Right-hand safety switch.
  • R1: 10 kΩ resistor, function: Pull-down for S1.
  • R2: 10 kΩ resistor, function: Pull-down for S2.
  • R3: 1 kΩ resistor, function: Base current limiting for Q1.
  • Q1: 2N2222 NPN transistor, function: Relay driver.
  • D1: 1N4007 diode, function: Flyback protection for relay coil.
  • K1: 5 V SPDT Relay, function: High-power switching interface.
  • M1: 12 V DC Motor, function: Actuator (load).

Pin-out of the IC used (74HC00)

Chip: 74HC00 (Quad 2-Input NAND Gate)

Pin Name Logic Function Connection in this case
1 1 A Input A (Gate 1) Connected to S1 (Node BTN_L)
2 1B Input B (Gate 1) Connected to S2 (Node BTN_R)
3 1Y Output (Gate 1) Connected to Inputs of Gate 2 (Node NAND_INTER)
4 2 A Input A (Gate 2) Connected to Node NAND_INTER
5 2B Input B (Gate 2) Connected to Node NAND_INTER
6 2Y Output (Gate 2) Connected to R3 (Node LOGIC_OUT)
7 GND Ground Connected to Node 0
14 VCC Power Supply Connected to Node VCC

Note: Pins 8 through 13 are unused and should ideally be tied to GND or VCC in a permanent installation to prevent noise, though left floating for this basic breadboard exercise.

Wiring guide

Construct the circuit following these node connections. Ensure the power supply is off while building.

Power and Inputs:
* V1 (+): Connects to node VCC.
* V1 (-) / V2 (-): Connects to node 0 (Common Ground).
* S1: Connects between VCC and node BTN_L.
* R1: Connects between node BTN_L and 0.
* S2: Connects between VCC and node BTN_R.
* R2: Connects between node BTN_R and 0.

Logic Processing (Using U1 as AND Gate):
* U1 (Pin 14): Connects to VCC.
* U1 (Pin 7): Connects to 0.
* U1 (Pin 1): Connects to node BTN_L.
* U1 (Pin 2): Connects to node BTN_R.
* U1 (Pin 3): Connects to node NAND_INTER (First stage output).
* U1 (Pin 4 & Pin 5): Both connect to node NAND_INTER (Configures Gate 2 as an inverter).
* U1 (Pin 6): Connects to node LOGIC_OUT.

Output Stage:
* R3: Connects between node LOGIC_OUT and node BASE.
* Q1 (Base): Connects to node BASE.
* Q1 (Emitter): Connects to node 0.
* Q1 (Collector): Connects to node RELAY_COIL_LO.
* K1 (Coil +): Connects to VCC.
* K1 (Coil -): Connects to node RELAY_COIL_LO.
* D1 (Anode): Connects to node RELAY_COIL_LO.
* D1 (Cathode): Connects to VCC (Parallel to coil, reverse biased).

Motor Circuit:
* V2 (+): Connects to K1 Common contact (COM).
* K1 (NO – Normally Open): Connects to node MOTOR_POS.
* M1 (+): Connects to node MOTOR_POS.
* M1 (-): Connects to node 0.

Conceptual block diagram

Conceptual block diagram — 74HC00 NAND gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

+-----------------------------------------------------------------------------+
|                  DUAL SAFETY MOTOR ACTIVATION BLOCK DIAGRAM                 |
+-----------------------------------------------------------------------------+

1. INPUTS & LOGIC STAGE (5 V Domain)
   (Both buttons must be pressed to activate the output)

   V1(5 V)
     |
     +---> [ S1: Left Button ] ---+--(BTN_L)------\
                                  |                \
                                  v                 \
                               [ R1: 10k ]           +---> [ U1:A (NAND) ] --(NAND_INTER)--> [ U1:B (NOT*) ] --(LOGIC_OUT)-->
                                  |                 /       (Pins 1 & 2)                      (Pins 4 & 5)          |
                                 GND               /                                         *Wired as Inverter     |
                                                  /                                                                 |
   V1(5 V)                                        /                                                                  |
     |                                          /                                                                   |
     +---> [ S2: Right Button ] --+--(BTN_R)---/                                                                    |
                                  |                                                                                 |
                                  v                                                                                 |
                               [ R2: 10k ]                                                                          |
                                  |                                                                                 |
                                 GND                                                                                |
                                                                                                                    |
+-------------------------------------------------------------------------------------------------------------------+
|                                                                                                                   |
| 2. RELAY DRIVER STAGE (5 V Domain)                                                                                 |
|    (Low-Side Transistor Switch)                                                                                   |
|                                                                                                                   |
|    (From Logic Above)                                                                                             |
|            |                                         V1(5 V)                                                       |
|            v                                           |                                                          |
|      [ R3: 1k ]                                        |                                                          |
|            |                                           v                                                          |
|            +----------------------------------> [ Q1: Base ]                                                      |
|                                                        :                                                          |
|                                             (Controls Current Flow)                                               |
|                                                        :                                                          |
|                                      +-----------------+                                                          |
|                                      |                                                                            |
|                              [ Q1: Collector ]                                                                    |
|                                      ^                                                                            |
|                                      |                                                                            |
|                             (Node: RELAY_COIL_LO)                                                                 |
|                                      |                                                                            |
|                    +-----------------+-----------------+                                                          |
|                    |                                   |                                                          |
|           [ K1: Relay Coil ]                    [ D1: Diode ]                                                     |
|           (Control Side)                        (Protection)                                                      |
|                    |                            (Anode to Coll)                                                   |
|                    |                            (Cathode to VCC)                                                  |
|                    +-----------------+-----------------+                                                          |
|                                      ^                                                                            |
|                                      |                                                                            |
|                                    V1(5 V)                                                                         |
|                                                                                                                   |
|                              [ Q1: Emitter ]                                                                      |
|                                      |                                                                            |
|                                      v                                                                            |
|                                     GND                                                                           |
|                                                                                                                   |
+-------------------------------------------------------------------------------------------------------------------+
|                                                                                                                   |
| 3. MOTOR OUTPUT STAGE (12 V Domain)                                                                                |
|    (High Power Load)                                                                                              |
|                                                                                                                   |
|                       (Magnetic Link from K1 Coil Above)                                                          |
|                                      |                                                                            |
|                                      v                                                                            |
|    V2(12 V) ---------> [ K1: Switch (COM to NO) ] --(MOTOR_POS)--> [ M1: 12 V Motor ] ----> GND                     |
|                                                                                                                   |
+-------------------------------------------------------------------------------------------------------------------+
Electrical Schematic

Electrical diagram

Electrical diagram for case: Dual Safety Motor Activation
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the monthly membership (7-day free trial) you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Truth table

We are using two NAND gates. The first combines the inputs; the second inverts the result to create an AND function.

S1 (Left) S2 (Right) U1 Pin 3 (1Y) U1 Pin 6 (2Y) Motor State
0 (OFF) 0 (OFF) 1 (High) 0 (Low) STOP
0 (OFF) 1 (ON) 1 (High) 0 (Low) STOP
1 (ON) 0 (OFF) 1 (High) 0 (Low) STOP
1 (ON) 1 (ON) 0 (Low) 1 (High) RUN

Measurements and tests

  1. Idle Check: Power on V1. Do not press any buttons. Measure the voltage at LOGIC_OUT (Pin 6). It should be ~0 V. The motor should be stopped.
  2. Input Validation: Press S1 only. Measure voltage at Pin 1. It should be 5 V. Pin 2 should be 0 V. Output at Pin 6 must remain 0 V.
  3. Active Test: Press and hold both S1 and S2 simultaneously.
    • Listen for the «click» of the relay K1.
    • Observe M1 spinning.
    • Measure the voltage at LOGIC_OUT; it should be close to 5 V.
  4. Release Test: Release just one button. The motor must stop immediately.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Logic AND gate controlling a relay and motor

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================
* Generic NPN Transistor Model (2N2222)
.model 2N2222MOD NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)

* Generic Diode Model (1N4007)
.model D1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3 BV=1000 IBV=10m CJO=10p VJ=0.7 M=0.5 FC=0.5 TT=100n)

* Ideal Switch Model for Buttons and Relay Contact
* Vt=2.5V (Logic Threshold), Ron=0.1 Ohm, Roff=10 MegOhm
.model SW_IDEAL SW(Vt=2.5 Vh=0.1 Ron=0.1 Roff=10Meg)

* ==============================================================================
* POWER SUPPLIES
* ==============================================================================
* V1: 5V DC Supply for Logic and Relay Coil
V1 VCC 0 DC 5
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the monthly membership (7-day free trial) you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

🔓 See premium access plans 

* Practical case: Logic AND gate controlling a relay and motor

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================
* Generic NPN Transistor Model (2N2222)
.model 2N2222MOD NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)

* Generic Diode Model (1N4007)
.model D1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3 BV=1000 IBV=10m CJO=10p VJ=0.7 M=0.5 FC=0.5 TT=100n)

* Ideal Switch Model for Buttons and Relay Contact
* Vt=2.5V (Logic Threshold), Ron=0.1 Ohm, Roff=10 MegOhm
.model SW_IDEAL SW(Vt=2.5 Vh=0.1 Ron=0.1 Roff=10Meg)

* ==============================================================================
* POWER SUPPLIES
* ==============================================================================
* V1: 5V DC Supply for Logic and Relay Coil
V1 VCC 0 DC 5

* V2: 12V DC Supply for Motor
V2 V_MOTOR_RAIL 0 DC 12

* ==============================================================================
* INPUT STAGE (Safety Switches)
* ==============================================================================
* Simulation of User Pressing Buttons:
* We use Pulse sources (V_ACT_...) to control ideal switches (S1, S2).
* This preserves the Pull-down resistor topology.

* S1: Left Safety Switch (Pushbutton NO)
* Connects VCC to BTN_L when pressed.
* Pulse Pattern: Period 120us, Pulse 50us (Tests asynchronous press)
V_ACT_L ACT_L 0 PULSE(0 5 10u 1u 1u 50u 120u)
S1 VCC BTN_L ACT_L 0 SW_IDEAL
R1 BTN_L 0 10k

* S2: Right Safety Switch (Pushbutton NO)
* Connects VCC to BTN_R when pressed.
* Pulse Pattern: Period 100us, Pulse 50us
V_ACT_R ACT_R 0 PULSE(0 5 20u 1u 1u 50u 100u)
S2 VCC BTN_R ACT_R 0 SW_IDEAL
R2 BTN_R 0 10k

* ==============================================================================
* LOGIC STAGE (U1: 74HC00 Quad NAND)
* ==============================================================================
* Implementing logic using Behavioral Voltage Sources (B-Sources) with continuous
* sigmoid functions for convergence robustness.
* Logic High = 5V, Logic Low = 0V. Threshold ~ 2.5V.

* U1 Gate 1: Inputs BTN_L (Pin 1), BTN_R (Pin 2) -> Output NAND_INTER (Pin 3)
* Function: NAND(BTN_L, BTN_R)
B_U1_G1 NAND_INTER 0 V=5 * (1 - ( (1/(1+exp(-20*(V(BTN_L)-2.5)))) * (1/(1+exp(-20*(V(BTN_R)-2.5)))) ))

* U1 Gate 2: Inputs NAND_INTER (Pin 4, 5) -> Output LOGIC_OUT (Pin 6)
* Function: NAND(NAND_INTER, NAND_INTER) = NOT(NAND_INTER)
* Combined Function: AND(BTN_L, BTN_R)
B_U1_G2 LOGIC_OUT 0 V=5 * (1 - ( (1/(1+exp(-20*(V(NAND_INTER)-2.5)))) * (1/(1+exp(-20*(V(NAND_INTER)-2.5)))) ))

* ==============================================================================
* OUTPUT DRIVER STAGE
* ==============================================================================
* R3: Base current limiting
R3 LOGIC_OUT BASE 1k

* Q1: 2N2222 Relay Driver
* Emitter to GND, Collector to RELAY_COIL_LO
Q1 RELAY_COIL_LO BASE 0 2N2222MOD

* ==============================================================================
* RELAY STAGE (K1)
* ==============================================================================
* Relay Coil Configuration:
* Connected between VCC and RELAY_COIL_LO.
* Modeled as Inductor + Series Resistor.
L_K1 VCC K1_NODE 10m
R_K1 K1_NODE RELAY_COIL_LO 100

* D1: Flyback Diode (1N4007)
* Anode to RELAY_COIL_LO, Cathode to VCC (Reverse biased)
D1 RELAY_COIL_LO VCC D1N4007

* Relay Contact (Switch):
* Logic: Switch closes when Coil is energized.
* Coil is energized when Q1 is ON (RELAY_COIL_LO is Low).
* Control Voltage = V(VCC) - V(RELAY_COIL_LO).
* If Q1 ON: 5V - 0.2V = 4.8V (> 2.5V Threshold) -> Switch CLOSED.
* If Q1 OFF: 5V - 5V = 0V (< 2.5V Threshold) -> Switch OPEN.
B_K1_CTRL K1_CTRL 0 V = V(VCC) - V(RELAY_COIL_LO)
S_K1 V_MOTOR_RAIL MOTOR_POS K1_CTRL 0 SW_IDEAL

* ==============================================================================
* LOAD (Motor M1)
* ==============================================================================
* M1: 12V DC Motor connected between MOTOR_POS and 0
* Modeled as Resistor + Inductor
R_M1 MOTOR_POS M1_INT 20
L_M1 M1_INT 0 5m

* ==============================================================================
* ANALYSIS COMMANDS
* ==============================================================================
.op
* Transient analysis: 1us step, 500us total time
.tran 1u 500u

* Print results for batch processing
* Inputs: BTN_L, BTN_R
* Output: MOTOR_POS (Load Voltage)
* Debug: LOGIC_OUT, RELAY_COIL_LO
.print tran V(BTN_L) V(BTN_R) V(MOTOR_POS) V(LOGIC_OUT) V(RELAY_COIL_LO) I(L_M1)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation confirms the AND logic behavior. The motor voltage (v(motor_pos)) only goes high (~12V) when both inputs (v(btn_l) and v(btn_r)) are high (~5V) simultaneously (e.g., around time index 60-100 and 300-340). When only one or neither is high, the motor voltage remains near zero.
Show raw data table (1202 rows) 
Index   time            v(btn_l)        v(btn_r)        v(motor_pos)    v(logic_out)    v(relay_coil_lo l_m1#branch
0	0.000000e+00	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
1	1.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
2	2.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
3	4.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
4	8.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
5	1.600000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
6	3.200000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
7	6.400000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
8	1.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
9	2.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
10	3.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
11	4.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
12	5.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
13	6.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
14	7.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
15	8.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
16	9.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
17	1.000000e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
18	1.010000e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
19	1.027500e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
20	1.032344e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
21	1.040820e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
22	1.043167e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
23	1.047272e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
... (1178 more rows) ...

Common mistakes and how to avoid them

  1. Floating Inputs: Forgetting R1 or R2 causes the NAND gate inputs to float, often reading as «High» due to noise. Solution: Ensure pull-down resistors are firmly connected to Ground.
  2. Missing Flyback Diode: Omitting D1 creates voltage spikes when the relay turns off, which can destroy Q1 or reset the logic chip. Solution: Always place a diode across the relay coil (Cathode to positive).
  3. Direct Drive: Attempting to drive the motor or relay directly from the 74HC00 output pin. Solution: Always use a transistor (Q1) to amplify the current for inductive loads like relays.

Troubleshooting

  • Motor runs immediately upon power-up: Check if S1 or S2 are wired as Normally Closed instead of Normally Open, or if the transistor Q1 is shorted.
  • Relay clicks but motor doesn’t run: Check the V2 power supply and the connections on the relay contacts (COM and NO).
  • Logic works but gets hot: Check if VCC (Pin 14) and GND (Pin 7) are reversed. Disconnect power immediately.
  • Erratic behavior: Add a 100 nF decoupling capacitor between Pin 14 and Pin 7 of the IC, close to the chip.

Possible improvements and extensions

  1. Emergency Stop: Add a Normally Closed (NC) latching button in series with the relay coil or the base resistor R3 to cut power instantly regardless of logic state.
  2. Visual Feedback: Add a green LED (with a 330 Ω resistor) connected to node LOGIC_OUT to indicate when the safety condition is met, even if the motor power (V2) is off.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the circuit described in the article?




Question 2: Which integrated circuit (IC) is used to implement the logic for this project?




Question 3: What is a common real-world application for this type of 'two-hand control' system?




Question 4: What logic function is effectively created using the universal NAND gates in this project?




Question 5: What is the state of the motor if only one button is pressed?




Question 6: Which component is mentioned as responsible for driving the high-current relay coil?




Question 7: What is the expected logic output voltage during a 'Dual Press' state?




Question 8: Why is this circuit considered an accident prevention measure?




Question 9: What is the status of the logic output when the system is in an 'Idle State'?




Question 10: Who is the target audience for this project?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Practical case: Veto Voting System

Veto Voting System prototype (Maker Style)

Level: Basic
Implement a logic circuit where a proposal passes only if two members vote «Yes» and a third member grants approval (no veto), using a single 74HC00 IC.

Objective and use case

In this practical case, you will build a decision-making circuit using digital logic. The system represents a committee where Member A and Member B must both vote in favor for a motion to pass, but Member C (the Chairperson) holds an «Authorization Key.» If Member C does not activate their switch (Logic Low), the vote is vetoed regardless of A and B.

  • Corporate Governance: Models a board where majority support is needed but the CEO has final approval.
  • Safety Interlocks: Represents a machine press where two operators must press buttons (A and B), but a Master Enable key (C) must be inserted for the machine to run.
  • Security Access: Requires two distinct user keys plus a central server authorization signal.

Expected Outcome:
* Output High (LED ON): Only when Input A is High, Input B is High, AND Input C is High.
* Output Low (LED OFF): Any other combination (e.g., if A or B vote «No», or if C exerts veto by setting their input Low).
* Target Audience: Students and hobbyists learning to construct complex logic functions (3-input AND) using universal NAND gates.

Materials

  • U1: 74HC00 (Quad 2-Input NAND Gate)
  • SW1: 3-position DIP Switch (or three individual SPST switches), function: Inputs A, B, and C
  • R1: 10 kΩ resistor, function: pull-down for Input A
  • R2: 10 kΩ resistor, function: pull-down for Input B
  • R3: 10 kΩ resistor, function: pull-down for Input C
  • R4: 330 Ω resistor, function: LED current limiting
  • D1: Red LED, function: Logic Output Indicator
  • V1: 5 V DC Power Supply

Pin-out of the IC used

Chip: 74HC00 (Quad 2-input NAND)
This project utilizes all four gates inside the chip to create a 3-input AND function (Y = A · B · C).

Pin Name Logic Function Connection in this case
1 1 A Input Connect to Switch A
2 1B Input Connect to Switch B
3 1Y Output Output of Gate 1 (\overlineA · B)
4 2 A Input Connect to Pin 3 (1Y)
5 2B Input Connect to Pin 3 (1Y)
6 2Y Output Output of Gate 2 (Inverted 1Y \to A · B)
7 GND Ground Connect to Power Supply 0 V
8 3Y Output Output of Gate 3 (\overline(A · B) · C)
9 3 A Input Connect to Switch C
10 3B Input Connect to Pin 6 (2Y)
11 4Y Output Final Output (drives LED)
12 4 A Input Connect to Pin 8 (3Y)
13 4B Input Connect to Pin 8 (3Y)
14 VCC Power Connect to +5 V

Wiring guide

  • VCC: Connect V1 positive terminal, U1 pin 14, and the common side of SW1.
  • GND: Connect V1 negative terminal, U1 pin 7, R1 (bottom), R2 (bottom), R3 (bottom), and D1 (cathode).
  • Input_A: Connect SW1 (Switch 1) to R1 (top) and U1 pin 1.
  • Input_B: Connect SW1 (Switch 2) to R2 (top) and U1 pin 2.
  • Input_C (Veto): Connect SW1 (Switch 3) to R3 (top) and U1 pin 9.
  • Node_NAND1: Connect U1 pin 3 (Output 1) to U1 pin 4 and U1 pin 5 (Inputs of Gate 2).
  • Node_AND_AB: Connect U1 pin 6 (Output 2) to U1 pin 10 (Input of Gate 3).
  • Node_NAND_FINAL: Connect U1 pin 8 (Output 3) to U1 pin 12 and U1 pin 13 (Inputs of Gate 4).
  • Vout: Connect U1 pin 11 (Final Output) to R4 (one side).
  • LED_Anode: Connect R4 (other side) to D1 (anode).

Conceptual block diagram

Conceptual block diagram — 74HC00 NAND gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Practical Case: Veto Voting System (74HC00 Logic Flow)

INPUTS (Active High)           LOGIC PROCESSING (74HC00 Quad NAND)                               OUTPUT
=======================================================================================================

[ SW A + R1 ] --(Pin 1)-->+
                          |
                    [ U1: Gate 1 ] --(Pin 3)--> [ U1: Gate 2 ] --(Pin 6)---+
                    [ 2-In NAND  ]              [ NAND as NOT]             |
                          |                     (Pins 4+5)                 |
[ SW B + R2 ] --(Pin 2)-->+                                                |
                                                                           |
                                                                           v
                                                                     [ U1: Gate 3 ] --(Pin 8)--> [ U1: Gate 4 ] --(Pin 11)--> [ R4: 330R ] --> [ D1: LED ] --> GND
                                                                     [ 2-In NAND  ]              [ NAND as NOT]
                                                                     (Pin 10)      \             (Pins 12+13)
                                                                                    \
[ SW C + R3 ] -------------------------------------------------------(Pin 9)---------+
(Veto/Enable)

=======================================================================================================
Logic Summary:
1. Gate 1 & 2 form an AND gate for Inputs A & B.
2. Gate 3 & 4 form an AND gate for (Result of A/B) & Input C.
3. Final Function: LED turns ON only if A AND B AND C are all High.
Electrical Schematic

Electrical diagram

Electrical diagram for case: Veto Voting System
Generated from the validated SPICE netlist for this case.

🔒 This electrical diagram is premium. With the monthly membership (7-day free trial) you can unlock the complete didactic material and the print-ready PDF pack.🔓 See premium access plans

Truth table

The circuit implements the logic function Y = A · B · C.
* A/B: Voters
* C: Chairman/Authorization (0 = Veto/Block, 1 = Allow)

Input A (Voter 1) Input B (Voter 2) Input C (Authorization) Output Y (LED) Result
0 0 0 0 Fail
0 1 1 0 Fail (Lack of votes)
1 0 1 0 Fail (Lack of votes)
1 1 0 0 VETOED
1 1 1 1 Approved

Measurements and tests

  1. Supply Check: Before inserting the IC, verify 5 V between VCC and GND lines on your breadboard.
  2. Default State: Ensure all switches are OFF. Power on. LED should be OFF.
  3. Veto Test: Turn Switch A and Switch B ON (High). Keep Switch C OFF (Low).
    • Observation: LED must remain OFF. This confirms the Veto is active.
  4. Approval Test: With A and B still ON, turn Switch C ON.
    • Observation: LED should light up (Logic High, approx 3.5 V – 4.5 V).
  5. Single Vote Test: Turn Switch A OFF while B and C are ON.
    • Observation: LED should turn OFF.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Veto Voting System
.width out=256

* ==============================================================================
* Components and Models
* ==============================================================================

* LED Model
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=10p)

* 74HC00 Quad 2-Input NAND Gate Subcircuit
* Pins: 1=1A, 2=1B, 3=1Y, 4=2A, 5=2B, 6=2Y, 7=GND, 8=3Y, 9=3A, 10=3B, 11=4Y, 12=4A, 13=4B, 14=VCC
.subckt 74HC00 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Logic Threshold (2.5V) and Gain (20)
.param Vth=2.5
.param K=20
* Gate 1: Inputs 1,2 -> Output 3
B1 3 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(1,7)-Vth)))) * (1/(1+exp(-K*(V(2,7)-Vth)))))
* Gate 2: Inputs 4,5 -> Output 6
B2 6 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(4,7)-Vth)))) * (1/(1+exp(-K*(V(5,7)-Vth)))))
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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🔓 See premium access plans 

* Practical case: Veto Voting System
.width out=256

* ==============================================================================
* Components and Models
* ==============================================================================

* LED Model
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=10p)

* 74HC00 Quad 2-Input NAND Gate Subcircuit
* Pins: 1=1A, 2=1B, 3=1Y, 4=2A, 5=2B, 6=2Y, 7=GND, 8=3Y, 9=3A, 10=3B, 11=4Y, 12=4A, 13=4B, 14=VCC
.subckt 74HC00 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Logic Threshold (2.5V) and Gain (20)
.param Vth=2.5
.param K=20
* Gate 1: Inputs 1,2 -> Output 3
B1 3 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(1,7)-Vth)))) * (1/(1+exp(-K*(V(2,7)-Vth)))))
* Gate 2: Inputs 4,5 -> Output 6
B2 6 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(4,7)-Vth)))) * (1/(1+exp(-K*(V(5,7)-Vth)))))
* Gate 3: Inputs 9,10 -> Output 8
B3 8 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(9,7)-Vth)))) * (1/(1+exp(-K*(V(10,7)-Vth)))))
* Gate 4: Inputs 12,13 -> Output 11
B4 11 7 V = V(14,7) * (1 - (1/(1+exp(-K*(V(12,7)-Vth)))) * (1/(1+exp(-K*(V(13,7)-Vth)))))
.ends 74HC00

* ==============================================================================
* Main Circuit Wiring
* ==============================================================================

* Power Supply (V1)
V1 VCC 0 DC 5

* Inputs (Simulating Switches SW1 positions A, B, C)
* Generating dynamic pulses to test the truth table (000 to 111)
* Input A (LSB, Period 100us)
Va Input_A 0 PULSE(0 5 10u 1u 1u 50u 100u)
* Input B (Period 200us)
Vb Input_B 0 PULSE(0 5 10u 1u 1u 100u 200u)
* Input C (MSB, Period 400us)
Vc Input_C 0 PULSE(0 5 10u 1u 1u 200u 400u)

* Pull-down Resistors (R1, R2, R3)
R1 Input_A 0 10k
R2 Input_B 0 10k
R3 Input_C 0 10k

* Logic IC U1 (74HC00)
* Connectivity based on Wiring Guide:
* Pin 1 (In A) -> Input_A
* Pin 2 (In B) -> Input_B
* Pin 3 (Out 1) -> Node_NAND1
* Pin 4 (In 2A) -> Node_NAND1
* Pin 5 (In 2B) -> Node_NAND1
* Pin 6 (Out 2) -> Node_AND_AB
* Pin 7 (GND)   -> 0
* Pin 8 (Out 3) -> Node_NAND_FINAL
* Pin 9 (In 3A) -> Input_C
* Pin 10 (In 3B)-> Node_AND_AB
* Pin 11 (Out 4)-> Vout
* Pin 12 (In 4A)-> Node_NAND_FINAL
* Pin 13 (In 4B)-> Node_NAND_FINAL
* Pin 14 (VCC)  -> VCC
XU1 Input_A Input_B Node_NAND1 Node_NAND1 Node_NAND1 Node_AND_AB 0 Node_NAND_FINAL Input_C Node_AND_AB Vout Node_NAND_FINAL Node_NAND_FINAL VCC 74HC00

* Output Stage
R4 Vout LED_Anode 330
D1 LED_Anode 0 DLED

* ==============================================================================
* Simulation Commands
* ==============================================================================

.op
.tran 1u 500u

* Print Inputs and Output to check logic (Vout should be High only when A, B, C are High)
.print tran V(Input_A) V(Input_B) V(Input_C) V(Vout)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation successfully sweeps inputs A, B, and C. Vout is High (5V) only when A, B, and C are all High (e.g., around 33us, 301us, 559us). In all other states (000, 011, 101, 110, etc.), Vout remains Low (~0V). This matches the logic Y = A · B · C.
Show raw data table (671 rows) 
Index   time            v(input_a)      v(input_b)      v(input_c)      v(vout)
0	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
1	1.000000e-08	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
2	2.000000e-08	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
3	4.000000e-08	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
4	8.000000e-08	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
5	1.600000e-07	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
6	3.200000e-07	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
7	6.400000e-07	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
8	1.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
9	2.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
10	3.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
11	4.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
12	5.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
13	6.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
14	7.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
15	8.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
16	9.280000e-06	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
17	1.000000e-05	0.000000e+00	0.000000e+00	0.000000e+00	-6.01853e-36
18	1.010000e-05	5.000000e-01	5.000000e-01	5.000000e-01	-6.01853e-36
19	1.030000e-05	1.500000e+00	1.500000e+00	1.500000e+00	-6.01853e-36
20	1.048757e-05	2.437858e+00	2.437858e+00	2.437858e+00	-6.01853e-36
21	1.071179e-05	3.558937e+00	3.558937e+00	3.558937e+00	5.000000e+00
22	1.085965e-05	4.298271e+00	4.298271e+00	4.298271e+00	5.000000e+00
23	1.099537e-05	4.976846e+00	4.976846e+00	4.976846e+00	5.000000e+00
... (647 more rows) ...

Common mistakes and how to avoid them

  1. Floating Inputs: Forgetting the pull-down resistors (R1, R2, R3). Without them, the CMOS inputs of the 74HC00 will float, causing erratic switching or oscillation.
  2. Confusing Pinout: The 74HC00 pinout is standard, but mixing up Input pins (e.g., 1 A/1B) with Output pins (e.g., 1Y) is common. Double-check the datasheet diagram.
  3. Misinterpreting «Veto»: In this design, Input C is an «Enable» line (Active High). If you think of Veto as «Switch ON to Block» (Active Low logic), the wiring of Switch C would need to be inverted. Here, Switch C ON means «Authorize».

Troubleshooting

  • LED never turns ON: Check that the LED polarity is correct (Anode to resistor, Cathode to GND). Verify U1 is powered (Pin 14 to 5 V, Pin 7 to GND).
  • LED stays ON even when switches are OFF: Check if R1, R2, or R3 are missing or disconnected. Ensure you are not using NC (Normally Closed) switches by mistake.
  • Circuit works for A and B but C has no effect: Check the wiring on Gate 3 (Pins 8, 9, 10). Ensure pin 9 connects to Switch C and pin 10 connects to the output of the previous stage (Pin 6).

Possible improvements and extensions

  1. Veto Indicator: Add a second LED (Green) driven by an unused gate (or a transistor) connected to Input C, indicating «Session Open» (Authorization Granted) or «Session Locked» (Veto).
  2. Majority Vote Modification: Redesign the circuit to allow the proposal to pass if any two of the three members (A, B, C) vote Yes, removing the specific veto power and making all members equal.

More Practical Cases on Prometeo.blog

Find this product and/or books on this topic on Amazon

Go to Amazon

As an Amazon Associate, I earn from qualifying purchases. If you buy through this link, you help keep this project running.

Quick Quiz

Question 1: What is the primary objective of the circuit described in the text?




Question 2: Which specific integrated circuit (IC) is specified to implement the logic?




Question 3: What exact condition is required for the proposal to pass (LED ON)?




Question 4: What role does Member C play in this circuit?




Question 5: In the 'Safety Interlocks' use case, what does Input C represent?




Question 6: Based on the required outcome (High only if A, B, and C are High), what logic function is this circuit implementing?




Question 7: What happens to the output if Member C sets their input to Logic Low?




Question 8: Which real-world scenario is NOT listed as a use case for this circuit?




Question 9: If Member A votes 'Yes' (High) and Member B votes 'No' (Low), what is the output state?




Question 10: Why is the 74HC00 IC suitable for this specific task?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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