Practical case: Debouncing SR Latch with NAND

Debouncing SR Latch with NAND prototype (Maker Style)

Level: Medium – Build a stable memory circuit to eliminate mechanical switch noise using cross-coupled NAND gates.

Objective and use case

In this practical case, you will build a Set-Reset (SR) Latch using a 74HC00 IC. By arranging two NAND gates in a cross-coupled feedback topology, the circuit creates a bistable memory element that ignores the mechanical «bouncing» noise generated when a physical switch contacts are closed.

Why it is useful:
* Mechanical switch interfacing: Essential for reading buttons in digital systems without false triggering.
* Microcontroller interrupts: Provides a clean edge (rising/falling) to trigger hardware interrupts reliably.
* State retention: Maintains the last known state (Set or Reset) even after the input trigger is released (return to idle).
* Industrial control: Used in «Start/Stop» motor control circuits where stability is safety-critical.

Expected outcome:
* Q Output: Stays HIGH (5 V) when Set is triggered and remains HIGH until Reset is triggered.
* Q_bar Output: Always the inverse of Q (Logic LOW when Q is HIGH).
* Visual feedback: Two LEDs (Green and Red) indicating the stored state clearly.
* Noise immunity: The output transitions once cleanly, even if the switch contacts bounce multiple times in milliseconds.

Target audience and level: Electronics students and intermediate hobbyists.

Materials

  • V1: 5 V DC supply
  • U1: 74HC00 (Quad 2-Input NAND Gate)
  • SW1: SPDT (Single Pole Double Throw) switch, function: Set/Reset selector
  • R1: 10 kΩ resistor, function: pull-up for SET_N
  • R2: 10 kΩ resistor, function: pull-up for RESET_N
  • R3: 330 Ω resistor, function: LED current limiting for Q
  • R4: 330 Ω resistor, function: LED current limiting for Q_bar
  • D1: Green LED, function: Indicator for State Q (Active)
  • D2: Red LED, function: Indicator for State Q_bar (Inactive)
  • C1: 100 nF capacitor, function: decoupling for U1 power pins

Pin-out of the IC used

Chip: 74HC00 (Quad 2-Input NAND Gate)

Pin Name Logic function Connection in this case
1 1 A Input Connects to Node SET_N
2 1B Input Connects to Node Q_BAR (Feedback)
3 1Y Output Connects to Node Q
4 2 A Input Connects to Node RESET_N
5 2B Input Connects to Node Q (Feedback)
6 2Y Output Connects to Node Q_BAR
7 GND Ground Connects to Node 0
14 VCC Power Connects to Node VCC (5 V)

Wiring guide

  • Power Supply:
  • Connect V1 positive terminal to node VCC.
  • Connect V1 negative terminal to node 0 (GND).
  • Connect C1 between VCC and 0 (close to U1).
  • Connect U1 pin 14 to VCC.

  • Connect U1 pin 7 to 0.

  • Input Stage (Switch and Pull-ups):

  • Connect R1 between VCC and node SET_N.
  • Connect R2 between VCC and node RESET_N.
  • Connect SW1 Common terminal to node 0.
  • Connect SW1 Normally Open (NO) terminal to node SET_N.

  • Connect SW1 Normally Closed (NC) terminal to node RESET_N. (Note: Toggling SW1 pulls one line Low while the other stays High).

  • Logic Core (Cross-coupled NANDs):

  • Connect U1 pin 1 (1 A) to node SET_N.
  • Connect U1 pin 2 (1B) to node Q_BAR.
  • Connect U1 pin 3 (1Y) to node Q.
  • Connect U1 pin 4 (2 A) to node RESET_N.
  • Connect U1 pin 5 (2B) to node Q.

  • Connect U1 pin 6 (2Y) to node Q_BAR.

  • Output Stage (Indicators):

  • Connect R3 between node Q and D1 Anode.
  • Connect D1 Cathode to node 0.
  • Connect R4 between node Q_BAR and D2 Anode.
  • Connect D2 Cathode to node 0.

Conceptual block diagram

Conceptual block diagram — 74HC00 Feedback: Q sends state to …
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Debouncing SR Latch with NAND

      INPUT STAGE (Switch & Pull-ups)           LOGIC CORE (74HC00 Latch)               OUTPUT STAGE (Indicators)
      ================================          =========================               =========================

      [ VCC ]
         |
         V
      [ R1: 10k Pull-up ]
         |
         V
      (Node: SET_N) --------------------------> [ U1: NAND Gate A ] --(Signal: Q)-----> [ R3: 330 ] --> [ D1: Green LED ] --> GND
         ^                                      ^       |
         |                                      |       |
      [ SW1: SPDT Switch ]                      |       +--(Feedback: Q sends state to Gate B)
      (Connects GND to SET_N or RESET_N)        |
         |                                      +--(Feedback: Q_BAR maintains state of Gate A)
         v                                              |
      (Node: RESET_N) ------------------------> [ U1: NAND Gate B ] --(Signal: Q_BAR)-> [ R4: 330 ] --> [ D2: Red LED ] ----> GND
         ^
         |
      [ R2: 10k Pull-up ]
         |
         ^
         |
      [ VCC ]


      POWER & DECOUPLING:
      [ VCC ] --(Power)--> [ U1: Pin 14 ]
      [ GND ] --(Ground)--> [ U1: Pin 7 ]
      [ VCC ] --(Filter)--> [ C1: 100nF ] --> [ GND ]
Electrical Schematic

Truth table

The NAND SR Latch inputs are Active Low.

SET_N (Input) RESET_N (Input) Q (Output) Q_bar (Output) State Description
1 (High) 1 (High) Previous Q Previous Q_bar Hold (Memory)
0 (Low) 1 (High) 1 0 Set
1 (High) 0 (Low) 0 1 Reset
0 (Low) 0 (Low) 1 1 Invalid (Avoid)

Measurements and tests

  1. Initial Power-Up: Turn on the 5 V supply. Ensure SW1 is in one specific position.
  2. Verify Reset: Toggle SW1 to pull RESET_N Low (and SET_N High).
    • Confirm Red LED (D2, Q_bar) turns ON.
    • Confirm Green LED (D1, Q) turns OFF.
    • Measure voltage at Q: should be approx 0 V.
  3. Verify Set: Toggle SW1 to pull SET_N Low.
    • Confirm Green LED (D1, Q) turns ON.
    • Confirm Red LED (D2, Q_bar) turns OFF.
    • Measure voltage at Q: should be approx 5 V.
  4. Debounce Test: While moving the switch, observe the LEDs. They should switch states instantly without flickering, even if the switch contact is imperfect.
  5. Disconnect Test (Hold State): If you unplug the switch wires so both inputs are pulled High by R1/R2, the LEDs must maintain their last valid state.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Title: Practical case: Debouncing SR Latch with NAND
* NGSPICE Netlist
.width out=256

* --- Power Supply ---
V1 VCC 0 DC 5
C1 VCC 0 100n

* --- Input Stage (Switch and Pull-ups) ---
* R1 Pull-up for SET_N
R1 VCC SET_N 10k
* R2 Pull-up for RESET_N
R2 VCC RESET_N 10k

* --- Switch Simulation (SW1 SPDT) ---
* Control Signal Source
V_SW_CTRL CTRL 0 PULSE(0 5 100u 1u 1u 200u 600u)

* Inverted control signal for the NC contact
B_SW_INV CTRL_N 0 V=5-V(CTRL)
* ... (truncated in public view) ...

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* Title: Practical case: Debouncing SR Latch with NAND
* NGSPICE Netlist
.width out=256

* --- Power Supply ---
V1 VCC 0 DC 5
C1 VCC 0 100n

* --- Input Stage (Switch and Pull-ups) ---
* R1 Pull-up for SET_N
R1 VCC SET_N 10k
* R2 Pull-up for RESET_N
R2 VCC RESET_N 10k

* --- Switch Simulation (SW1 SPDT) ---
* Control Signal Source
V_SW_CTRL CTRL 0 PULSE(0 5 100u 1u 1u 200u 600u)

* Inverted control signal for the NC contact
B_SW_INV CTRL_N 0 V=5-V(CTRL)

* Switch Models (Threshold 2.5V)
.model SW_MECH SW(Vt=2.5 Vh=0.1 Ron=0.1 Roff=100Meg)

* S1 (NO Contact): Connects SET_N to 0 when CTRL is High
S1 SET_N 0 CTRL 0 SW_MECH

* S2 (NC Contact): Connects RESET_N to 0 when CTRL_N is High (CTRL is Low)
S2 RESET_N 0 CTRL_N 0 SW_MECH

* --- Logic Core (74HC00 Quad 2-Input NAND) ---
* Subcircuit for 74HC00 using robust behavioral NAND gates
* Pinout: 1=1A, 2=1B, 3=1Y, 4=2A, 5=2B, 6=2Y, 7=GND, 14=VCC
.subckt 74HC00 1 2 3 4 5 6 7 14
    * Gate 1 (Pins 1, 2 -> Output 3)
    * Logic: NAND. Implementation: Sigmoid-based continuous function for convergence.
    * Vout = VCC * (1 - (Sigmoid(A) * Sigmoid(B)))
    B_NAND1 3 7 V=V(14) * (1 - ( (1/(1+exp(-50*(V(1)-2.5)))) * (1/(1+exp(-50*(V(2)-2.5)))) ))

    * Gate 2 (Pins 4, 5 -> Output 6)
    B_NAND2 6 7 V=V(14) * (1 - ( (1/(1+exp(-50*(V(4)-2.5)))) * (1/(1+exp(-50*(V(5)-2.5)))) ))
.ends

* --- Instantiate U1 ---
* Wiring per guide: 1=SET_N, 2=Q_BAR, 3=Q, 4=RESET_N, 5=Q, 6=Q_BAR, 7=0, 14=VCC
XU1 SET_N Q_BAR Q RESET_N Q Q_BAR 0 VCC 74HC00

* --- Output Stage (Indicators) ---
* R3 between node Q and D1 Anode
R3 Q D1_A 330
* D1 Green LED (Q Active)
D1 D1_A 0 LED_GREEN

* R4 between node Q_BAR and D2 Anode
R4 Q_BAR D2_A 330
* D2 Red LED (Q_BAR Inactive)
D2 D2_A 0 LED_RED

* LED Models
.model LED_GREEN D(Is=1e-22 Rs=5 N=1.5 Eg=2.1)
.model LED_RED D(Is=1e-22 Rs=5 N=1.5 Eg=1.8)

* --- Simulation Commands ---
.op
.tran 1u 1ms

* --- Measurements ---
* Listing SET_N (Input) and Q (Output) first
.print tran V(SET_N) V(Q) V(RESET_N) V(Q_BAR) V(CTRL)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation confirms correct SR Latch behavior. At t=0, SET_N is Low and RESET_N is High, resulting in Q=High (Set state). At t=100us, the switch toggles: SET_N goes High and RESET_N goes Low, causing Q to go Low and Q_BAR to go High (Reset state). The latch holds state correctly between transitions.
* bom_vs_spice equivalences ignored:
*   - SW1 (SPDT Switch) is modeled using a voltage-controlled switch pair (S1, S2) driven by a PULSE source (V_SW_CTRL) and its inverse.
*   - U1 (74HC00 Quad NAND) is modeled using a behavioral subcircuit with sigmoid-based voltage sources.
* overall_comment: The circuit is a textbook example of a NAND-based SR latch used for switch debouncing. The SPICE implementation faithfully follows the wiring guide, using a clever behavioral model for the 74HC00 and a dual-switch setup to simulate the SPDT action. The transient analysis clearly demonstrates the Set and Reset actions corresponding to the switch position, matching the provided truth table perfectly.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation confirms correct SR Latch behavior. At t=0, SET_N is Low and RESET_N is High, resulting in Q=High (Set state). At t=100us, the switch toggles: SET_N goes High and RESET_N goes Low, causing Q to go Low and Q_BAR to go High (Reset state). The latch holds state correctly between transitions.
Show raw data table (1072 rows) 
Index   time            v(set_n)        v(q)            v(reset_n)      v(q_bar)        v(ctrl)
0	0.000000e+00	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
1	1.000000e-08	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
2	2.000000e-08	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
3	4.000000e-08	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
4	8.000000e-08	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
5	1.600000e-07	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
6	3.200000e-07	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
7	6.400000e-07	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
8	1.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
9	2.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
10	3.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
11	4.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
12	5.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
13	6.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
14	7.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
15	8.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
16	9.280000e-06	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
17	1.028000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
18	1.128000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
19	1.228000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
20	1.328000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
21	1.428000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
22	1.528000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
23	1.628000e-05	4.999500e+00	3.709206e-68	4.999950e-05	5.000000e+00	0.000000e+00
... (1048 more rows) ...

Common mistakes and how to avoid them

  1. Leaving inputs floating: If you remove the switch and don’t have resistors R1/R2, the inputs float, causing unpredictable oscillation. Solution: Always use pull-up resistors (10 kΩ) on NAND latch inputs.
  2. Confusing Active Low vs. Active High: Users often expect «1» to set the latch. A NAND latch sets when the input goes to «0». Solution: Remember that NAND latches trigger on ground (Low) pulses.
  3. Forbidden State: pressing two buttons simultaneously (if using buttons instead of SPDT) creates Logic 0 on both inputs, forcing both outputs High. Solution: Mechanically prevent simultaneous presses or design logic to prioritize one input.

Troubleshooting

  • Both LEDs are ON:
    • Cause: Both SET_N and RESET_N are connected to Ground (Logic 0) simultaneously.
    • Fix: Check the switch wiring; ensure you are not shorting both inputs to ground.
  • Circuit does not latch (LEDs flicker or follow switch loosely):
    • Cause: Missing feedback connection.
    • Fix: Ensure the wire from Pin 3 (Q) goes to Pin 5, and Pin 6 (Q_BAR) goes to Pin 2.
  • Chip gets hot:
    • Cause: Output short circuit or reversed supply polarity.
    • Fix: Check that R3 and R4 are present (do not connect LEDs directly to outputs) and verify Pin 14 is 5 V and Pin 7 is GND.

Possible improvements and extensions

  1. Gated SR Latch: Add two extra NAND gates (using the remaining two in the 74HC00) to add an «Enable» signal, turning it into a synchronous memory cell.
  2. Digital Counter Driver: Use the Q output to drive the clock input of a CD4017 or 74HC4017 counter, proving that the manual button press generates exactly one clean clock pulse.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: Which IC is used to build the SR Latch in this practical case?




Question 2: What specific topology is used to connect the two NAND gates to create the latch?




Question 3: What is the primary problem this circuit solves when interfacing with mechanical switches?




Question 4: According to the expected outcome, what is the state of the Q Output when Set is triggered?




Question 5: What is the relationship between the Q output and the Q_bar output?




Question 6: What happens to the stored state when the input trigger is released and returns to idle?




Question 7: Why is this circuit described as a 'bistable' memory element?




Question 8: Which of the following is a specific use case mentioned for this circuit?




Question 9: In an industrial context, what type of control circuit relies on this stability?




Question 10: What visual feedback is used in this practical case to indicate the stored state?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: CMOS linear amplifier

CMOS linear amplifier prototype (Maker Style)

Level: Advanced. Configure a 74HC04 inverter as a Class A linear analog amplifier using negative feedback.

Objective and use case

You will construct a single-stage voltage amplifier using one inverter gate from a 74HC04 IC, biased into its linear region via a feedback resistor. This configuration forces the digital gate to act as an analog inverting amplifier for small AC signals.

Why it is useful:
* Internal structure analysis: Demonstrates that digital logic gates are constructed from analog transistors (MOSFETs) and possess an active linear region.
* Crystal oscillators: This topology is the fundamental building block for Pierce oscillators used in clock generation.
* Low-cost amplification: Provides a simple, cheap high-impedance amplifier for piezoelectric sensors or microphones without requiring a dedicated Op-Amp.
* Signal buffering: Can be used to square up «lazy» analog edges into sharp digital pulses if the feedback is adjusted.

Expected outcome:
* Self-biasing: The input and output DC voltage settles automatically at approximately VCC / 2 (e.g., ~2.5 V).
* Amplification: An input sine wave of 50 mVpp results in an amplified inverted output sine wave.
* Linearity: The output signal replicates the input shape without clipping (provided the input signal remains small).

Target audience and level:
Electronic engineering students and analog system designers (Level: Advanced).

Materials

  • U1: 74HC04 (Hex Inverter), function: active amplification element.
  • Rf: 1 MΩ resistor, function: negative feedback for DC biasing (Class A operation).
  • Cin: 100 nF ceramic capacitor, function: AC coupling for input signal.
  • Cout: 10 µF electrolytic capacitor, function: AC coupling for load.
  • RL: 10 kΩ resistor, function: output load simulation.
  • V1: 5 V DC supply, function: main power source.
  • V_SIG: Signal generator, function: 1 kHz sine wave, 50 mVpp (with 0 V DC offset).

Pin-out of the IC used

Chip: 74HC04 (Hex Inverter)

Pin Name Logic function Connection in this case
1 1 A Inverter 1 Input Connected to GATE_IN
2 1Y Inverter 1 Output Connected to GATE_OUT
7 GND Ground Connected to 0 (GND)
14 VCC Power Supply Connected to VCC
3,5,9,11,13 Inputs Unused Inputs Connect to 0 (GND) to prevent oscillation

Wiring guide

  • V1: Positive terminal to VCC, negative terminal to 0.
  • U1: Pin 14 to VCC, Pin 7 to 0.
  • Unused Inputs: U1 pins 3, 5, 9, 11, 13 to 0 (Essential for stability).
  • Rf: Connect between GATE_IN (Pin 1) and GATE_OUT (Pin 2).
  • Cin: Connect between VIN_AC (Signal Generator output) and GATE_IN.
  • U1 Gate: Pin 1 to GATE_IN, Pin 2 to GATE_OUT.
  • Cout: Positive terminal to GATE_OUT, negative terminal to VOUT_LOAD.
  • RL: Connect between VOUT_LOAD and 0.
  • V_SIG: Output to VIN_AC, Ground to 0.

Conceptual block diagram

Conceptual block diagram — 74HC04 NOT gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Practical case: CMOS linear amplifier

                                            (Feedback Loop)
                                  .-----------[ Rf: 1 MΩ ]------------.
                                  |                                   |
                                  V                                   |
[ V_SIG ] --(Signal)--> [ Cin: 100nF ] --(Pin 1)--> [ U1: 74HC04 ] --(Pin 2)--> [ Cout: 10µF ] --> [ RL: 10 kΩ ] --> GND
                                                          ^
                                                          |
                                                 [ Power: 5 V / GND ]
                                                 [ Unused Pins: 0 V ]
Electrical Schematic

Truth table

Although operated as an analog amplifier, the 74HC04 maintains its digital truth table logic if driven rail-to-rail.

Input (A) Output (Y)
L (0 V) H (5 V)
H (5 V) L (0 V)

Measurements and tests

  1. DC Bias Check:

    • Disconnect V_SIG temporarily.
    • Measure the DC voltage at GATE_IN and GATE_OUT.
    • Validation: Both should measure approximately VCC / 2 (around 2.5 V). This confirms the feedback resistor Rf has correctly biased the inverter into the transition region.

  2. AC Gain Measurement:

    • Reconnect V_SIG (1 kHz, sine, 50 mVpp).
    • Use an oscilloscope to observe Channel 1 at VIN_AC and Channel 2 at GATE_OUT.
    • Validation: Calculate Voltage Gain Av = Voutpp / Vinpp. You should observe an inverted sine wave with significant gain (typically 10x to 100x depending on the specific manufacturer of the 74HC04).

  3. Linearity Limit:

    • Slowly increase the amplitude of V_SIG.
    • Validation: Observe the point where the output sine wave flattens at the top (near 5 V) and bottom (near 0 V). This is the dynamic range limit.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: CMOS linear amplifier
* 74HC04 Hex Inverter Linear Amplifier Configuration

* --- Power Supply ---
* V1: 5V DC supply
V1 VCC 0 DC 5

* --- Signal Generator ---
* V_SIG: 1 kHz sine wave, 50 mVpp (25 mV amplitude), 0 V DC offset
V_SIG VIN_AC 0 SIN(0 25m 1k)

* --- Components ---

* Cin: 100 nF ceramic capacitor for AC coupling input
Cin VIN_AC GATE_IN 100n

* Rf: 1 MΩ resistor for negative feedback (DC biasing)
Rf GATE_IN GATE_OUT 1Meg

* U1: 74HC04 Hex Inverter
* ... (truncated in public view) ...

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* Practical case: CMOS linear amplifier
* 74HC04 Hex Inverter Linear Amplifier Configuration

* --- Power Supply ---
* V1: 5V DC supply
V1 VCC 0 DC 5

* --- Signal Generator ---
* V_SIG: 1 kHz sine wave, 50 mVpp (25 mV amplitude), 0 V DC offset
V_SIG VIN_AC 0 SIN(0 25m 1k)

* --- Components ---

* Cin: 100 nF ceramic capacitor for AC coupling input
Cin VIN_AC GATE_IN 100n

* Rf: 1 MΩ resistor for negative feedback (DC biasing)
Rf GATE_IN GATE_OUT 1Meg

* U1: 74HC04 Hex Inverter
* Instantiated as a subcircuit to strictly follow pinout and wiring guide.
* Pinout: 1=1A, 2=1Y, 3=2A, 4=2Y, 5=3A, 6=3Y, 7=GND, 8=4Y, 9=4A, 10=5Y, 11=5A, 12=6Y, 13=6A, 14=VCC
* Connected: Pin 1->GATE_IN, Pin 2->GATE_OUT, Pin 7->0, Pin 14->VCC
* Unused Inputs (3, 5, 9, 11, 13) connected to 0 (Ground).
* Unused Outputs (4, 6, 8, 10, 12) left as floating nodes (NC_x).
XU1 GATE_IN GATE_OUT 0 NC_2 0 NC_3 0 NC_4 0 NC_5 0 NC_6 0 VCC 74HC04

* Cout: 10 µF electrolytic capacitor for AC coupling load
* Connected from GATE_OUT (approx 2.5V DC) to VOUT_LOAD (0V DC)
Cout GATE_OUT VOUT_LOAD 10u

* RL: 10 kΩ load resistor
RL VOUT_LOAD 0 10k

* --- Subcircuit Models ---

* Subcircuit for 74HC04 Hex Inverter
* Implements 6 inverters using robust continuous behavioral sources (tanh).
* Model assumes Vth = VCC/2.
* Gain factor 100 used to approximate open-loop gain in linear region (~250) while ensuring convergence.
.subckt 74HC04 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Pin 14 = VCC, Pin 7 = GND
* Inverter 1 (1A->1Y)
B1 2 7 V = V(14,7)/2 + (V(14,7)/2) * tanh(100 * (V(14,7)/2 - V(1,7)))
* Inverter 2 (2A->2Y)
B2 4 7 V = V(14,7)/2 + (V(14,7)/2) * tanh(100 * (V(14,7)/2 - V(3,7)))
* Inverter 3 (3A->3Y)
B3 6 7 V = V(14,7)/2 + (V(14,7)/2) * tanh(100 * (V(14,7)/2 - V(5,7)))
* Inverter 4 (4A->4Y) - Note: Pin 9 is Input, Pin 8 is Output
B4 8 7 V = V(14,7)/2 + (V(14,7)/2) * tanh(100 * (V(14,7)/2 - V(9,7)))
* Inverter 5 (5A->5Y) - Note: Pin 11 is Input, Pin 10 is Output
B5 10 7 V = V(14,7)/2 + (V(14,7)/2) * tanh(100 * (V(14,7)/2 - V(11,7)))
* Inverter 6 (6A->6Y) - Note: Pin 13 is Input, Pin 12 is Output
B6 12 7 V = V(14,7)/2 + (V(14,7)/2) * tanh(100 * (V(14,7)/2 - V(13,7)))
.ends

* --- Analysis Directives ---
* Transient analysis: 5 ms duration to capture multiple 1 kHz cycles.
.tran 10u 5m

* Output variables for batch processing
* INPUT: VIN_AC, OUTPUT: VOUT_LOAD
.print tran V(VIN_AC) V(VOUT_LOAD) V(GATE_IN) V(GATE_OUT)

.op
.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation shows a functional inverting amplifier. The input signal (VIN_AC) is a ~25mV amplitude sine wave. The output (VOUT_LOAD) is an inverted sine wave with an amplitude of approximately 2.4V to 2.5V, indicating a very high gain that is causing significant clipping/saturation near the rails (approx +/- 2.5V swing). The DC bias point at GATE_IN and GATE_OUT settles near 2.5V (VCC/2) as expected for this self-biasing topology.
* bom_vs_spice equivalences ignored:
*   - U1 (74HC04) is modeled as a subcircuit using continuous behavioral voltage sources (tanh functions) to approximate the analog transfer curve of CMOS inverters.
* overall_comment: The circuit is a classic example of using a digital CMOS inverter as a linear class A amplifier. The netlist correctly implements the self-biasing scheme (Rf feedback) and AC coupling. The simulation results confirm the high open-loop gain of the HC series inverter, resulting in a heavily clipped output for a 50mVpp input. As a didactic example, it effectively demonstrates the concept, though a teacher might want to reduce the input amplitude or add an input series resistor to reduce the gain if a cleaner sine wave is desired.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation shows a functional inverting amplifier. The input signal (VIN_AC) is a ~25mV amplitude sine wave. The output (VOUT_LOAD) is an inverted sine wave with an amplitude of approximately 2.4V to 2.5V, indicating a very high gain that is causing significant clipping/saturation near the rails (approx +/- 2.5V swing). The DC bias point at GATE_IN and GATE_OUT settles near 2.5V (VCC/2) as expected for this self-biasing topology.
Show raw data table (508 rows) 
Index   time            v(vin_ac)       v(vout_load)    v(gate_in)      v(gate_out)
0	0.000000e+00	0.000000e+00	0.000000e+00	2.500000e+00	2.500000e+00
1	1.000000e-07	1.570796e-05	-3.92600e-03	2.500016e+00	2.496074e+00
2	2.000000e-07	3.141592e-05	-7.85100e-03	2.500031e+00	2.492149e+00
3	4.000000e-07	6.283179e-05	-1.56989e-02	2.500063e+00	2.484301e+00
4	8.000000e-07	1.256632e-04	-3.13823e-02	2.500126e+00	2.468618e+00
5	1.600000e-06	2.513232e-04	-6.26967e-02	2.500251e+00	2.437303e+00
6	3.200000e-06	5.026210e-04	-1.25097e-01	2.500501e+00	2.374901e+00
7	6.400000e-06	1.005039e-03	-2.48425e-01	2.500997e+00	2.251567e+00
8	1.280000e-05	2.008453e-03	-4.87825e-01	2.501977e+00	2.012143e+00
9	2.280000e-05	3.569178e-03	-8.34430e-01	2.503471e+00	1.665472e+00
10	3.280000e-05	5.115818e-03	-1.13904e+00	2.504919e+00	1.360762e+00
11	4.280000e-05	6.642268e-03	-1.39785e+00	2.506318e+00	1.101832e+00
12	5.280000e-05	8.142504e-03	-1.61199e+00	2.507667e+00	8.875322e-01
13	6.280000e-05	9.610606e-03	-1.78571e+00	2.508964e+00	7.136492e-01
14	7.280000e-05	1.104078e-02	-1.92461e+00	2.510208e+00	5.745580e-01
15	8.280000e-05	1.242738e-02	-2.03459e+00	2.511395e+00	4.643784e-01
16	9.280000e-05	1.376493e-02	-2.12112e+00	2.512524e+00	3.776434e-01
17	1.028000e-04	1.504816e-02	-2.18894e+00	2.513590e+00	3.096072e-01
18	1.128000e-04	1.627201e-02	-2.24200e+00	2.514591e+00	2.563270e-01
19	1.228000e-04	1.743163e-02	-2.28348e+00	2.515522e+00	2.146211e-01
20	1.328000e-04	1.852246e-02	-2.31590e+00	2.516381e+00	1.819734e-01
21	1.428000e-04	1.954019e-02	-2.34122e+00	2.517164e+00	1.564217e-01
22	1.528000e-04	2.048080e-02	-2.36095e+00	2.517868e+00	1.364514e-01
23	1.628000e-04	2.134059e-02	-2.37626e+00	2.518489e+00	1.209036e-01
... (484 more rows) ...

Common mistakes and how to avoid them

  1. Using the wrong logic family: Students often use 74LS04 or 74HCT04. These have internal pull-ups or different input thresholds that prevent symmetrical linear biasing. Solution: Ensure you use the 74HC04 (CMOS) or CD4069UB.
  2. Input signal too large: Applying a standard TTL/CMOS logic signal (0-5 V) will result in a square wave output, not amplification. Solution: Keep the input signal small (under 100 mVpp) to stay within the linear region.
  3. Floating unused inputs: Leaving pins 3, 5, 9, etc., disconnected causes internal noise and excessive power consumption. Solution: Always tie unused inputs of CMOS chips to Ground (0).

Troubleshooting

  • Symptom: Output is stuck at 0 V or 5 V.
    • Cause: Feedback resistor Rf is missing or open circuit.
    • Fix: Check continuity of Rf (1 MΩ). It is required to pull the input voltage to the tipping point.
  • Symptom: High frequency noise superimposed on the signal.
    • Cause: Parasitic oscillation due to high gain and stray capacitance.
    • Fix: Shorten wires or add a small capacitor (e.g., 10 pF) in parallel with Rf to reduce bandwidth.
  • Symptom: Gain is very low ($< 2$).
    • Cause: Load resistance RL is too small.
    • Fix: The output impedance of a 74HC04 in linear mode is relatively high. Increase RL to 100 kΩ or remove it for testing.

Possible improvements and extensions

  1. Crystal Oscillator: Replace the signal generator with a quartz crystal and two load capacitors (to ground) at the input and output pins to create a stable clock source.
  2. Cascaded Amplifier: Connect the output of the first stage (via a capacitor) to a second identically configured 74HC04 stage to achieve much higher total voltage gain.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the feedback resistor in this circuit configuration?




Question 2: In this self-biasing configuration, what is the expected DC voltage at the input and output (assuming a 5 V supply)?




Question 3: Which internal components of the 74HC04 allow it to function as an analog amplifier?




Question 4: This linear inverter topology is the fundamental building block for which common circuit?




Question 5: When configured with negative feedback, the inverter operates as which class of amplifier?




Question 6: What is the phase relationship between the AC input signal and the amplified output signal?




Question 7: What is a key advantage of this configuration regarding the input impedance?




Question 8: To maintain linear operation without clipping, how should the input signal be characterized?




Question 9: Besides amplification, what other use case is mentioned for this circuit topology?




Question 10: Why is the 74HC04 specifically capable of this operation?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Practical case: Ring Oscillator and Delay

Ring Oscillator and Delay prototype (Maker Style)

Level: Advanced — Build and analyze a 5-stage ring oscillator to calculate component propagation delay.

Objective and use case

In this case, you will construct a ring oscillator by cascading an odd number (5) of NOT gates (inverters) in a closed feedback loop using a 74HC04 IC. You will measure the resulting oscillation frequency to calculate the intrinsic propagation delay of the logic gates.

Why it is useful:
* Process characterization: Used in semiconductor manufacturing to test the speed and quality of silicon wafers.
* Clock generation: Fundamental topology for generating internal clocks in ASICs and FPGAs.
* Random Number Generation: The inherent jitter in ring oscillators is a source of entropy for True Random Number Generators (TRNG).
* Time-to-Digital Converters (TDC): Used to measure time intervals with high precision.

Expected outcome:
* A stable square wave output oscillating in the MHz range (typically 20 MHz–50 MHz for 74HC logic on a breadboard).
* Measurement of oscillation frequency (fosc).
* Calculation of the average propagation delay (tpd) per gate.
* Visual observation of rise (tr) and fall (tf) times due to capacitive loading.

Target audience and level:
Advanced Electronics Students; Engineering Undergraduates.

Materials

  • U1: 74HC04 Hex Inverter IC, function: logic gates for the ring
  • C1: 100 nF ceramic capacitor, function: power supply decoupling (critical for stability)
  • C2: 10 pF capacitor, function: simulated load (optional, represents probe capacitance)
  • V1: 5 V DC supply
  • W1-W5: Jumper wires, function: inter-stage connections

Pin-out of the IC used

Selected Chip: 74HC04 (Hex Inverter)

Pin Name Logic function Connection in this case
1 1 A Input 1 From Output 5 (Node N5)
2 1Y Output 1 To Input 2 (Node N1)
3 2 A Input 2 From Output 1 (Node N1)
4 2Y Output 2 To Input 3 (Node N2)
5 3 A Input 3 From Output 2 (Node N2)
6 3Y Output 3 To Input 4 (Node N3)
7 GND Ground Connect to Node 0
8 4Y Output 4 To Input 5 (Node N4)
9 4 A Input 4 From Output 3 (Node N3)
10 5Y Output 5 To Input 1 (Node N5 – Feedback)
11 5 A Input 5 From Output 4 (Node N4)
14 VCC Power Supply Connect to Node VCC (+5 V)

Note: Pins 12 (6Y) and 13 (6 A) are unused and should be left open or tied to GND/VCC depending on specific noise requirements, though for this test leaving them open is acceptable.

Wiring guide

This circuit relies on minimal trace length to sustain high-frequency oscillation.

  • V1 connects between node VCC and node 0 (GND).
  • C1 connects between node VCC and node 0 (place physically close to U1).
  • U1 (Pin 14) connects to node VCC.
  • U1 (Pin 7) connects to node 0.
  • U1 (Pin 1 – Input 1) connects to node N5 (Feedback loop closure).
  • U1 (Pin 2 – Output 1) connects to node N1.
  • U1 (Pin 3 – Input 2) connects to node N1.
  • U1 (Pin 4 – Output 2) connects to node N2.
  • U1 (Pin 5 – Input 3) connects to node N2.
  • U1 (Pin 6 – Output 3) connects to node N3.
  • U1 (Pin 9 – Input 4) connects to node N3.
  • U1 (Pin 8 – Output 4) connects to node N4.
  • U1 (Pin 11 – Input 5) connects to node N4.
  • U1 (Pin 10 – Output 5) connects to node N5.
  • C2 (Optional Load) connects between node N5 and node 0 to simulate probe capacitance.

Conceptual block diagram

Conceptual block diagram — 74HC04 NOT gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

POWER SUPPLY & DECOUPLING:
      VCC (5 V) --> [ Node VCC ] --(Pin 14)--> [ U1: 74HC04 Power ]
                      |
                    [ C1: 100nF ]
                      |
      GND (0 V) --> [ Node 0 ] --(Pin 7)---> [ U1: 74HC04 GND ]


SIGNAL FLOW (RING OSCILLATOR):
(Logic flows Left to Right, wrapping around at the end)

      [ Feedback N5 ] --> [ U1: Gate 1 ] --(Node N1)--> [ U1: Gate 2 ] --(Node N2)--> [ U1: Gate 3 ] --(Node N3)--> \
      (Input Pin 1)       (In:1 / Out:2)                (In:3 / Out:4)                (In:5 / Out:6)                |
                                                                                                                    |
      /-------------------------------------------------------------------------------------------------------------/
      |
      \--> [ U1: Gate 4 ] --(Node N4)--> [ U1: Gate 5 ] --(Node N5)--> [ C2: 10pF ] --> GND
           (In:9 / Out:8)                (In:11 / Out:10)      |
                                                               |
                                                      (Loop back to Start)
Electrical Schematic

Truth table (Single NOT Gate)

Input (A) Output (Y)
L H
H L

In a ring configuration with an odd number of stages, the logic never settles, causing perpetual oscillation.

Measurements and tests

  1. Setup: Ensure wiring is short and neat. Long wires add parasitic inductance and capacitance which will significantly lower the frequency.
  2. Visualization: Connect an oscilloscope probe (x10 attenuation recommended to reduce loading) to Node N5 (or any node N1 through N4).
  3. Frequency Measurement: Measure the frequency of the oscillation (fosc). For a 74HC series at 5 V, expect approx 20MHz – 40MHz depending on stray capacitance.
  4. Propagation Delay Calculation: Calculate the average propagation delay per gate (tpd) using the formula:
    $tpd = (1 / (2 × N × fosc))$
    Where $N = 5$ (number of stages).
    Example: If $f_{osc} = 25 MHz$, then $T = 40 ns$. $t_{pd} = 40 ns / 10 = 4 ns$.
  5. Waveform Analysis: Zoom in on the edges. Notice that the wave is not a perfect square; the rise time ($t_{r}$) and fall time ($t_{f}$) are visible due to the capacitive charging of the next gate’s input.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Ring Oscillator and Delay
.width out=256
* Ngspice Netlist

* --- Power Supply ---
* V1: 5 V DC supply connecting VCC to GND (0)
V1 VCC 0 DC 5

* --- Decoupling Capacitor ---
* C1: 100 nF ceramic capacitor, power supply decoupling
C1 VCC 0 100n

* --- Integrated Circuit U1: 74HC04 Hex Inverter ---
* Modeled as a subcircuit to strictly follow physical pinout and wiring guide.
* Pin Mapping (Standard DIP-14):
* 1:1A  2:1Y  3:2A  4:2Y  5:3A  6:3Y  7:GND
* 8:4Y  9:4A 10:5Y 11:5A 12:6Y 13:6A 14:VCC
*
* Wiring Connections based on Guide:
* Pin 1 (In1)  -> N5
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Ring Oscillator and Delay
.width out=256
* Ngspice Netlist

* --- Power Supply ---
* V1: 5 V DC supply connecting VCC to GND (0)
V1 VCC 0 DC 5

* --- Decoupling Capacitor ---
* C1: 100 nF ceramic capacitor, power supply decoupling
C1 VCC 0 100n

* --- Integrated Circuit U1: 74HC04 Hex Inverter ---
* Modeled as a subcircuit to strictly follow physical pinout and wiring guide.
* Pin Mapping (Standard DIP-14):
* 1:1A  2:1Y  3:2A  4:2Y  5:3A  6:3Y  7:GND
* 8:4Y  9:4A 10:5Y 11:5A 12:6Y 13:6A 14:VCC
*
* Wiring Connections based on Guide:
* Pin 1 (In1)  -> N5
* Pin 2 (Out1) -> N1
* Pin 3 (In2)  -> N1
* Pin 4 (Out2) -> N2
* Pin 5 (In3)  -> N2
* Pin 6 (Out3) -> N3
* Pin 7 (GND)  -> 0
* Pin 8 (Out4) -> N4
* Pin 9 (In4)  -> N3
* Pin 10 (Out5)-> N5
* Pin 11 (In5) -> N4
* Pin 12 (Out6)-> NC_OUT (Unused)
* Pin 13 (In6) -> NC_IN  (Unused)
* Pin 14 (VCC) -> VCC

XU1 N5 N1 N1 N2 N2 N3 0 N4 N3 N5 N4 NC_OUT NC_IN VCC 74HC04

* --- Load Capacitor ---
* C2: 10 pF capacitor, simulated load on Output Node N5
C2 N5 0 10p

* --- Unused Pin Termination ---
* High resistance to ground to prevent floating node errors
R_NC1 NC_OUT 0 1G
R_NC2 NC_IN 0 1G

* --- Subcircuit Definitions ---

.subckt 74HC04 1 2 3 4 5 6 7 8 9 10 11 12 13 14
    * Local Power: 14=VCC, 7=GND
    * Gate 1
    X1 1 2 14 7 inv_gate
    * Gate 2
    X2 3 4 14 7 inv_gate
    * Gate 3
    X3 5 6 14 7 inv_gate
    * Gate 4 (Note: Pin 9 is Input, Pin 8 is Output)
    X4 9 8 14 7 inv_gate
    * Gate 5 (Note: Pin 11 is Input, Pin 10 is Output)
    X5 11 10 14 7 inv_gate
    * Gate 6 (Unused)
    X6 13 12 14 7 inv_gate
.ends

.subckt inv_gate in out vcc gnd
    * Internal RC Delay Stage
    * Essential for Ring Oscillator simulation to function (creates phase shift)
    * R=1k, C=10p yields approx 10ns delay per stage
    R_delay in int 1k
    C_delay int gnd 10p
    
    * Behavioral Voltage Source (Sigmoid Inverter)
    * Uses continuous function for convergence: Vout = Vcc / (1 + exp(k*(Vin - Vcc/2)))
    * Gain factor k=10
    B_logic out gnd V=V(vcc) / (1 + exp(10 * (V(int) - V(vcc)/2)))
.ends

* --- Simulation Directives ---

* Initial Condition:
* Force node N1 to 0V at t=0 to prevent metastable state (kickstart oscillation)
.ic V(N1)=0

* Transient Analysis:
* Run for 2 microseconds, step size 1 nanosecond
* 'uic' (Use Initial Conditions) is required for .ic to take effect
.tran 1n 2u uic

* Operating Point (for check)
.op

* Output Printing:
* V(N5) is the primary OSC_OUT node
.print tran V(N5) V(N1) V(N2) V(N3) V(N4)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The transient analysis shows sustained oscillation on nodes N1 through N5. The voltages swing between ~0V and ~5V. The frequency can be inferred from the timestamps (e.g., N5 rising edges around 1.43us and subsequent cycles), confirming the ring oscillator behavior.
* bom_vs_spice equivalences ignored:
*   - U1 (74HC04 Hex Inverter) is modeled as a subcircuit using behavioral voltage sources and RC delay stages to simulate propagation delay and logic inversion.
* overall_comment: The circuit is well-modeled for a didactic example. The inclusion of internal RC delay stages inside the inverter subcircuit is crucial for a ring oscillator simulation, as ideal SPICE inverters often fail to oscillate or converge without explicit time-dependent behavior. The initial condition (.ic V(N1)=0) correctly kickstarts the oscillation. The connectivity matches the wiring guide perfectly.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The transient analysis shows sustained oscillation on nodes N1 through N5. The voltages swing between ~0V and ~5V. The frequency can be inferred from the timestamps (e.g., N5 rising edges around 1.43us and subsequent cycles), confirming the ring oscillator behavior.
Show raw data table (2039 rows) 
Index   time            v(n5)           v(n1)           v(n2)           v(n3)           v(n4)
0	1.000000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
1	1.028000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
2	1.084000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
3	1.196000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
4	1.420000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
5	1.868000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
6	2.764000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
7	4.556000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
8	8.140000e-11	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
9	1.530800e-10	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
10	2.964400e-10	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
11	5.831600e-10	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
12	1.000000e-09	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
13	1.057344e-09	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
14	1.172032e-09	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
15	1.401408e-09	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
16	1.860160e-09	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00	5.000000e+00
17	2.777664e-09	4.999998e+00	4.999998e+00	4.999998e+00	4.999998e+00	4.999998e+00
18	3.777664e-09	4.999526e+00	4.999526e+00	4.999526e+00	4.999526e+00	4.999526e+00
19	4.777664e-09	4.987728e+00	4.987728e+00	4.987728e+00	4.987728e+00	4.987728e+00
20	5.777664e-09	4.795985e+00	4.795985e+00	4.795985e+00	4.795985e+00	4.795985e+00
21	6.777664e-09	3.794650e+00	3.794650e+00	3.794650e+00	3.794650e+00	3.794650e+00
22	7.777664e-09	2.828762e+00	2.828762e+00	2.828762e+00	2.828762e+00	2.828762e+00
23	8.777664e-09	2.564867e+00	2.564867e+00	2.564867e+00	2.564867e+00	2.564867e+00
... (2015 more rows) ...

Common mistakes and how to avoid them

  1. Using an even number of gates: If you use 4 or 6 gates, the logic will settle into a stable state (latch up) rather than oscillate. Always use an odd number (3, 5, 7…).
  2. Breadboard capacitance: Standard breadboards have high parasitic capacitance between rows (approx 2-5pF). This will make the oscillator run slower than the datasheet specs imply. Avoid long jumper loops.
  3. Missing decoupling capacitor: Without C1 close to the chip, the high-frequency switching current will cause VCC sag, resulting in erratic frequency or no oscillation.

Troubleshooting

  • Output is stuck High or Low: Check that you have an odd number of inverters in the loop. Verify the feedback wire connects the last output to the first input.
  • Frequency is unstable (jitter): Likely power supply noise. Ensure C1 (100nF) is installed extremely close to pins 14 and 7.
  • Scope shows a sine wave instead of square: At very high frequencies (approaching the bandwidth limit of the scope or probe), square waves look like sine waves due to the attenuation of higher harmonics. Ensure your scope bandwidth is at least 100 MHz.
  • Circuit gets hot: Check for short circuits between outputs. Never connect two outputs together.

Possible improvements and extensions

  1. Enable Control: Replace the first inverter with a NAND gate (e.g., using 74HC00). Use one input for the feedback loop and the other as an Enable/Disable control signal.
  2. Buffered Output: Use the 6th unused inverter in the 74HC04 package as a buffer connected to one of the ring nodes. Connect your probe/load to this buffer output. This isolates the ring oscillator from the load capacitance, providing a more accurate frequency measurement.

More Practical Cases on Prometeo.blog

Find this product and/or books on this topic on Amazon

Go to Amazon

As an Amazon Associate, I earn from qualifying purchases. If you buy through this link, you help keep this project running.

Quick Quiz

Question 1: What specific arrangement of NOT gates is required to construct a ring oscillator?




Question 2: What is a strict requirement regarding the number of stages in a ring oscillator to ensure oscillation?




Question 3: What is the primary physical parameter calculated by measuring the oscillation frequency in this experiment?




Question 4: Which characteristic of ring oscillators allows them to be used for True Random Number Generators (TRNG)?




Question 5: What is the typical expected frequency range for a 5-stage ring oscillator using 74HC logic on a breadboard?




Question 6: What is the function of the 100 nF ceramic capacitor (C1) typically placed near the IC in this circuit?




Question 7: In the context of semiconductor manufacturing, why are ring oscillators useful?




Question 8: What does the optional 10 pF capacitor (C2) simulate in this experiment?




Question 9: Which IC is specifically selected to provide the logic gates for this ring oscillator?




Question 10: What type of waveform is expected at the output of the ring oscillator?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Practical case: Frequency divider by 2, 4 and 8

Frequency divider by 2, 4 and 8 prototype (Maker Style)

Level: Basic – Verify the frequency division relationship on the Q outputs of a binary counter relative to the clock.

Objective and use case

In this practical case, you will build a digital circuit using a 4-bit binary counter (74HC393) to divide an input clock signal frequency by factors of 2 (2^1), 4 (2^2), and 8 (2^3).

  • Digital Clocks: Used to divide high-frequency crystal oscillator signals down to 1 Hz for keeping time (seconds).
  • Audio Synthesis: Used to generate lower octaves from a base tone (frequency halving results in a tone one octave lower).
  • Baud Rate Generation: Used in UART communication to derive specific data transmission speeds from a master system clock.
  • Address Counters: Used to sequence through memory addresses in microcontrollers.

Expected outcome:
* Q0 Output: A square wave with a frequency exactly half of the input clock (f/2).
* Q1 Output: A square wave with a frequency one-quarter of the input clock (f/4).
* Q2 Output: A square wave with a frequency one-eighth of the input clock (f/8).
* Target Audience: Basic level students and hobbyists.

Materials

  • V1: 5 V DC supply, function: Main power source.
  • V_CLK: Pulse generator (0 V to 5 V, 1 kHz, 50% duty cycle), function: Input Clock signal.
  • U1: 74HC393, function: Dual 4-bit Binary Counter.
  • R1: 330 Ω resistor, function: Current limiting for LED D1.
  • R2: 330 Ω resistor, function: Current limiting for LED D2.
  • R3: 330 Ω resistor, function: Current limiting for LED D3.
  • D1: Red LED, function: Visual indicator for Q0 (f/2).
  • D2: Green LED, function: Visual indicator for Q1 (f/4).
  • D3: Yellow LED, function: Visual indicator for Q2 (f/8).
  • Scope: 4-Channel Oscilloscope, function: Waveform analysis.

Pin-out of the IC used

Selected Chip: 74HC393 (Dual 4-bit Binary Counter). We will use the first counter block (Side 1).

Pin Name Logic function Connection in this case
1 1CP (CLK) Clock Input (Falling edge trigger) Connected to CLK_IN
2 1MR Master Reset (Active High) Connected to 0 (GND)
3 1Q0 Output Bit 0 (Divide by 2) Connected to Q0
4 1Q1 Output Bit 1 (Divide by 4) Connected to Q1
5 1Q2 Output Bit 2 (Divide by 8) Connected to Q2
7 GND Ground Connected to 0
14 VCC Power Supply (+5 V) Connected to VCC

Wiring guide

  • V1 connects between node VCC and node 0 (GND).
  • U1 pin 14 connects to node VCC.
  • U1 pin 7 connects to node 0 (GND).
  • U1 pin 2 (Reset) connects to node 0 (GND) to enable counting.
  • V_CLK connects between node CLK_IN and node 0 (GND).
  • U1 pin 1 connects to node CLK_IN.
  • U1 pin 3 connects to node Q0.
  • U1 pin 4 connects to node Q1.
  • U1 pin 5 connects to node Q2.
  • R1 connects between node Q0 and node LED_Q0.
  • D1 anode connects to LED_Q0, cathode connects to 0 (GND).
  • R2 connects between node Q1 and node LED_Q1.
  • D2 anode connects to LED_Q1, cathode connects to 0 (GND).
  • R3 connects between node Q2 and node LED_Q2.
  • D3 anode connects to LED_Q2, cathode connects to 0 (GND).

Conceptual block diagram

Conceptual block diagram — 74HC393 Binary counter
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

INPUTS                                   PROCESSING                                     OUTPUTS / LOADS
(Left)                                    (Center)                                          (Right)

                                   +-----------------------+
                                   |                       |
 [ V_CLK: 1kHz ] --(Pin 1: CP)---> |                       | --(Pin 3: Q0)--> [ R1: 330 ] --> [ D1: Red ] --> GND
                                   |                       |       |
                                   |      U1: 74HC393      |       '--------(Scope Ch1: f/2)
                                   |      Dual 4-bit       |
                                   |      Bin Counter      |
 [ GND ] ---------(Pin 2: MR)--->  |                       | --(Pin 4: Q1)--> [ R2: 330 ] --> [ D2: Grn ] --> GND
             (Reset Disabled)      |   (Power: VCC=Pin 14, |       |
                                   |           GND=Pin 7)  |       '--------(Scope Ch2: f/4)
                                   |                       |
                                   |                       |
                                   |                       | --(Pin 5: Q2)--> [ R3: 330 ] --> [ D3: Yel ] --> GND
                                   |                       |       |
                                   +-----------------------+       '--------(Scope Ch3: f/8)
Electrical Schematic

Measurements and tests

To validate the circuit, perform the following measurements using the 4-channel oscilloscope:

  1. Setup: Connect the Ground clip of all oscilloscope probes to node 0 (GND).
  2. Channel 1 (Input): Connect to CLK_IN. Verify the frequency is 1 kHz.
  3. Channel 2 (Q0): Connect to Q0. Measure the frequency. It must be 500 Hz ($1kHz / 2$).
  4. Channel 3 (Q1): Connect to Q1. Measure the frequency. It must be 250 Hz ($1kHz / 4$).
  5. Channel 4 (Q2): Connect to Q2. Measure the frequency. It must be 125 Hz ($1kHz / 8$).
  6. Visual Check: If you lower the input clock frequency to 10 Hz, you should see D1 blinking fastest, D2 slower, and D3 slowest.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Frequency divider by 2, 4 and 8

.width out=256

* --- Models ---
* Generic LED Model
.model DLED D(IS=1e-14 N=2 RS=10 BV=5 IBV=10u CJO=10p)

* --- Power Supply ---
* V1: 5V Main Supply
V1 VCC 0 DC 5

* --- Input Signal ---
* V_CLK: 1kHz Pulse, 0V to 5V, 50% Duty Cycle
V_CLK CLK_IN 0 PULSE(0 5 0 1u 1u 0.5m 1m)

* --- Subcircuit: 74HC393 (Behavioral XSPICE) ---
* Dual 4-bit Binary Counter
* Implements Counter 1 logic using XSPICE primitives.
* Pinout (DIP-14): 1=1CP, 2=1MR, 3=1Q0, 4=1Q1, 5=1Q2, 6=1Q3, 7=GND
* ... (truncated in public view) ...

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* Practical case: Frequency divider by 2, 4 and 8

.width out=256

* --- Models ---
* Generic LED Model
.model DLED D(IS=1e-14 N=2 RS=10 BV=5 IBV=10u CJO=10p)

* --- Power Supply ---
* V1: 5V Main Supply
V1 VCC 0 DC 5

* --- Input Signal ---
* V_CLK: 1kHz Pulse, 0V to 5V, 50% Duty Cycle
V_CLK CLK_IN 0 PULSE(0 5 0 1u 1u 0.5m 1m)

* --- Subcircuit: 74HC393 (Behavioral XSPICE) ---
* Dual 4-bit Binary Counter
* Implements Counter 1 logic using XSPICE primitives.
* Pinout (DIP-14): 1=1CP, 2=1MR, 3=1Q0, 4=1Q1, 5=1Q2, 6=1Q3, 7=GND
*                  8=2Q3, 9=2Q2, 10=2Q1, 11=2Q0, 12=2MR, 13=2CP, 14=VCC
.subckt 74HC393 1CP 1MR 1Q0 1Q1 1Q2 1Q3 GND 2Q3 2Q2 2Q1 2Q0 2MR 2CP VCC

    * ADC Bridge to read analog inputs (Clock and Reset)
    .model adc_mod adc_bridge(in_low=1.5 in_high=3.5)
    A_IN [1CP 1MR] [d_1cp d_1mr] adc_mod
    
    * ADC Bridge to read GND for Logic Low (used for SET inputs)
    A_GND [GND] [d_low] adc_mod

    * Logic Models
    .model inv_mod d_inverter(rise_delay=10n fall_delay=10n)
    .model dff_mod d_dff(clk_delay=10n rise_delay=10n fall_delay=10n)
    .model dac_mod dac_bridge(out_low=0.0 out_high=5.0)

    * --- Counter Logic (Side 1) ---
    * 74HC393 triggers on High-to-Low transition of CP.
    * XSPICE DFF triggers on Rising Edge. So we invert CP.
    A_INV1 d_1cp d_1cp_inv inv_mod

    * Stage 1 (Q0): Divider by 2
    * T-FF behavior: D = ~Q. Clock = ~CP. Reset = MR.
    * Port order: din clk set reset out nout
    A_DFF1 d_1q0_bar d_1cp_inv d_low d_1mr d_1q0 d_1q0_bar dff_mod

    * Stage 2 (Q1): Divider by 4
    * Ripples from Q0 Falling Edge.
    * Q0 Falling = ~Q0 Rising. Use d_1q0_bar as clock.
    A_DFF2 d_1q1_bar d_1q0_bar d_low d_1mr d_1q1 d_1q1_bar dff_mod

    * Stage 3 (Q2): Divider by 8
    * Ripples from Q1 Falling Edge. Use d_1q1_bar as clock.
    A_DFF3 d_1q2_bar d_1q1_bar d_low d_1mr d_1q2 d_1q2_bar dff_mod

    * Stage 4 (Q3): Divider by 16 (Not used externally but part of logic)
    A_DFF4 d_1q3_bar d_1q2_bar d_low d_1mr d_1q3 d_1q3_bar dff_mod

    * Drive Outputs
    A_OUT [d_1q0 d_1q1 d_1q2 d_1q3] [1Q0 1Q1 1Q2 1Q3] dac_mod

    * Side 2 is unused, inputs grounded in main circuit, outputs open.
.ends 74HC393

* --- Main Circuit Instances ---
* U1: 74HC393 Counter
* Pin connections based on Wiring Guide:
* 1(CLK_IN), 2(0/Reset), 3(Q0), 4(Q1), 5(Q2), 7(0/GND), 14(VCC)
* Unused outputs mapped to NC nodes. Unused inputs to 0.
* Subcircuit Pin Order: 1CP 1MR 1Q0 1Q1 1Q2 1Q3 GND 2Q3 2Q2 2Q1 2Q0 2MR 2CP VCC
XU1 CLK_IN 0 Q0 Q1 Q2 NC_1Q3 0 NC_2Q3 NC_2Q2 NC_2Q1 NC_2Q0 0 0 VCC 74HC393

* --- Output Paths (LEDs and Resistors) ---
* Path 1: Q0 -> R1 -> D1 (Red)
R1 Q0 LED_Q0 330
D1 LED_Q0 0 DLED

* Path 2: Q1 -> R2 -> D2 (Green)
R2 Q1 LED_Q1 330
D2 LED_Q1 0 DLED

* Path 3: Q2 -> R3 -> D3 (Yellow)
R3 Q2 LED_Q2 330
D3 LED_Q2 0 DLED

* --- Simulation & Output ---
.op
.tran 10u 20m
.print tran V(CLK_IN) V(Q0) V(Q1) V(Q2)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation shows a clear binary counting sequence. CLK_IN is a 1kHz clock (period 1ms). Q0 toggles every 1ms (f/2, period 2ms). Q1 toggles every 2ms (f/4, period 4ms). Q2 toggles every 4ms (f/8, period 8ms). The outputs transition cleanly between 0V and 5V.
* bom_vs_spice equivalences ignored:
*   - LEDs (D1, D2, D3) are modeled using a generic diode model (DLED) with specific parameters.
*   - U1 (74HC393) is modeled as a behavioral subcircuit using XSPICE primitives (ADC/DAC bridges, DFFs) instead of a transistor-level model.
* overall_comment: The circuit is perfectly functional and accurately represents a 3-bit binary ripple counter (frequency divider). The behavioral model for the 74HC393 is correctly implemented with the necessary ADC/DAC bridges for XSPICE. The wiring matches the guide exactly, and the simulation results confirm the expected frequency division ratios (f/2, f/4, f/8). It is an excellent didactic example.
* --------------------------------------

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation shows a clear binary counting sequence. CLK_IN is a 1kHz clock (period 1ms). Q0 toggles every 1ms (f/2, period 2ms). Q1 toggles every 2ms (f/4, period 4ms). Q2 toggles every 4ms (f/8, period 8ms). The outputs transition cleanly between 0V and 5V.
Show raw data table (3323 rows) 
Index   time            v(clk_in)       v(q0)           v(q1)           v(q2)
0	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
1	1.000000e-08	5.000000e-02	0.000000e+00	0.000000e+00	0.000000e+00
2	2.000000e-08	1.000000e-01	0.000000e+00	0.000000e+00	0.000000e+00
3	4.000000e-08	2.000000e-01	0.000000e+00	0.000000e+00	0.000000e+00
4	8.000000e-08	4.000000e-01	0.000000e+00	0.000000e+00	0.000000e+00
5	1.600000e-07	8.000000e-01	0.000000e+00	0.000000e+00	0.000000e+00
6	3.200000e-07	1.600000e+00	0.000000e+00	0.000000e+00	0.000000e+00
7	6.400000e-07	3.200000e+00	0.000000e+00	0.000000e+00	0.000000e+00
8	1.000000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
9	1.064000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
10	1.192000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
11	1.448000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
12	1.960000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
13	2.984000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
14	5.032000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
15	9.128000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
16	1.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
17	2.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
18	3.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
19	4.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
20	5.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
21	6.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
22	7.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
23	8.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
... (3299 more rows) ...

Common mistakes and how to avoid them

  1. Floating the Master Reset (MR) pin: Leaving pin 2 disconnected causes the counter to reset randomly due to noise. Solution: Always tie the MR pin to GND (Logic 0) for normal counting operation.
  2. Confusing Pin Numbers: The 74HC393 has two counters inside. Students often mix pins from Counter 1 and Counter 2. Solution: Strictly follow the datasheet and use pins 1, 2, 3, 4, 5, and 6 for the first counter only.
  3. Ignoring VCC/GND: Forgetting to power the chip leads to unpredictable output or no activity. Solution: Always connect Pin 14 to +5 V and Pin 7 to GND before testing.

Troubleshooting

  • Symptom: No LEDs light up, and outputs remain at 0 V.
    • Cause: Master Reset (Pin 2) might be connected to VCC instead of GND.
    • Fix: Move connection of Pin 2 to GND.
  • Symptom: LEDs are always on or flickering very dimly.
    • Cause: Frequency is too high for the eye to see blinking (e.g., 1 kHz).
    • Fix: Use the oscilloscope to verify the signal, or lower V_CLK frequency to < 10 Hz for visual confirmation.
  • Symptom: Output frequency is unstable or erratic.
    • Cause: Noisy power supply or lack of decoupling capacitor.
    • Fix: Add a 100 nF capacitor across VCC and GND near the IC.

Possible improvements and extensions

  1. Divide by 16 and 256: Cascade the first counter into the second counter of the U1 chip (connect 1Q3 to 2CP) to achieve higher division ratios up to 256.
  2. Variable Audio Generator: Connect the outputs to a simple speaker driver and use a variable potentiometer on a 555 timer (as the clock) to hear how the pitch drops by octaves as you switch between Q0, Q1, and Q2.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What is the primary function of the 74HC393 IC used in this circuit?




Question 2: What is the frequency relationship of the Q0 output relative to the input clock (f)?




Question 3: If the input clock frequency is 1 kHz, what is the expected frequency at the Q1 output?




Question 4: What is the expected frequency relationship at the Q2 output?




Question 5: In audio synthesis, what is the result of halving a tone's frequency?




Question 6: What is the purpose of using this circuit in digital clocks?




Question 7: What DC supply voltage is specified for this circuit?




Question 8: How is this circuit applied in UART communication?




Question 9: Which power of 2 represents the division factor for the Q1 output?




Question 10: What is the role of address counters in microcontrollers?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: 4-bit up counter with LEDs

4-bit up counter with LEDs prototype (Maker Style)

Level: Basic. Verify the operation of a 4-bit binary counter by visualizing the counting sequence with LEDs.

Objective and use case

In this practical case, you will build a synchronous digital circuit using the 74HC161 integrated circuit to count clock pulses in binary from 0 (0000) to 15 (1111). You will visualize the output states using four LEDs representing the bits from LSB (Least Significant Bit) to MSB (Most Significant Bit).

Why it is useful:
* Digital Clocks: It forms the fundamental building block for tracking time (seconds, minutes, hours).
* Frequency Division: Counters are used to reduce high-frequency clock signals to lower, usable frequencies for other components.
* Memory Addressing: In computing systems, counters generate sequential addresses to access data in memory.
* Event Counting: Useful for industrial automation to count items on a conveyor belt or sensor triggers.
* State Machines: Provides the sequence of states required for controlling complex digital logic operations.

Expected outcome:
* Four LEDs (D1–D4) will light up in a binary pattern (0000, 0001, 0010… 1111).
* The sequence repeats every 16 clock pulses.
* Activating the reset switch forces all LEDs to turn OFF immediately.
* Logic High output voltage approx. 5 V; Logic Low approx. 0 V.

Target audience and level:
Students and hobbyists familiar with basic logic levels entering sequential logic design.

Materials

  • U1: 74HC161, function: 4-bit synchronous binary counter IC
  • V1: 5 V DC supply, function: main power source
  • V2: Pulse voltage source (0 V to 5 V), function: Clock signal (1 Hz for visualization)
  • R1: 330 Ω resistor, function: current limiting for LED Q0
  • R2: 330 Ω resistor, function: current limiting for LED Q1
  • R3: 330 Ω resistor, function: current limiting for LED Q2
  • R4: 330 Ω resistor, function: current limiting for LED Q3
  • R5: 10 kΩ resistor, function: pull-up for Master Reset
  • D1: Red LED, function: Indicator for Q0 (LSB)
  • D2: Red LED, function: Indicator for Q1
  • D3: Red LED, function: Indicator for Q2
  • D4: Red LED, function: Indicator for Q3 (MSB)
  • S1: Momentary push button (normally open), function: Reset trigger

Pin-out of the IC used

Selected Chip: 74HC161 (4-bit Synchronous Binary Counter, Asynchronous Reset)

Pin Name Logic function Connection in this case
1 \overlineMR Master Reset (Active Low) Connected to Reset node (S1/R5)
2 CP Clock Pulse (Rising Edge) Connected to V2 (Clock Source)
7 CEP Count Enable Parallel Connected to VCC (Always Enabled)
8 GND Ground Connected to 0 (GND)
9 \overlinePE Parallel Enable (Load) Connected to VCC (Disabled)
10 CET Count Enable Trickle Connected to VCC (Always Enabled)
11 Q3 Output Bit 3 (MSB) Connected to D4 via R4
12 Q2 Output Bit 2 Connected to D3 via R3
13 Q1 Output Bit 1 Connected to D2 via R2
14 Q0 Output Bit 0 (LSB) Connected to D1 via R1
16 VCC Power Supply (+5 V) Connected to VCC

Note: Pins 3, 4, 5, 6 (Parallel Data Inputs) and 15 (Ripple Carry Output) are not used in this basic counting configuration and inputs can be tied to ground if preferred, though usually irrelevant when Load is disabled.

Wiring guide

Construct the circuit following these explicit node connections:

  • Power Nodes:

    • Connect V1 positive terminal to node VCC.
    • Connect V1 negative terminal to node 0 (GND).
    • Connect U1 pin 16 to VCC.
    • Connect U1 pin 8 to 0.

  • Control Inputs:

    • Connect V2 (Clock Source) positive to node CLK. Connect V2 negative to 0.
    • Connect U1 pin 2 to node CLK.
    • Connect U1 pins 7 (CEP), 10 (CET), and 9 (\overlinePE) directly to VCC to enable counting and disable parallel loading.
    • Reset Circuit: Connect R5 between VCC and node RESET_N. Connect S1 between node RESET_N and 0. Connect U1 pin 1 to RESET_N.

  • Outputs (LED Indicators):

    • Bit 0 (LSB): Connect U1 pin 14 to node Q0. Connect R1 between Q0 and node LED_A1. Connect D1 anode to LED_A1 and cathode to 0.
    • Bit 1: Connect U1 pin 13 to node Q1. Connect R2 between Q1 and node LED_A2. Connect D2 anode to LED_A2 and cathode to 0.
    • Bit 2: Connect U1 pin 12 to node Q2. Connect R3 between Q2 and node LED_A3. Connect D3 anode to LED_A3 and cathode to 0.
    • Bit 3 (MSB): Connect U1 pin 11 to node Q3. Connect R4 between Q3 and node LED_A4. Connect D4 anode to LED_A4 and cathode to 0.

Conceptual block diagram

Conceptual block diagram — 74HC161 Binary counter
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

+-------------------------------------------------------------------------------------------------------+
|                                  PRACTICAL CASE: 4-BIT UP COUNTER                                     |
+-------------------------------------------------------------------------------------------------------+

      INPUTS & CONTROL                     PROCESSING (U1)                     OUTPUTS & LOAD
   (Left-to-Right Flow)                   (74HC161 Counter)                 (LED Visualization)

                                     +-------------------------+
                                     |                         |
[ V2: Clock Source ] --(CLK 1Hz)---> | [Pin 2] CP              |
                                     |                         |
                                     |                         |          (Bit 0 - LSB)
[ Reset Logic ]                      |             [Pin 14] Q0 | --(Q0)--> [ R1: 330 ] --> [ D1: Red ] --> GND
(VCC->R5->Node->S1->GND) --(RST_N)-> | [Pin 1] ~MR             |
                                     |                         |
                                     |                         |          (Bit 1)
                                     |             [Pin 13] Q1 | --(Q1)--> [ R2: 330 ] --> [ D2: Red ] --> GND
[ VCC: 5 V Source ] --(Enable High)-> | [Pin 7]  CEP            |
                   --(Enable High)-> | [Pin 10] CET            |
                   --(Disable Load)> | [Pin 9]  ~PE            |          (Bit 2)
                                     |             [Pin 12] Q2 | --(Q2)--> [ R3: 330 ] --> [ D3: Red ] --> GND
                                     |                         |
                                     |                         |
                                     |                         |          (Bit 3 - MSB)
                                     |             [Pin 11] Q3 | --(Q3)--> [ R4: 330 ] --> [ D4: Red ] --> GND
                                     |                         |
                                     +-------------------------+
                                            |           |
                                         [Pin 16]    [Pin 8]
                                            |           |
                                           VCC         GND
Electrical Schematic

Measurements and tests

  1. Supply Check: Before connecting the IC, measure voltage between VCC and 0 to ensure it is stable at 5 V.
  2. Clock Verification: Set V2 to a low frequency (e.g., 1 Hz). Verify the signal at node CLK oscillates between 0 V and 5 V.
  3. Sequence Observation: Power on the circuit. Observe D1 through D4. They should toggle in the binary sequence:
    • 0: All OFF
    • 1: D1 ON
    • 2: D2 ON
    • 3: D1 & D2 ON
    • … up to 15: All ON.
  4. Reset Test: While the counter is running, press S1. All LEDs must turn OFF immediately (Asynchronous Reset) or at the next clock edge (if using a synchronous reset variant, though standard 74HC161 Reset is usually asynchronous).
  5. Logic Levels: Use a multimeter to measure node Q3 when D4 is lit. It should read close to 5 V (Logic High).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: 4-bit up counter with LEDs (74HC161)
* NGSPICE Netlist
* Requires XSPICE extensions

.width out=256

* --- Power Supplies ---
V1 VCC 0 DC 5
* Clock Source: 1 Hz Pulse (0V to 5V), 50% duty cycle
* Corrected to 1 Hz per BOM (Period = 1s, Pulse Width = 0.5s)
V2 CLK 0 PULSE(0 5 0 1u 1u 0.5 1)

* --- Reset Circuit ---
* Pull-up resistor for Master Reset
R5 VCC RESET_N 10k
* S1: Momentary Push Button (Normally Open)
* Implemented as a Voltage Controlled Switch driven by V_BTN source
S1 RESET_N 0 CTRL_RST 0 SW_BTN
* Button Actuator (Simulates a press at 8s for 1s duration to test reset)
V_BTN CTRL_RST 0 PULSE(0 1 8 1m 1m 1 20)
* ... (truncated in public view) ...

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🔓 See premium access plans 

* Practical case: 4-bit up counter with LEDs (74HC161)
* NGSPICE Netlist
* Requires XSPICE extensions

.width out=256

* --- Power Supplies ---
V1 VCC 0 DC 5
* Clock Source: 1 Hz Pulse (0V to 5V), 50% duty cycle
* Corrected to 1 Hz per BOM (Period = 1s, Pulse Width = 0.5s)
V2 CLK 0 PULSE(0 5 0 1u 1u 0.5 1)

* --- Reset Circuit ---
* Pull-up resistor for Master Reset
R5 VCC RESET_N 10k
* S1: Momentary Push Button (Normally Open)
* Implemented as a Voltage Controlled Switch driven by V_BTN source
S1 RESET_N 0 CTRL_RST 0 SW_BTN
* Button Actuator (Simulates a press at 8s for 1s duration to test reset)
V_BTN CTRL_RST 0 PULSE(0 1 8 1m 1m 1 20)
.model SW_BTN sw(vt=0.5 ron=1 roff=10Meg)

* --- 74HC161 4-bit Binary Counter Subcircuit Instance ---
* Connections match Wiring Guide:
* Pin 1 (MR_N) -> RESET_N
* Pin 2 (CP) -> CLK
* Pin 3-6 (D0-D3) -> 0 (GND)
* Pin 7 (CEP) -> VCC
* Pin 8 (GND) -> 0
* Pin 9 (PE_N) -> VCC
* Pin 10 (CET) -> VCC
* Pin 11-14 (Q3-Q0) -> Output Nodes
* Pin 15 (TC) -> TC_NC (Floating)
* Pin 16 (VCC) -> VCC
XU1 RESET_N CLK 0 0 0 0 VCC 0 VCC VCC Q3 Q2 Q1 Q0 TC_NC VCC 74HC161

* --- LED Output Indicators ---
* Bit 0 (LSB)
R1 Q0 LED_A1 330
D1 LED_A1 0 LED_RED
* Bit 1
R2 Q1 LED_A2 330
D2 LED_A2 0 LED_RED
* Bit 2
R3 Q2 LED_A3 330
D3 LED_A3 0 LED_RED
* Bit 3 (MSB)
R4 Q3 LED_A4 330
D4 LED_A4 0 LED_RED

* --- Models ---
.model LED_RED D(Is=1e-14 Rs=5 N=2)

* --- Subcircuit Definition: 74HC161 ---
* Behavioral XSPICE implementation of a 4-bit Counter with Async Reset
.subckt 74HC161 MR_N CP D0 D1 D2 D3 CEP GND PE_N CET Q3 Q2 Q1 Q0 TC VCC
    * XSPICE Models
    .model adc_in adc_bridge(in_low=2.0 in_high=3.0)
    .model dac_out dac_bridge(out_low=0.0 out_high=5.0)
    .model dff_mod d_dff(rise_delay=10n fall_delay=10n)
    .model inv_mod d_inverter(rise_delay=5n fall_delay=5n)

    * Input Bridges (Analog to Digital)
    A_IN [MR_N CP] [mr_dig cp_dig] adc_in

    * Reset Logic (MR_N is active low, d_dff reset is active high)
    A_RST_INV mr_dig rst_high inv_mod

    * Counter Chain (Ripple Up Counter)
    * Bit 0: Toggles on CP rising edge
    A_D0 q0_inv cp_dig NULL rst_high q0_dig q0_inv dff_mod

    * Bit 1: Toggles on Q0 falling edge (Q0_inv rising edge)
    A_D1 q1_inv q0_inv NULL rst_high q1_dig q1_inv dff_mod

    * Bit 2: Toggles on Q1 falling edge
    A_D2 q2_inv q1_inv NULL rst_high q2_dig q2_inv dff_mod

    * Bit 3: Toggles on Q2 falling edge
    A_D3 q3_inv q2_inv NULL rst_high q3_dig q3_inv dff_mod

    * Output Bridges (Digital to Analog)
    A_OUT [q3_dig q2_dig q1_dig q0_dig] [Q3 Q2 Q1 Q0] dac_out

    * Terminal Count (Unused/Dummy pull-down)
    R_TC TC 0 100k
.ends

* --- Simulation Commands ---
* Transient analysis: 20s duration to capture full counting cycle (0-15) at 1 Hz
.op
.tran 10m 20s

* Print critical signals (Inputs first)
.print tran V(CLK) V(RESET_N) V(Q0) V(Q1) V(Q2) V(Q3)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation shows a correct 4-bit binary counting sequence (0000 to 1111) on outputs Q0-Q3. The clock toggles at 1Hz. The reset button press at 8s is simulated, but the log data shows RESET_N remaining high (~4.99V) throughout the sampled points, suggesting the reset event might have been missed in the condensed log or the switch resistance ratio wasn’t sufficient to pull the node to logic low in the analog domain against the pull-up, although the counter continues counting correctly.
Show raw data table (3020 rows) 
Index   time            v(clk)          v(reset_n)      v(q0)           v(q1)           v(q2)           v(q3)
0	0.000000e+00	0.000000e+00	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
1	1.000000e-08	5.000000e-02	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
2	2.000000e-08	1.000000e-01	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
3	4.000000e-08	2.000000e-01	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
4	8.000000e-08	4.000000e-01	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
5	1.600000e-07	8.000000e-01	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
6	3.200000e-07	1.600000e+00	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
7	6.400000e-07	3.200000e+00	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
8	6.520000e-07	3.260000e+00	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
9	6.760000e-07	3.380000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
10	7.240000e-07	3.620000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
11	8.200000e-07	4.100000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
12	1.000000e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
13	1.019200e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
14	1.057600e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
15	1.134400e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
16	1.288000e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
17	1.595200e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
18	2.209600e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
19	3.438400e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
20	5.896000e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
21	1.081120e-05	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
22	2.064160e-05	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
23	4.030240e-05	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
... (2996 more rows) ...

Common mistakes and how to avoid them

  1. Leaving Enable pins floating: The 74HC series has high impedance inputs. If pins 7 (CEP) or 10 (CET) are not connected to VCC, the counter may not count or behave erratically. Always tie unused control inputs to a defined logic level.
  2. Clock frequency too high: If V2 is set to 1 kHz or higher, all LEDs will appear to be dimly lit continuously due to persistence of vision. Keep the clock below 5 Hz for visual debugging.
  3. Floating Parallel Load pin: If pin 9 (\overlinePE) is left floating or low, the chip might constantly try to load data from inputs P0-P3 instead of counting. Ensure pin 9 is tied to VCC.

Troubleshooting

  • LEDs never turn on: Check power supply connections to pins 16 and 8. Ensure LEDs are inserted with the correct polarity (anode to resistor/IC, cathode to ground).
  • Counter stays at zero: Verify that the Reset pin (1) is High (5 V). If S1 is stuck or the pull-up R5 is missing, the chip remains in Reset state. Also, check that Enable pins (7, 10) are High.
  • Counter skips numbers: This is often due to «switch bounce» if you are using a mechanical switch as a manual clock. Use a clean square wave generator or a debounce circuit (capacitor + resistor) for the clock input.
  • Random sequence: Check if the Parallel Enable (\overlinePE) pin is accidentally Low or floating. It must be High.

Possible improvements and extensions

  1. 8-bit Counter: Cascade a second 74HC161 by connecting the Carry Output (pin 15) of the first counter to the Enable Trickle (pin 10) of the second counter. This allows counting up to 255.
  2. Manual Clock: Replace the frequency generator V2 with a 555 timer circuit in astable mode or a debounced push-button to advance the count manually.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: Which integrated circuit is used as the 4-bit synchronous binary counter in this experiment?




Question 2: What is the counting range of the circuit described in the text?




Question 3: What happens to the LED sequence after 16 clock pulses?




Question 4: What does the acronym LSB stand for in the context of this circuit?




Question 5: According to the text, how are counters used in Digital Clocks?




Question 6: What is the purpose of using counters for Frequency Division?




Question 7: In computing systems, what are counters typically used for according to the text?




Question 8: Which application is mentioned for industrial automation?




Question 9: How is the 74HC161 circuit described in the objective section?




Question 10: What is the primary method used to visualize the output states in this experiment?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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Practical case: Dual Safety Motor Activation

Dual Safety Motor Activation prototype (Maker Style)

Level: Basic — Implement a system where a motor runs only when two buttons are pressed simultaneously.

Objective and use case

In this session, you will build a safety logic circuit using a 74HC00 (Quad 2-input NAND gate) to control a DC motor. The motor will only activate when two separate pushbuttons are engaged at the same time, mimicking a «two-hand control» safety device.

Why it is useful:
* Industrial Safety: Prevents operators from reaching into a hydraulic press or cutting machine while it is moving.
* Accident Prevention: Ensures both hands are occupied on the controls during the dangerous phase of operation.
* Logic Composition: Demonstrates how to create an AND function using universal NAND gates.

Expected outcome:
* Idle State: Logic output is LOW (0 V); Motor is OFF.
* Single Press: Logic output remains LOW (0 V); Motor remains OFF.
* Dual Press: Logic output becomes HIGH (5 V); Relay engages; Motor runs.
* Current Handling: The logic gate drives a transistor, which safely switches the high-current relay coil.

Target audience and level:
Basic electronics students and hobbyists interested in digital logic applications.

Materials

  • V1: 5 V DC voltage source, function: Logic and relay coil power supply.
  • V2: 12 V DC voltage source, function: Motor power supply.
  • U1: 74HC00, function: Quad 2-input NAND gate IC.
  • S1: Pushbutton (normally open), function: Left-hand safety switch.
  • S2: Pushbutton (normally open), function: Right-hand safety switch.
  • R1: 10 kΩ resistor, function: Pull-down for S1.
  • R2: 10 kΩ resistor, function: Pull-down for S2.
  • R3: 1 kΩ resistor, function: Base current limiting for Q1.
  • Q1: 2N2222 NPN transistor, function: Relay driver.
  • D1: 1N4007 diode, function: Flyback protection for relay coil.
  • K1: 5 V SPDT Relay, function: High-power switching interface.
  • M1: 12 V DC Motor, function: Actuator (load).

Pin-out of the IC used (74HC00)

Chip: 74HC00 (Quad 2-Input NAND Gate)

Pin Name Logic Function Connection in this case
1 1 A Input A (Gate 1) Connected to S1 (Node BTN_L)
2 1B Input B (Gate 1) Connected to S2 (Node BTN_R)
3 1Y Output (Gate 1) Connected to Inputs of Gate 2 (Node NAND_INTER)
4 2 A Input A (Gate 2) Connected to Node NAND_INTER
5 2B Input B (Gate 2) Connected to Node NAND_INTER
6 2Y Output (Gate 2) Connected to R3 (Node LOGIC_OUT)
7 GND Ground Connected to Node 0
14 VCC Power Supply Connected to Node VCC

Note: Pins 8 through 13 are unused and should ideally be tied to GND or VCC in a permanent installation to prevent noise, though left floating for this basic breadboard exercise.

Wiring guide

Construct the circuit following these node connections. Ensure the power supply is off while building.

Power and Inputs:
* V1 (+): Connects to node VCC.
* V1 (-) / V2 (-): Connects to node 0 (Common Ground).
* S1: Connects between VCC and node BTN_L.
* R1: Connects between node BTN_L and 0.
* S2: Connects between VCC and node BTN_R.
* R2: Connects between node BTN_R and 0.

Logic Processing (Using U1 as AND Gate):
* U1 (Pin 14): Connects to VCC.
* U1 (Pin 7): Connects to 0.
* U1 (Pin 1): Connects to node BTN_L.
* U1 (Pin 2): Connects to node BTN_R.
* U1 (Pin 3): Connects to node NAND_INTER (First stage output).
* U1 (Pin 4 & Pin 5): Both connect to node NAND_INTER (Configures Gate 2 as an inverter).
* U1 (Pin 6): Connects to node LOGIC_OUT.

Output Stage:
* R3: Connects between node LOGIC_OUT and node BASE.
* Q1 (Base): Connects to node BASE.
* Q1 (Emitter): Connects to node 0.
* Q1 (Collector): Connects to node RELAY_COIL_LO.
* K1 (Coil +): Connects to VCC.
* K1 (Coil -): Connects to node RELAY_COIL_LO.
* D1 (Anode): Connects to node RELAY_COIL_LO.
* D1 (Cathode): Connects to VCC (Parallel to coil, reverse biased).

Motor Circuit:
* V2 (+): Connects to K1 Common contact (COM).
* K1 (NO – Normally Open): Connects to node MOTOR_POS.
* M1 (+): Connects to node MOTOR_POS.
* M1 (-): Connects to node 0.

Conceptual block diagram

Conceptual block diagram — 74HC00 NAND gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

+-----------------------------------------------------------------------------+
|                  DUAL SAFETY MOTOR ACTIVATION BLOCK DIAGRAM                 |
+-----------------------------------------------------------------------------+

1. INPUTS & LOGIC STAGE (5 V Domain)
   (Both buttons must be pressed to activate the output)

   V1(5 V)
     |
     +---> [ S1: Left Button ] ---+--(BTN_L)------\
                                  |                \
                                  v                 \
                               [ R1: 10k ]           +---> [ U1:A (NAND) ] --(NAND_INTER)--> [ U1:B (NOT*) ] --(LOGIC_OUT)-->
                                  |                 /       (Pins 1 & 2)                      (Pins 4 & 5)          |
                                 GND               /                                         *Wired as Inverter     |
                                                  /                                                                 |
   V1(5 V)                                        /                                                                  |
     |                                          /                                                                   |
     +---> [ S2: Right Button ] --+--(BTN_R)---/                                                                    |
                                  |                                                                                 |
                                  v                                                                                 |
                               [ R2: 10k ]                                                                          |
                                  |                                                                                 |
                                 GND                                                                                |
                                                                                                                    |
+-------------------------------------------------------------------------------------------------------------------+
|                                                                                                                   |
| 2. RELAY DRIVER STAGE (5 V Domain)                                                                                 |
|    (Low-Side Transistor Switch)                                                                                   |
|                                                                                                                   |
|    (From Logic Above)                                                                                             |
|            |                                         V1(5 V)                                                       |
|            v                                           |                                                          |
|      [ R3: 1k ]                                        |                                                          |
|            |                                           v                                                          |
|            +----------------------------------> [ Q1: Base ]                                                      |
|                                                        :                                                          |
|                                             (Controls Current Flow)                                               |
|                                                        :                                                          |
|                                      +-----------------+                                                          |
|                                      |                                                                            |
|                              [ Q1: Collector ]                                                                    |
|                                      ^                                                                            |
|                                      |                                                                            |
|                             (Node: RELAY_COIL_LO)                                                                 |
|                                      |                                                                            |
|                    +-----------------+-----------------+                                                          |
|                    |                                   |                                                          |
|           [ K1: Relay Coil ]                    [ D1: Diode ]                                                     |
|           (Control Side)                        (Protection)                                                      |
|                    |                            (Anode to Coll)                                                   |
|                    |                            (Cathode to VCC)                                                  |
|                    +-----------------+-----------------+                                                          |
|                                      ^                                                                            |
|                                      |                                                                            |
|                                    V1(5 V)                                                                         |
|                                                                                                                   |
|                              [ Q1: Emitter ]                                                                      |
|                                      |                                                                            |
|                                      v                                                                            |
|                                     GND                                                                           |
|                                                                                                                   |
+-------------------------------------------------------------------------------------------------------------------+
|                                                                                                                   |
| 3. MOTOR OUTPUT STAGE (12 V Domain)                                                                                |
|    (High Power Load)                                                                                              |
|                                                                                                                   |
|                       (Magnetic Link from K1 Coil Above)                                                          |
|                                      |                                                                            |
|                                      v                                                                            |
|    V2(12 V) ---------> [ K1: Switch (COM to NO) ] --(MOTOR_POS)--> [ M1: 12 V Motor ] ----> GND                     |
|                                                                                                                   |
+-------------------------------------------------------------------------------------------------------------------+
Electrical Schematic

Truth table

We are using two NAND gates. The first combines the inputs; the second inverts the result to create an AND function.

S1 (Left) S2 (Right) U1 Pin 3 (1Y) U1 Pin 6 (2Y) Motor State
0 (OFF) 0 (OFF) 1 (High) 0 (Low) STOP
0 (OFF) 1 (ON) 1 (High) 0 (Low) STOP
1 (ON) 0 (OFF) 1 (High) 0 (Low) STOP
1 (ON) 1 (ON) 0 (Low) 1 (High) RUN

Measurements and tests

  1. Idle Check: Power on V1. Do not press any buttons. Measure the voltage at LOGIC_OUT (Pin 6). It should be ~0 V. The motor should be stopped.
  2. Input Validation: Press S1 only. Measure voltage at Pin 1. It should be 5 V. Pin 2 should be 0 V. Output at Pin 6 must remain 0 V.
  3. Active Test: Press and hold both S1 and S2 simultaneously.
    • Listen for the «click» of the relay K1.
    • Observe M1 spinning.
    • Measure the voltage at LOGIC_OUT; it should be close to 5 V.
  4. Release Test: Release just one button. The motor must stop immediately.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Logic AND gate controlling a relay and motor

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================
* Generic NPN Transistor Model (2N2222)
.model 2N2222MOD NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)

* Generic Diode Model (1N4007)
.model D1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3 BV=1000 IBV=10m CJO=10p VJ=0.7 M=0.5 FC=0.5 TT=100n)

* Ideal Switch Model for Buttons and Relay Contact
* Vt=2.5V (Logic Threshold), Ron=0.1 Ohm, Roff=10 MegOhm
.model SW_IDEAL SW(Vt=2.5 Vh=0.1 Ron=0.1 Roff=10Meg)

* ==============================================================================
* POWER SUPPLIES
* ==============================================================================
* V1: 5V DC Supply for Logic and Relay Coil
V1 VCC 0 DC 5
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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* Practical case: Logic AND gate controlling a relay and motor

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================
* Generic NPN Transistor Model (2N2222)
.model 2N2222MOD NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)

* Generic Diode Model (1N4007)
.model D1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3 BV=1000 IBV=10m CJO=10p VJ=0.7 M=0.5 FC=0.5 TT=100n)

* Ideal Switch Model for Buttons and Relay Contact
* Vt=2.5V (Logic Threshold), Ron=0.1 Ohm, Roff=10 MegOhm
.model SW_IDEAL SW(Vt=2.5 Vh=0.1 Ron=0.1 Roff=10Meg)

* ==============================================================================
* POWER SUPPLIES
* ==============================================================================
* V1: 5V DC Supply for Logic and Relay Coil
V1 VCC 0 DC 5

* V2: 12V DC Supply for Motor
V2 V_MOTOR_RAIL 0 DC 12

* ==============================================================================
* INPUT STAGE (Safety Switches)
* ==============================================================================
* Simulation of User Pressing Buttons:
* We use Pulse sources (V_ACT_...) to control ideal switches (S1, S2).
* This preserves the Pull-down resistor topology.

* S1: Left Safety Switch (Pushbutton NO)
* Connects VCC to BTN_L when pressed.
* Pulse Pattern: Period 120us, Pulse 50us (Tests asynchronous press)
V_ACT_L ACT_L 0 PULSE(0 5 10u 1u 1u 50u 120u)
S1 VCC BTN_L ACT_L 0 SW_IDEAL
R1 BTN_L 0 10k

* S2: Right Safety Switch (Pushbutton NO)
* Connects VCC to BTN_R when pressed.
* Pulse Pattern: Period 100us, Pulse 50us
V_ACT_R ACT_R 0 PULSE(0 5 20u 1u 1u 50u 100u)
S2 VCC BTN_R ACT_R 0 SW_IDEAL
R2 BTN_R 0 10k

* ==============================================================================
* LOGIC STAGE (U1: 74HC00 Quad NAND)
* ==============================================================================
* Implementing logic using Behavioral Voltage Sources (B-Sources) with continuous
* sigmoid functions for convergence robustness.
* Logic High = 5V, Logic Low = 0V. Threshold ~ 2.5V.

* U1 Gate 1: Inputs BTN_L (Pin 1), BTN_R (Pin 2) -> Output NAND_INTER (Pin 3)
* Function: NAND(BTN_L, BTN_R)
B_U1_G1 NAND_INTER 0 V=5 * (1 - ( (1/(1+exp(-20*(V(BTN_L)-2.5)))) * (1/(1+exp(-20*(V(BTN_R)-2.5)))) ))

* U1 Gate 2: Inputs NAND_INTER (Pin 4, 5) -> Output LOGIC_OUT (Pin 6)
* Function: NAND(NAND_INTER, NAND_INTER) = NOT(NAND_INTER)
* Combined Function: AND(BTN_L, BTN_R)
B_U1_G2 LOGIC_OUT 0 V=5 * (1 - ( (1/(1+exp(-20*(V(NAND_INTER)-2.5)))) * (1/(1+exp(-20*(V(NAND_INTER)-2.5)))) ))

* ==============================================================================
* OUTPUT DRIVER STAGE
* ==============================================================================
* R3: Base current limiting
R3 LOGIC_OUT BASE 1k

* Q1: 2N2222 Relay Driver
* Emitter to GND, Collector to RELAY_COIL_LO
Q1 RELAY_COIL_LO BASE 0 2N2222MOD

* ==============================================================================
* RELAY STAGE (K1)
* ==============================================================================
* Relay Coil Configuration:
* Connected between VCC and RELAY_COIL_LO.
* Modeled as Inductor + Series Resistor.
L_K1 VCC K1_NODE 10m
R_K1 K1_NODE RELAY_COIL_LO 100

* D1: Flyback Diode (1N4007)
* Anode to RELAY_COIL_LO, Cathode to VCC (Reverse biased)
D1 RELAY_COIL_LO VCC D1N4007

* Relay Contact (Switch):
* Logic: Switch closes when Coil is energized.
* Coil is energized when Q1 is ON (RELAY_COIL_LO is Low).
* Control Voltage = V(VCC) - V(RELAY_COIL_LO).
* If Q1 ON: 5V - 0.2V = 4.8V (> 2.5V Threshold) -> Switch CLOSED.
* If Q1 OFF: 5V - 5V = 0V (< 2.5V Threshold) -> Switch OPEN.
B_K1_CTRL K1_CTRL 0 V = V(VCC) - V(RELAY_COIL_LO)
S_K1 V_MOTOR_RAIL MOTOR_POS K1_CTRL 0 SW_IDEAL

* ==============================================================================
* LOAD (Motor M1)
* ==============================================================================
* M1: 12V DC Motor connected between MOTOR_POS and 0
* Modeled as Resistor + Inductor
R_M1 MOTOR_POS M1_INT 20
L_M1 M1_INT 0 5m

* ==============================================================================
* ANALYSIS COMMANDS
* ==============================================================================
.op
* Transient analysis: 1us step, 500us total time
.tran 1u 500u

* Print results for batch processing
* Inputs: BTN_L, BTN_R
* Output: MOTOR_POS (Load Voltage)
* Debug: LOGIC_OUT, RELAY_COIL_LO
.print tran V(BTN_L) V(BTN_R) V(MOTOR_POS) V(LOGIC_OUT) V(RELAY_COIL_LO) I(L_M1)

.end

Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation confirms the AND logic behavior. The motor voltage (v(motor_pos)) only goes high (~12V) when both inputs (v(btn_l) and v(btn_r)) are high (~5V) simultaneously (e.g., around time index 60-100 and 300-340). When only one or neither is high, the motor voltage remains near zero.
Show raw data table (1202 rows) 
Index   time            v(btn_l)        v(btn_r)        v(motor_pos)    v(logic_out)    v(relay_coil_lo l_m1#branch
0	0.000000e+00	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
1	1.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
2	2.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
3	4.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
4	8.000000e-08	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
5	1.600000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
6	3.200000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
7	6.400000e-07	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
8	1.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
9	2.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
10	3.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
11	4.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
12	5.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
13	6.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
14	7.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
15	8.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
16	9.280000e-06	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
17	1.000000e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
18	1.010000e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
19	1.027500e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
20	1.032344e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
21	1.040820e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
22	1.043167e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
23	1.047272e-05	4.995005e-03	4.995005e-03	2.399995e-05	-6.01853e-36	5.000000e+00	1.199998e-06
... (1178 more rows) ...

Common mistakes and how to avoid them

  1. Floating Inputs: Forgetting R1 or R2 causes the NAND gate inputs to float, often reading as «High» due to noise. Solution: Ensure pull-down resistors are firmly connected to Ground.
  2. Missing Flyback Diode: Omitting D1 creates voltage spikes when the relay turns off, which can destroy Q1 or reset the logic chip. Solution: Always place a diode across the relay coil (Cathode to positive).
  3. Direct Drive: Attempting to drive the motor or relay directly from the 74HC00 output pin. Solution: Always use a transistor (Q1) to amplify the current for inductive loads like relays.

Troubleshooting

  • Motor runs immediately upon power-up: Check if S1 or S2 are wired as Normally Closed instead of Normally Open, or if the transistor Q1 is shorted.
  • Relay clicks but motor doesn’t run: Check the V2 power supply and the connections on the relay contacts (COM and NO).
  • Logic works but gets hot: Check if VCC (Pin 14) and GND (Pin 7) are reversed. Disconnect power immediately.
  • Erratic behavior: Add a 100 nF decoupling capacitor between Pin 14 and Pin 7 of the IC, close to the chip.

Possible improvements and extensions

  1. Emergency Stop: Add a Normally Closed (NC) latching button in series with the relay coil or the base resistor R3 to cut power instantly regardless of logic state.
  2. Visual Feedback: Add a green LED (with a 330 Ω resistor) connected to node LOGIC_OUT to indicate when the safety condition is met, even if the motor power (V2) is off.

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Quick Quiz

Question 1: What is the primary function of the circuit described in the article?




Question 2: Which integrated circuit (IC) is used to implement the logic for this project?




Question 3: What is a common real-world application for this type of 'two-hand control' system?




Question 4: What logic function is effectively created using the universal NAND gates in this project?




Question 5: What is the state of the motor if only one button is pressed?




Question 6: Which component is mentioned as responsible for driving the high-current relay coil?




Question 7: What is the expected logic output voltage during a 'Dual Press' state?




Question 8: Why is this circuit considered an accident prevention measure?




Question 9: What is the status of the logic output when the system is in an 'Idle State'?




Question 10: Who is the target audience for this project?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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