Objective and use case

In this practical case, you will build a digital equality detector using a 74HC7266 XNOR logic gate, mechanical switches, and an LED indicator.

This circuit concept is highly useful in real-world digital electronics:
* Digital locks: Comparing an entered bit to a stored security key bit.
* Error detection: Verifying if two redundant sensor signals output the exact same digital state.
* Data routing: Confirming destination addresses in memory mapping or basic communication protocols.
* Automation: Checking if a machine’s actual state matches the commanded state.

Expected outcome:
* The output LED turns ON when both inputs are perfectly equal (both LOW or both HIGH).
* The output LED remains OFF when the inputs differ (one is HIGH and the other is LOW).
* Logic LOW is measured as approximately 0 V, and logic HIGH as approximately 5 V.

Target audience: Beginners learning fundamental digital logic gates and Boolean algebra.

Materials

• V1: 5 V DC power supply, function: circuit power
• SW1: SPST switch, function: input A control
• SW2: SPST switch, function: input B control
• R1: 10 kΩ resistor, function: pull-down for node VA
• R2: 10 kΩ resistor, function: pull-down for node VB
• R3: 330 Ω resistor, function: LED current limiting
• D1: red LED, function: equality indicator
• U1: 74HC7266 IC, function: XNOR logic gate

Wiring guide

• V1: connects between node VCC and node 0 (GND).
• SW1: connects between node VCC and node VA.
• R1: connects between node VA and node 0.
• SW2: connects between node VCC and node VB.
• R2: connects between node VB and node 0.
• U1: VCC pin (14) connects to node VCC.
• U1: GND pin (7) connects to node 0.
• U1: Pin 1 (1 A) connects to node VA.
• U1: Pin 2 (1B) connects to node VB.
• U1: Pin 3 (1Y) connects to node VOUT.
• U1: Pins 5, 6, 8, 9, 12, and 13 connect directly to node 0.
• R3: connects between node VOUT and node D1_ANODE.
• D1: anode connects to node D1_ANODE, cathode connects to node 0.

Conceptual block diagram

Measurements and tests

1. Initial Power Verification: Before actuating any switches, power on the circuit. Measure the voltage between VCC and 0 to ensure it is 5 V.
2. Input State Testing: Set your multimeter to DC Voltage. Measure nodes VA and VB with respect to node 0. Toggle SW1 and SW2 to verify that an open switch yields ~0 V (thanks to the pull-down resistors) and a closed switch yields ~5 V.
3. XNOR Logic Verification: Measure the voltage at VOUT with respect to node 0 for all four combinations of SW1 and SW2.
4. Equality Confirmation: Ensure VOUT is approximately 5 V and the LED is illuminated ONLY when VA and VB are perfectly matched (0 V & 0 V, or 5 V & 5 V).

Common mistakes and how to avoid them

• Confusing 74HC7266 with 74HC266: The 74HC266 has open-drain outputs, which means it cannot source current to turn on an LED without an external pull-up resistor. Ensure you use the 74HC7266 (push-pull) or add a pull-up resistor if using the 74HC266.
• Leaving CMOS inputs floating: Forgetting to ground the unused inputs of the 74HC7266 can cause internal high-frequency oscillation, drawing excessive current and potentially damaging the IC. Always tie unused inputs to GND or VCC.
• Omitting pull-down resistors: If R1 and R2 are forgotten, the inputs will float unpredictably when the switches are open, causing the LED to flicker randomly.

Troubleshooting

• Symptom: LED flickers or behaves erratically when switches are open.
  • Cause: Node VA or VB is floating.
  • Fix: Verify that R1 and R2 are securely connected between the switch inputs and ground.
• Symptom: LED never turns on.
  • Cause: LED D1 is inserted backwards (reversed polarity) or R3 is too large (e.g., 100 kΩ instead of 330 Ω).
  • Fix: Check the orientation of D1 (longer leg to D1_ANODE) and verify the value of R3.
• Symptom: LED is always ON regardless of switch positions.
  • Cause: Output pin (3) is shorted to VCC, or both switches are permanently shorted to the same logic level.
  • Fix: Inspect the wiring around VOUT, VA, and VB. Ensure the switches physically break the connection to VCC when toggled off.

Objective and use case

You will build a digital logic comparator circuit using a 74LS86 XOR (Exclusive-OR) gate to monitor two redundant switches acting as system sensors. The circuit evaluates the inputs continuously and activates a visual LED alarm only when the two sensors report conflicting states, indicating a potential sensor failure.

This circuit is highly useful in practical scenarios such as:
* Industrial automation, for monitoring dual-redundant safety limit switches on heavy machinery.
* Aerospace and aviation control systems, to detect disagreements between redundant flight sensors.
* Basic logic fault-detection training for maintenance and electronics technicians.

Expected outcome:
* A high output logic level (VOUT > 2.4 V) triggering the LED when the sensor states do not match.
* A low output logic level (VOUT < 0.4 V) keeping the LED turned off when both sensors agree (both HIGH or both LOW).
* A clear, immediate visual indication of logic discrepancies to the operator.

Target audience: Basic-level students learning digital logic gates, boolean algebra, and redundancy systems.

Materials

• V1: 5 V DC supply, function: primary power source
• SW1: SPST switch, function: redundant sensor A simulator
• SW2: SPST switch, function: redundant sensor B simulator
• R1: 10 kΩ resistor, function: pull-down for VA
• R2: 10 kΩ resistor, function: pull-down for VB
• R3: 330 Ω resistor, function: LED current limiting
• U1: 74LS86 Quad 2-Input Exclusive-OR Gate, function: fault detection logic
• D1: red LED, function: visual fault alarm indicator

Wiring guide

• V1: connects between VCC and 0.
• SW1: connects between VCC and VA.
• SW2: connects between VCC and VB.
• R1: connects between VA and 0.
• R2: connects between VB and 0.
• U1: connects Pin 14 to VCC, Pin 7 to 0, Pin 1 to VA, Pin 2 to VB, and Pin 3 to VOUT.
• R3: connects between VOUT and VLED.
• D1: connects its anode to VLED and its cathode to 0.

Conceptual block diagram

Measurements and tests

1. System Normal (Low): Leave both SW1 and SW2 open. Measure the voltage at nodes VA and VB with a multimeter; both should read 0 V. Measure VOUT; it should be < 0.4 V. The LED D1 must be OFF.
2. Sensor A Fault: Close SW1 (applying 5 V to VA) while leaving SW2 open (0 V at VB). Measure VOUT; it should read > 2.4 V. The LED D1 must turn ON.
3. Sensor B Fault: Open SW1 (0 V at VA) and close SW2 (applying 5 V to VB). Measure VOUT; it should read > 2.4 V. The LED D1 must turn ON.
4. System Normal (High): Close both SW1 and SW2 so that both VA and VB read 5 V. Measure VOUT; it should drop back to < 0.4 V. The LED D1 must be OFF.

Common mistakes and how to avoid them

• Forgetting pull-down resistors: Connecting the switches directly to the IC without R1 and R2 leaves the inputs floating when the switches are open, causing unpredictable behavior and false alarms. Always use pull-down resistors.
• LED polarity reversal: Putting the LED in backward (cathode to VLED, anode to 0) will prevent it from lighting up even when a fault is detected. Verify the flat edge or shorter leg is connected to ground.
• Leaving unused inputs floating: The 74LS86 contains four XOR gates. Leaving the inputs of the unused gates disconnected can cause internal oscillation and increase power consumption. Tie unused inputs to ground (0).

Troubleshooting

• Symptom: The LED never turns on under any switch combination.
  • Cause: Faulty LED, backward LED polarity, broken R3 connection, or missing VCC/GND to the chip.
  • Fix: Check D1 orientation. Verify 5 V at Pin 14 and 0 V at Pin 7 of U1.
• Symptom: The LED is always on, even when both switches are open or both are closed.
  • Cause: One of the inputs is floating (missing pull-down resistor R1 or R2), or a switch is wired incorrectly.
  • Fix: Check continuity on R1 and R2 to ground. Verify the voltages at VA and VB correspond strictly to the truth table.
• Symptom: The LED lights up correctly but is very dim.
  • Cause: The 74LS series has weak current sourcing capabilities compared to modern CMOS chips, or the value of R3 is too high.
  • Fix: Reduce R3 slightly (e.g., to 220 Ω), or see the extensions below for a better way to drive the LED.

Objective and use case

We will build a simple security alarm simulator using a 74HC02 NOR gate. In this system, the alarm (an LED) will illuminate only when all connected monitoring sensors (represented by switches) indicate a safe, undisturbed state (Logic 0).

Why it is useful:
* Demonstrates negative logic applications where the absence of inputs is required to trigger an action.
* Provides practical experience with CMOS logic gate behavior and logic-level thresholds.
* Mimics real-world safety interlocks, such as machine guards, where multiple conditions must be false for the system to operate.
* Introduces the essential use of pull-down resistors to ensure stable, predictable logic states.

Expected outcome:
* The output LED will illuminate only when both sensor switches are open (Logic 0, 0 V).
* The output LED will turn off immediately if either or both switches are closed (Logic 1, 5 V).
* Input voltages will measure close to 0 V when switches are open, and near 5 V when closed.
* The output voltage will strictly follow the theoretical truth table of a NOR logic gate.

Target audience: Beginners in digital electronics learning fundamental logic gates and basic control circuits.

Materials

• V1: 5 V DC power supply
• U1: 74HC02 Quad 2-Input NOR Gate
• SW1: SPST switch, function: sensor A input
• SW2: SPST switch, function: sensor B input
• R1: 10 kΩ resistor, function: pull-down for VA
• R2: 10 kΩ resistor, function: pull-down for VB
• R3: 330 Ω resistor, function: LED current limiting
• D1: Red LED, function: alarm active indicator

Wiring guide

• V1: Connects between VCC and 0.
• U1 (Pin 14): Connects to VCC.
• U1 (Pin 7): Connects to 0.
• SW1: Connects between VCC and VA.
• SW2: Connects between VCC and VB.
• R1: Connects between VA and 0.
• R2: Connects between VB and 0.
• U1 (Pin 2): Connects to VA.
• U1 (Pin 3): Connects to VB.
• U1 (Pin 1): Connects to VOUT.
• R3: Connects between VOUT and D1_A.
• D1: Connects between D1_A (anode) and 0 (cathode).

Conceptual block diagram

Measurements and tests

1. Power verification: With the power supply connected, use a multimeter to measure the voltage between nodes VCC and 0. Ensure it is strictly 5 V.
2. Idle state test (0, 0): Leave both SW1 and SW2 open. Measure nodes VA and VB with respect to ground; they should be 0 V. Measure VOUT; it should read near 5 V, and the LED should be ON.
3. Single sensor test (1, 0 / 0, 1): Close SW1 (leaving SW2 open). Measure VA; it should be 5 V. Measure VOUT; it should immediately drop to 0 V, and the LED should turn OFF. Repeat by opening SW1 and closing SW2.
4. Dual sensor test (1, 1): Close both SW1 and SW2. Confirm both VA and VB measure 5 V. Measure VOUT to verify it remains 0 V (LED OFF).

Common mistakes and how to avoid them

1. Misinterpreting the 74HC02 pinout: Unlike standard AND/OR gates (where pins 1 and 2 are inputs and 3 is the output), the 74HC02 has its output on Pin 1, and inputs on Pins 2 and 3. Wiring it like a 74HC08 will result in short circuits and component failure.
2. Floating inputs (Missing pull-down resistors): Omitting R1 or R2 leaves the CMOS inputs floating when the switches are open. This causes the output to oscillate or randomly toggle based on environmental electromagnetic noise. Always ensure your inputs have a defined path to ground.
3. Reversing LED polarity: Connecting the LED backwards (anode to ground) will prevent it from lighting up, even if the gate outputs a correct 5 V Logic 1 state.

Troubleshooting

• Symptom: LED is always OFF, even when both switches are open.
• Cause: Floating inputs acting as logic HIGH, or an incorrect wiring to Pin 1 (Output).
• Fix: Verify R1 and R2 are properly connected between the input nodes (VA, VB) and ground (0). Double-check that the LED is connected to Pin 1, not Pin 3.
• Symptom: IC becomes excessively hot to the touch.
• Cause: Power pins (VCC and 0) are reversed, or an output pin is directly shorted to ground or VCC.
• Fix: Instantly disconnect power. Verify Pin 14 goes strictly to VCC and Pin 7 goes strictly to 0.
• Symptom: The alarm triggers (LED turns ON) when any switch is closed, rather than when they are open.
• Cause: Using an OR gate (74HC32) instead of a NOR gate (74HC02), or using pull-up resistors instead of pull-downs.
• Fix: Check the markings on the IC package to ensure it is a 74HC02, and verify R1 and R2 are wired to ground (0).

Objective and use case

In this practical case, you will build a delay-on timer using the versatile NE555 integrated circuit. Upon applying 5 V power, an RC network dictates a waiting period before the timer’s output activates and turns on a «READY» LED.

This timer topology is highly useful in real-world applications:
* Audio amplifiers: Delaying speaker connection until internal voltages stabilize to prevent loud popping noises.
* Power supply sequencing: Ensuring primary rails are fully powered before activating secondary logic circuits.
* Microcontroller resets: Holding a reset line active for a brief period during startup to guarantee clean initialization.

Expected outcome:
* At power-on ($t=0$), the LED will remain OFF.
* The voltage at the timing node (VCAP) will exponentially decay from 5 V down to 1.66 V (which is 1/3 VCC).
* Once VCAP crosses the 1.66 V threshold, the NE555 output (VOUT) will snap from 0 V to 5 V (HIGH), illuminating the LED.
* The delay time will be approximately 5.1 seconds.

Target audience and level: Beginners learning analog-digital timing and RC time constants.

Materials

• U1: NE555 timer IC, function: timing controller
• R1: 100 kΩ resistor, function: timing resistor
• C1: 47 µF electrolytic capacitor, function: timing capacitor
• R2: 330 Ω resistor, function: LED current limiting
• C2: 10 nF ceramic capacitor, function: control voltage stabilization
• D1: green LED, function: READY indicator
• V1: 5 V DC supply

Wiring guide

• V1: connects between VCC (+5 V) and 0 (GND).
• C1: connects between VCC (positive leg) and VCAP (negative leg).
• R1: connects between VCAP and 0.
• U1 connections:
• Pin 1 (GND) connects to 0.
• Pin 2 (TRIG) connects to VCAP.
• Pin 3 (OUT) connects to VOUT.
• Pin 4 (RESET) connects to VCC.
• Pin 5 (CTRL) connects to VCTRL.
• Pin 6 (THR) connects to VCAP.
• Pin 8 (VCC) connects to VCC.
• C2: connects between VCTRL and 0.
• R2: connects between VOUT and VLED.
• D1: connects between VLED (anode) and 0 (cathode).

Conceptual block diagram

Measurements and tests

To validate the transient behavior of this delay-on timer, perform the following steps:

1. Initial State Verification: Ensure power is completely disconnected. Use a multimeter or oscilloscope to confirm that VCAP and VOUT are at 0 V.
2. Apply Power: Turn on the 5 V supply (V1). Start a stopwatch immediately. Verify that VOUT is initially ~0 V and the LED is OFF.
3. Transient Validation of VCAP: Measure the voltage at node VCAP with respect to ground (0). Because the capacitor C1 is tied to VCC, it acts as a short circuit at $t=0$, pulling VCAP to 5 V. As C1 charges through R1, observe VCAP exponentially decaying toward 0 V.
4. Trigger Threshold: Monitor VCAP as it drops. Exactly as it crosses 1.66 V (1/3 of VCC), verify that VOUT instantly jumps to 5 V and the READY LED illuminates.
5. Timing Calculation: Verify the elapsed time. The theoretical delay for this configuration is calculated as T ≈ 1.1 × R × C. With 100 kΩ and 47 µF, T ≈ 5.17 seconds. Check that your measured time aligns with this estimate.

Common mistakes and how to avoid them

• Reversing the R and C positions: Connecting R1 to VCC and C1 to 0 creates a delay-off timer rather than a delay-on timer. Ensure C1 connects strictly to VCC and R1 to 0 to achieve the desired power-on delay.
• Leaving the RESET pin floating: An unconnected Pin 4 can pick up ambient electrical noise, causing the timer to reset randomly and preventing the LED from turning on. Always tie Pin 4 directly to VCC.
• Electrolytic capacitor reverse polarity: In this specific configuration, the positive terminal of C1 must go to VCC and the negative terminal to VCAP. Reversing this will cause high leakage current, drastically altering the delay time or destroying the capacitor.

Troubleshooting

• Symptom: LED turns on instantly without delay.
  • Cause: C1 is internally shorted, or the R1/C1 components were swapped.
  • Fix: Double-check the wiring of nodes VCAP, VCC, and 0. Replace C1 if a short is suspected.
• Symptom: LED never turns on.
  • Cause: VCAP never drops below 1.66 V. This usually happens if C1 has excessive leakage current, essentially forming a voltage divider with R1. It can also occur if the LED (D1) is inserted backwards.
  • Fix: Ensure LED polarity is correct (anode to R2, cathode to 0). Use a higher quality capacitor or decrease R1 (while correspondingly increasing C1 to maintain the same time constant) to overcome leakage.
• Symptom: Delay time is significantly shorter or longer than 5 seconds.
  • Cause: Standard electrolytic capacitors have wide tolerances (often \pm 20\% or worse).
  • Fix: This is normal behavior for basic components. For precision timing, swap the electrolytic capacitor for a tantalum or film capacitor with a tighter tolerance.

Objective and use case

You will build a digital logic circuit where an alarm sensor and an enable switch must both be triggered to turn on a warning LED, implemented entirely with a single 74HC00 NAND gate chip.

This circuit is highly useful for demonstrating fundamental digital concepts:
* It demonstrates the concept of «universal gates,» showing how a NAND gate can be wired as a NOT gate (inverter) to achieve an AND logic function.
* It illustrates how an «enable» signal works, which is an industry standard method to authorize or safely block system operations.
* It provides hands-on practice with handling CMOS logic levels and configuring pull-down networks for reliable switch operation.

Expected outcome:
* The intermediate signal (the output of the first NAND gate) will output a logic LOW (0 V) only when both inputs are HIGH (5 V).
* The final output will be logic HIGH (5 V) and will light the LED strictly when both the Alarm and Enable inputs are HIGH.
* You will practically verify the combined truth table of a NAND and a NOT gate.

Target audience: Beginners in digital electronics learning how to manipulate logic gates.

Materials

• V1: 5 V DC supply
• SW1: SPST switch, function: Alarm trigger
• SW2: SPST switch, function: Enable signal
• R1: 10 kΩ resistor, function: pull-down for ALARM node
• R2: 10 kΩ resistor, function: pull-down for ENABLE node
• R3: 330 Ω resistor, function: LED current limiting
• U1: 74HC00 Quad 2-Input NAND Gate, function: logic evaluation and inversion
• D1: Red LED, function: Alarm indicator

Wiring guide

• V1: connects between VCC and 0.
• SW1: connects between VCC and ALARM.
• R1: connects between ALARM and 0.
• SW2: connects between VCC and ENABLE.
• R2: connects between ENABLE and 0.
• U1 Pin 14 (VCC): connects to VCC.
• U1 Pin 7 (GND): connects to 0.
• U1 Pin 1 (1 A): connects to ALARM.
• U1 Pin 2 (1B): connects to ENABLE.
• U1 Pin 3 (1Y): connects to INTERMEDIATE.
• U1 Pin 4 (2 A): connects to INTERMEDIATE.
• U1 Pin 5 (2B): connects to INTERMEDIATE.
• U1 Pin 6 (2Y): connects to VOUT.
• D1: Anode connects to VOUT, Cathode connects to NODE_LED.
• R3: connects between NODE_LED and 0.
• Safety connection: Connect pins 9, 10, 12, and 13 of U1 to 0 (GND) to prevent unused gates from floating.

Conceptual block diagram

Measurements and tests

1. Use a multimeter to verify the power supply is exactly 5 V across the VCC and 0 nodes.
2. Probe the ALARM and ENABLE nodes relative to 0. Verify they read exactly 0 V when their respective switches are open, and 5 V when closed.
3. Probe the INTERMEDIATE node. It should read ~5 V when either or both switches are open, and drop to ~0 V strictly when both switches are closed.
4. Probe the VOUT node. It should always display the exact opposite logic level of the INTERMEDIATE node.
5. Visually confirm that the LED turns on if and only if both switches are toggled to the closed (active) position.

Common mistakes and how to avoid them

1. Leaving unused inputs floating: CMOS chips like the 74HC00 are highly sensitive to static and ambient noise. Unused gate inputs (pins 9, 10, 12, 13) must be explicitly tied to ground (0) or VCC.
2. Omitting the pull-down resistors: Without R1 and R2, the input pins will float when the switches are open, leading to unpredictable, flickering behavior in the LED. Always ensure the 10 kΩ pull-downs are securely connected to ground.
3. Connecting the LED without a series resistor: Connecting D1 directly between VOUT and 0 will draw excessive current, potentially destroying the LED and burning out the output stage of the 74HC00 chip. R3 is mandatory.

Troubleshooting

• Symptom: The LED never turns off, regardless of switch positions.
• Cause: One of the input pull-down resistors is loose, causing the chip to read a false HIGH, or the intermediate node isn’t wired correctly to both inputs of the second gate.
• Fix: Verify connections for R1 and R2 to ground. Ensure U1 Pin 3 routes precisely to both Pin 4 and Pin 5.
• Symptom: The LED brightness flickers when a hand is moved near the circuit.
• Cause: A floating input is acting as an antenna and picking up environmental noise.
• Fix: Check that all unused inputs on the IC are tied to ground, and ensure R1 and R2 are seated firmly in the breadboard.
• Symptom: The IC becomes hot to the touch.
• Cause: The power supply is connected backwards, or the output node is shorted directly to ground or VCC.
• Fix: Disconnect power immediately. Verify that U1 Pin 14 goes strictly to +5 V and Pin 7 goes strictly to Ground.

Objective and use case

In this practical case, you will build a 2-bit digital counter using a 74HC393 IC and decode its maximum state (binary 11, decimal 3) using a 74HC08 AND gate. A simulated clock pushbutton increments the count, while a manual reset pushbutton forces the counter back to zero.

Why this is useful:
* Demonstrates how sequential logic (counters) tracks discrete events over time.
* Shows how combinational logic (AND gate) is used to decode specific binary states and trigger events.
* Provides a foundational understanding of clock edge triggering and asynchronous resets.
* Acts as a building block for state machines, timers, and step-sequencers in industrial or hobbyist electronics.

Expected outcome:
* Pressing and releasing the clock button will advance the binary state sequentially: 00 → 01 → 10 → 11.
* Two LEDs will display the current binary count (LSB and MSB).
* A third LED (end-of-cycle indicator) will light up strictly when the count reaches state 3.
* Pressing the reset button will immediately extinguish all LEDs, returning the circuit to state 00 regardless of the current count.
* Target audience: Electronics beginners learning digital logic and basic state tracking.

Materials

• V1: 5 V DC supply
• S1: normally open pushbutton, function: clock pulse generator
• S2: normally open pushbutton, function: manual reset trigger
• R1: 10 kΩ resistor, function: pull-down for CLK node
• R2: 10 kΩ resistor, function: pull-down for MR node
• R3: 330 Ω resistor, function: current limiting for QA LED
• R4: 330 Ω resistor, function: current limiting for QB LED
• R5: 330 Ω resistor, function: current limiting for MAX_VAL LED
• D1: green LED, function: LSB indicator (QA)
• D2: yellow LED, function: MSB indicator (QB)
• D3: red LED, function: end-of-cycle indicator
• U1: 74HC393 dual 4-bit binary counter, function: state counting
• U2: 74HC08 quad 2-input AND gate, function: state decoding

Wiring guide

• V1: connects between VCC and 0.
• S1: connects between VCC and CLK.
• R1: connects between CLK and 0.
• S2: connects between VCC and MR.
• R2: connects between MR and 0.
• U1: Pin 1 connects to CLK, Pin 2 connects to MR, Pin 3 connects to QA, Pin 4 connects to QB, Pin 7 connects to 0, Pin 14 connects to VCC.
• U2: Pin 1 connects to QA, Pin 2 connects to QB, Pin 3 connects to MAX_VAL, Pin 7 connects to 0, Pin 14 connects to VCC.
• R3: connects between QA and N_D1.
• D1: connects between N_D1 and 0 (anode to N_D1, cathode to 0).
• R4: connects between QB and N_D2.
• D2: connects between N_D2 and 0 (anode to N_D2, cathode to 0).
• R5: connects between MAX_VAL and N_D3.
• D3: connects between N_D3 and 0 (anode to N_D3, cathode to 0).

Conceptual block diagram

Measurements and tests

1. Initial State Check: Power on the circuit. If any LEDs are lit, press and release S2 (Master Reset). The voltage at the MR node will spike to 5 V, clearing the counter. Measure QA, QB, and MAX_VAL; all should be 0 V. All LEDs must be OFF.
2. First Clock Pulse (State 1): Press and hold S1. The CLK node goes to 5 V. Release S1. The 74HC393 triggers on the falling edge (high-to-low transition). D1 (QA) should turn on. D2 (QB) and D3 (MAX_VAL) remain off.
3. Second Clock Pulse (State 2): Press and release S1 again. D1 turns off and D2 turns on. This represents binary 10 (decimal 2).
4. Third Clock Pulse (State 3): Press and release S1 a third time. Both D1 (QA) and D2 (QB) turn on. Consequently, inputs 1 A and 1B on the 74HC08 are both HIGH. The MAX_VAL node will output 5 V, lighting up the end-of-cycle LED (D3).
5. Rollover (State 0): Press and release S1 a fourth time. The counter overflows the 2-bit capacity represented by QA and QB. Both counting LEDs and the MAX_VAL LED will turn off.
6. Asynchronous Reset Verification: Cycle the counter to state 2 or 3. Press the reset button S2. Observe that the counter immediately resets to 00 without waiting for a clock pulse.

Common mistakes and how to avoid them

• Ignoring switch bounce: Mechanical pushbuttons exhibit «bounce,» creating multiple rapid voltage transitions on a single press. This causes the counter to skip numbers. Avoid this in critical applications by using a hardware debounce circuit (like an RC filter followed by a Schmitt trigger).
• Misunderstanding the clock edge: The 74HC393 increments on the falling edge of the clock signal. Beginners often expect the count to increase the moment the button is pressed, but it actually increases the moment the button is released (when the voltage drops from 5 V to 0 V).
• Leaving unused logic inputs floating: While this basic test circuit focuses on the used gates, leaving the inputs of the unused gates on the 74HC393 and 74HC08 floating can cause internal oscillation and excessive power draw. Always tie unused inputs to GND or VCC.

Troubleshooting

• Symptom: The counter jumps randomly (e.g., skips from 0 to 2 or 3).
• Cause: Mechanical switch bounce on S1 is sending multiple clock pulses instantly.
• Fix: Add a 100 nF capacitor in parallel with R1 to filter out the rapid mechanical bounces, or press the button very deliberately.
• Symptom: The counter never increments; LEDs remain off.
• Cause: The master reset pin is stuck HIGH, keeping the counter constantly cleared.
• Fix: Check R2. Ensure it is firmly connected to GND to pull the MR node LOW when the reset button is not pressed.
• Symptom: LEDs D1 and D2 count correctly, but D3 never turns on.
• Cause: The 74HC08 AND gate is not receiving power, or its inputs are incorrectly wired.
• Fix: Verify that pins 14 (VCC) and 7 (GND) of U2 are connected. Double-check that pin 1 connects to QA and pin 2 connects to QB.
• Symptom: LEDs are very dim or burn out instantly.
• Cause: Incorrect or missing current-limiting resistors.
• Fix: Ensure R3, R4, and R5 (330 Ω) are properly placed in series with the respective LED anodes.