Level: Basic — Build an NE555 astable timer that blinks an LED at a visible frequency.

Objective and use case

You will build a simple astable timer with an NE555 powered from 5 V. The circuit will generate a repetitive square wave that turns an LED on and off continuously.

Why it is useful:
– It demonstrates how a basic timer generates a clock signal without a microcontroller.
– It is useful as a visual blink indicator for power or system status.
– It can be used as a simple test source for checking frequency measurement tools.
– It helps students observe capacitor charge and discharge behavior in a real circuit.

Expected outcome:
– VOUT switches between approximately 0 V and 5 V.
– The LED blinks at a clearly visible rate, about 1 Hz to 3 Hz.
– The timing node TH_TR shows a repeating charge/discharge waveform between about 1/3 VCC and 2/3 VCC.
– The measured period is close to the value predicted by the NE555 astable equations.
– The duty cycle is greater than 50% for the standard RA/RB astable connection.

Target audience and level: Beginners in basic electronics laboratory practice.

Materials

• U1: NE555 timer IC, function: astable oscillator core
• R1: 10 kΩ resistor, function: timing resistor RA from VCC to DIS
• R2: 68 kΩ resistor, function: timing resistor RB from DIS to TH_TR
• C1: 10 µF electrolytic capacitor, function: timing capacitor
• C2: 10 nF capacitor, function: control-voltage noise filter on CV
• C3: 100 nF capacitor, function: supply decoupling across VCC and GND
• R3: 330 Ω resistor, function: LED current limiting
• D1: red LED, function: visual output indicator
• V1: 5 V DC supply
• B1: breadboard, function: circuit assembly platform
• J1: jumper wires, function: interconnections

Wiring guide

Use the node names VCC, 0, DIS, TH_TR, CV, RESET, and VOUT.

• V1 connects between nodes VCC and 0.
• U1 pin 8 (VCC) connects to node VCC.
• U1 pin 1 (GND) connects to node 0.
• U1 pin 4 (RESET) connects to node VCC.
• U1 pin 3 (OUT) connects to node VOUT.
• U1 pin 7 (DISCH) connects to node DIS.
• U1 pin 2 (TRIG) connects to node TH_TR.
• U1 pin 6 (THRESH) connects to node TH_TR.
• U1 pin 5 (CTRL) connects to node CV.
• R1 connects between nodes VCC and DIS.
• R2 connects between nodes DIS and TH_TR.
• C1 connects between nodes TH_TR and 0; if electrolytic, connect the positive lead to TH_TR and the negative lead to 0.
• C2 connects between nodes CV and 0.
• C3 connects between nodes VCC and 0, placed physically close to U1.
• R3 connects between nodes VOUT and LED_A.
• D1 connects between nodes LED_A and 0; connect the anode to LED_A and the cathode to 0.

Conceptual block diagram

Schematic

Practical case: astable oscillator with NE555

[ V1: 5 V DC ] --(+)--> [ VCC ]
[ V1: 5 V DC ] --(-)--> [ 0 ]

[ VCC ] --(pin8 supply)--> [ U1: NE555 astable core ] --(pin3 = VOUT)--> [ R3: 330 ohm ] --(LED_A)--> [ D1: Red LED ] --> [ 0 ]
[ VCC ] --(RESET to pin4)--> [ U1: NE555 astable core ]
[ VCC ] --(R1: 10 k ohm, RA)--> [ DIS / U1 pin7 ] --(R2: 68 k ohm, RB)--> [ TH_TR / U1 pins2+6 ] --(timing sense)--> [ U1: NE555 astable core ]
[ TH_TR / U1 pins2+6 ] --(C1: 10 uF, + to TH_TR, - to 0)--> [ 0 ]
[ U1 pin5 = CV ] --(C2: 10 nF noise filter to 0)--> [ 0 ]
[ VCC ] --(C3: 100 nF decoupling to 0, close to U1)--> [ 0 ]
[ U1 pin1 = GND ] --> [ 0 ]

Electrical diagram

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Measurements and tests

1. Power-off inspection
2. Check that U1 pin 1 goes to 0 and U1 pin 8 goes to VCC.
3. Verify that U1 pin 2 and U1 pin 6 are linked together at TH_TR.

4. Confirm LED polarity: anode toward R3, cathode toward 0.

5. Initial power test

6. Apply 5 V from V1.
7. The LED should start blinking immediately.

8. If the LED stays always on or always off, remove power and recheck wiring.

9. Measure output voltage

10. Probe VOUT with a multimeter or oscilloscope.
11. With an oscilloscope, expect a square-like waveform from near 0 V to near 5 V.

12. With a multimeter, the reading may show an average voltage between these limits, depending on blink speed.

13. Measure the timing node

14. Probe TH_TR.
15. Expect a repeating capacitor waveform rising from about 1.67 V to 3.33 V when VCC = 5 V.

16. This confirms the internal 1/3 VCC and 2/3 VCC thresholds of the NE555.

17. Check the control-voltage node

18. Probe CV.

19. Expect a nearly steady voltage close to 2/3 VCC, around 3.3 V, with small ripple.

20. Estimate period and frequency

21. Use the standard astable equations:
22. T = 0.693 x (R1 + 2R2) x C1
23. f = 1 / T
24. With R1 = 10 kΩ, R2 = 68 kΩ, C1 = 10 µF:
25. T ≈ 0.693 x (10k + 136k) x 10 µF ≈ 1.01 s
26. f ≈ 0.99 Hz

27. Measured blinking should be close to 1 blink per second.

28. Estimate duty cycle

29. Use:
30. tHIGH = 0.693 x (R1 + R2) x C1
31. tLOW = 0.693 x R2 x C1
32. Duty cycle ≈ tHIGH / T
33. For these values, duty cycle is about 53%.
34. On the oscilloscope, the high time should be slightly longer than the low time.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Astable oscillator with NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* NE555 Timer IC Subcircuit Instance
* Pins: GND TRIG OUT RESET CTRL THRES DISCH VCC_PIN
XU1 0 TH_TR VOUT VCC CV TH_TR DISCH VCC NE555

* Timing Components
R1 VCC DISCH 10k
R2 DISCH TH_TR 47k
C1 TH_TR 0 10u
C2 CV 0 10n

* Output Load (LED)
R3 VOUT LED_A 330
D1 LED_A 0 DLED

* ... (truncated in public view) ...

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* Practical case: Astable oscillator with NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* NE555 Timer IC Subcircuit Instance
* Pins: GND TRIG OUT RESET CTRL THRES DISCH VCC_PIN
XU1 0 TH_TR VOUT VCC CV TH_TR DISCH VCC NE555

* Timing Components
R1 VCC DISCH 10k
R2 DISCH TH_TR 47k
C1 TH_TR 0 10u
C2 CV 0 10n

* Output Load (LED)
R3 VOUT LED_A 330
D1 LED_A 0 DLED

* Models
.MODEL DLED D(IS=1e-19 N=1.6 RS=10 BV=5 IBV=10u)

* Behavioral NE555 Subcircuit
.SUBCKT NE555 GND TRIG OUT RESET CTRL THRES DISCH VCC_PIN
* Internal voltage divider (3 x 5k resistors)
R1 VCC_PIN CTRL 5k
R2 CTRL N1 5k
R3 N1 GND 5k

* Smooth comparators for threshold, trigger, and reset
B_COMP_TH COMP_TH GND V=0.5*(1+tanh(100*(V(THRES,GND)-V(CTRL,GND))))
B_COMP_TR COMP_TR GND V=0.5*(1+tanh(100*(V(N1,GND)-V(TRIG,GND))))
B_COMP_RST COMP_RST GND V=0.5*(1+tanh(100*(0.7-V(RESET,GND))))

* SR Latch (Integrator with positive feedback for infinite hold time)
B_LATCH GND LATCH I=V(COMP_TR,GND) - V(COMP_TH,GND) - 5*V(COMP_RST,GND) + (V(LATCH,GND)>0.5 ? 0.1 : -0.1)
C_LATCH LATCH GND 1n
R_LATCH LATCH GND 100Meg

* Latch Voltage Clamps (Clamps V(LATCH) between ~0V and ~1V)
D1 GND LATCH D_CLAMP
V_CLAMP V_CLAMP_NODE GND 1
D2 LATCH V_CLAMP_NODE D_CLAMP
.model D_CLAMP D(N=0.01 RS=1)

* Output Driver Stage
B_OUT OUT_INT GND V=V(LATCH,GND)>0.5 ? V(VCC_PIN,GND) : 0.1
R_OUT OUT_INT OUT 10

* Open-Collector Discharge Transistor (Modeled as a Switch)
B_DISCH_CTRL DISCH_CTRL GND V=V(LATCH,GND)<0.5 ? 1 : 0
S_DISCH DISCH GND DISCH_CTRL GND SW_DISCH
.model SW_DISCH SW(VT=0.5 RON=15 ROFF=100Meg)
.ENDS

* Force initial condition on timing capacitor to ensure guaranteed oscillator startup
.ic V(TH_TR)=0

* Simulation Commands
.op
.tran 1m 3
.print tran V(VOUT) V(TH_TR) V(DISCH) V(LED_A) V(CV)

Simulation Results (Transient Analysis)

Analysis: The transient analysis spans 0 s to 3 s. Main ranges: v(vout) 100 mV -> 4.9 V; v(disch) 8.02 mV -> 4.71 V; v(th_tr) 0 uV -> 3.32 V.

Show raw data table (3013 rows)

Index   time            v(vout)         v(th_tr)        v(disch)        v(led_a)        v(cv)
0	0.000000e+00	4.903386e+00	0.000000e+00	4.122467e+00	1.715117e+00	3.333333e+00
1	1.000000e-05	4.903386e+00	8.771053e-05	4.122482e+00	1.715117e+00	3.333333e+00
2	2.000000e-05	4.903386e+00	1.754195e-04	4.122498e+00	1.715117e+00	3.333333e+00
3	4.000000e-05	4.903386e+00	3.508344e-04	4.122529e+00	1.715117e+00	3.333333e+00
4	8.000000e-05	4.903386e+00	7.016457e-04	4.122590e+00	1.715117e+00	3.333333e+00
5	1.600000e-04	4.903386e+00	1.403195e-03	4.122713e+00	1.715117e+00	3.333333e+00
6	3.200000e-04	4.903386e+00	2.805997e-03	4.122959e+00	1.715117e+00	3.333333e+00
7	6.400000e-04	4.903386e+00	5.610420e-03	4.123451e+00	1.715117e+00	3.333333e+00
8	1.280000e-03	4.903386e+00	1.121455e-02	4.124434e+00	1.715117e+00	3.333333e+00
9	2.280000e-03	4.903386e+00	1.995841e-02	4.125968e+00	1.715117e+00	3.333333e+00
10	3.280000e-03	4.903386e+00	2.868694e-02	4.127499e+00	1.715117e+00	3.333333e+00
11	4.280000e-03	4.903386e+00	3.740018e-02	4.129028e+00	1.715117e+00	3.333333e+00
12	5.280000e-03	4.903386e+00	4.609814e-02	4.130554e+00	1.715117e+00	3.333333e+00
13	6.280000e-03	4.903386e+00	5.478085e-02	4.132077e+00	1.715117e+00	3.333333e+00
14	7.280000e-03	4.903386e+00	6.344835e-02	4.133597e+00	1.715117e+00	3.333333e+00
15	8.280000e-03	4.903386e+00	7.210065e-02	4.135115e+00	1.715117e+00	3.333333e+00
16	9.280000e-03	4.903386e+00	8.073778e-02	4.136630e+00	1.715117e+00	3.333333e+00
17	1.028000e-02	4.903386e+00	8.935978e-02	4.138143e+00	1.715117e+00	3.333333e+00
18	1.128000e-02	4.903386e+00	9.796666e-02	4.139653e+00	1.715117e+00	3.333333e+00
19	1.228000e-02	4.903386e+00	1.065585e-01	4.141160e+00	1.715117e+00	3.333333e+00
20	1.328000e-02	4.903386e+00	1.151352e-01	4.142665e+00	1.715117e+00	3.333333e+00
21	1.428000e-02	4.903386e+00	1.236969e-01	4.144166e+00	1.715117e+00	3.333333e+00
22	1.528000e-02	4.903386e+00	1.322436e-01	4.145666e+00	1.715117e+00	3.333333e+00
23	1.628000e-02	4.903386e+00	1.407753e-01	4.147162e+00	1.715117e+00	3.333333e+00
... (2989 more rows) ...

Common mistakes and how to avoid them

1. Reversing the electrolytic capacitor
2. Error: C1 installed with wrong polarity.

3. Fix: connect the positive terminal of C1 to TH_TR and the negative terminal to 0.

4. Wrong NE555 pin placement on the breadboard

5. Error: pin numbering mirrored or shifted.

6. Fix: identify the notch or dot on the IC and count pins correctly before wiring.

7. Forgetting supply decoupling

8. Error: omitting C3 causes unstable behavior or irregular blinking.
9. Fix: place C3 = 100 nF directly between U1 pin 8 and U1 pin 1.

Troubleshooting

• Symptom: LED does not light at all
• Cause: no 5 V supply, wrong LED polarity, or open resistor path.

• Fix: verify VCC, check D1 orientation, and confirm continuity from VOUT through R3 to D1.

• Symptom: LED stays permanently on

• Cause: TH_TR not connected correctly, DIS wiring error, or R2 misplaced.

• Fix: check that R2 is between DIS and TH_TR, and that pins 2 and 6 are tied together.

• Symptom: LED stays permanently off

• Cause: RESET not tied high or output shorted.

• Fix: connect U1 pin 4 directly to VCC and inspect VOUT for accidental grounding.

• Symptom: Blink rate is much too fast or too slow

• Cause: wrong resistor value or wrong capacitor value.

• Fix: measure R1, R2, and C1; replace parts with the intended values.

• Symptom: Irregular or noisy waveform

• Cause: poor breadboard contacts or missing C2/C3.
• Fix: reseat the IC, shorten wiring, and install the bypass capacitors.

Possible improvements and extensions

• Add a frequency control

• Replace R2 with a series combination of a fixed resistor and a potentiometer to adjust the blink rate.

• Drive a buzzer or second indicator

• Use VOUT to control a transistor stage so the timer can flash a brighter LED or pulse a small buzzer.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic – Build a monostable timer circuit using the NE555 IC to control an LED output for a set duration.

Objective and use case

In this practical case, you will build a monostable multivibrator (one-shot timer) using the classic NE555 IC. A mechanical push-button will trigger the circuit to illuminate an LED for a specific, predetermined amount of time based on a resistor-capacitor (RC) network.

This circuit is highly useful in real-world applications:
* Debouncing mechanical switches and push-buttons for digital microcontrollers.
* Creating timed light switches for hallways, staircases, or closets.
* Generating precise delays for industrial and automated dispensing systems.
* Providing a fixed-width pulse for alarm triggers or motor control logic.

Expected outcome:
* The LED remains completely OFF when the circuit is in its idle state.
* Pressing the trigger button causes the output to immediately go HIGH (approx. 5 V), turning on the LED.
* The LED stays illuminated for approximately 1.1 seconds before turning OFF automatically.
* The voltage across the timing capacitor will exponentially charge to 3.33 V (2/3 of VCC) before the output resets to LOW.

Target audience and level: Beginners in electronics learning about timing concepts, RC networks, and the 555 timer.

Materials

• V1: 5 V DC supply
• U1: NE555 timer IC, function: monostable controller
• R1: 10 kΩ resistor, function: pull-up for the trigger pin
• R2: 10 kΩ resistor, function: timing resistor (RT)
• R3: 330 Ω resistor, function: LED current limiting
• C1: 100 µF electrolytic capacitor, function: timing capacitor (CT)
• C2: 10 nF ceramic capacitor, function: control voltage stabilization
• S1: Normally Open (NO) push-button, function: trigger input
• D1: Red LED, function: output indicator

Wiring guide

• V1 connects between VCC and 0 (GND).
• U1 Pin 1 (GND) connects to 0.
• U1 Pin 8 (VCC) connects to VCC.
• R1 connects between VCC and TRIG.
• S1 connects between TRIG and 0.
• U1 Pin 2 (Trigger) connects to TRIG.
• R2 connects between VCC and DISCH_THRES.
• C1 connects between DISCH_THRES (positive lead) and 0 (negative lead).
• U1 Pin 6 (Threshold) connects to DISCH_THRES.
• U1 Pin 7 (Discharge) connects to DISCH_THRES.
• U1 Pin 4 (Reset) connects to VCC.
• C2 connects between CTRL and 0.
• U1 Pin 5 (Control Voltage) connects to CTRL.
• R3 connects between OUT and NODE_LED.
• D1 connects between NODE_LED (anode) and 0 (cathode).
• U1 Pin 3 (Output) connects to OUT.

Conceptual block diagram

Schematic

[ U1: NE555 Timer ]
VCC -----------------------------------------> [ Pin 8: VCC      ]
                                               [                 ]
VCC --> [ R1: 10 kΩ ] --(TRIG)----------------> [ Pin 2: Trigger  ]
                          |                    [                 ]
                     [ S1: Button ]            [                 ]
                          |                    [                 ]
                         GND                   [                 ]
                                               [                 ]
VCC --> [ R2: 10 kΩ ] --(DISCH_THRES)---------> [ Pin 6: Thres    ] --(Pin 3: OUT)--> [ R3: 330 Ω ] --> [ D1: Red LED ] --> GND
                          |                    [ Pin 7: Disch    ]
                     [ C1: 100µF ]             [                 ]
                          |                    [                 ]
                         GND                   [                 ]
                                               [                 ]
VCC -----------------------------------------> [ Pin 4: Reset    ]
                                               [                 ]
                                               [ Pin 5: Control  ] --(CTRL)--> [ C2: 10nF ] --> GND
                                               [                 ]
GND -----------------------------------------> [ Pin 1: GND      ]

Electrical diagram

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Measurements and tests

1. Standby Validation: Before pressing the button, use a multimeter to measure the voltage at node TRIG. It should read 5 V due to the pull-up resistor. The voltage at node OUT should be 0 V.
2. Trigger Observation: Press S1 and measure TRIG momentarily dropping to 0 V.
3. Output Behavior: Connect your multimeter or oscilloscope to node OUT. Press the button and verify the voltage jumps to ~5 V, stays high, and returns to 0 V automatically.
4. Capacitor Charging Curve: Connect a probe to node DISCH_THRES. Observe the voltage charging from 0 V up to ~3.33 V (which is 2/3 of VCC) immediately after the trigger is pressed. Once it hits this threshold, the voltage should sharply drop back to 0 V.
5. Timing Verification: Use a stopwatch or oscilloscope to measure the ON duration. Verify that it matches the theoretical formula: T = 1.1 × R2 × C1 (1.1 × 10,000 Ω × 0.0001 F ≈ 1.1 seconds).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* One-Shot Timer Using NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Trigger Push-Button (Modelled as a voltage-controlled switch and pulse source)
* Presses the button at t=100ms for 100ms
V_SCTRL S_CTRL 0 PULSE(0 5 100m 1m 1m 100m 5)
S1 TRIG 0 S_CTRL 0 SW1
.model SW1 SW(Vt=2.5 Ron=1 Roff=100Meg)

* Pull-up for Trigger
R1 VCC TRIG 10k

* Timing Components (10k and 100uF -> ~1.1s pulse)
R2 VCC DISCH_THRES 10k
C1 DISCH_THRES 0 100u

* Control Voltage Stabilization
* ... (truncated in public view) ...

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* One-Shot Timer Using NE555
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Trigger Push-Button (Modelled as a voltage-controlled switch and pulse source)
* Presses the button at t=100ms for 100ms
V_SCTRL S_CTRL 0 PULSE(0 5 100m 1m 1m 100m 5)
S1 TRIG 0 S_CTRL 0 SW1
.model SW1 SW(Vt=2.5 Ron=1 Roff=100Meg)

* Pull-up for Trigger
R1 VCC TRIG 10k

* Timing Components (10k and 100uF -> ~1.1s pulse)
R2 VCC DISCH_THRES 10k
C1 DISCH_THRES 0 100u

* Control Voltage Stabilization
C2 CTRL 0 10n

* Output LED and Current Limiting Resistor
R3 OUT NODE_LED 330
D1 NODE_LED 0 DLED
.model DLED D(IS=1e-15 N=2.0 RS=10)

* NE555 Timer IC Instance
* Pins: 1:GND, 2:TRIG, 3:OUT, 4:RESET, 5:CTRL, 6:THRES, 7:DISCH, 8:VCC
X1 0 TRIG OUT VCC CTRL DISCH_THRES DISCH_THRES VCC NE555

* Dummy IN node to satisfy print requirements
V_IN IN TRIG 0
R_IN IN 0 1G

* Functional NE555 subcircuit (Behavioral)
.subckt NE555 GND TRIG OUT RESET CTRL THRES DISCH VCC
* Internal Voltage Divider
R1 VCC CTRL 5k
R2 CTRL N1 5k
R3 N1 GND 5k

* SR Latch Logic (Reset > Trigger > Threshold)
B1 LATCH_IN GND V= V(RESET, GND)<1.0 ? 0 : ( V(TRIG, GND)V(CTRL, GND) ? 0 : V(Q_delay, GND) ) )

* Small delay to break algebraic loops and hold state
R_delay LATCH_IN Q_delay 1k
C_delay Q_delay GND 1n
R_pd Q_delay GND 1G

* Output Stage
B2 OUT_INT GND V= V(Q_delay, GND)>0.5 ? V(VCC, GND) : 0.1
R_OUT OUT_INT OUT 10

* Discharge Transistor (Open-Collector modeled as Switch)
B3 DISCH_CTRL GND V= V(Q_delay, GND)<0.5 ? 1 : 0
R_DC DISCH_CTRL GND 1G
S1 DISCH GND DISCH_CTRL GND S_DISCH
.model S_DISCH SW(Vt=0.5 Ron=10 Roff=100Meg)
.ends

.op
.tran 1m 2s
.print tran V(IN) V(OUT) V(TRIG) V(DISCH_THRES) V(CTRL) V(NODE_LED) V(S_CTRL) V(VCC)
.end

Simulation Results (Transient Analysis)

Analysis: The simulation shows the trigger signal dropping low at t=100ms, which causes the output to go high (~4.9V) and the LED node voltage to rise (~1.65V). The discharge threshold voltage then charges up to ~2.74V (which is slightly below 2/3 VCC, but the output drops back low at ~895ms). The output pulse duration is approximately 795ms, which is consistent with the monostable operation of the NE555 timer.

Show raw data table (2054 rows)

Index   time            v(in)           v(out)          v(trig)         v(disch_thres)  v(ctrl)         v(node_led)     v(s_ctrl)       v(vcc)
0	0.000000e+00	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
1	1.000000e-05	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
2	2.000000e-05	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
3	4.000000e-05	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
4	8.000000e-05	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
5	1.600000e-04	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
6	3.200000e-04	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
7	6.400000e-04	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
8	1.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
9	2.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
10	3.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
11	4.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
12	5.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
13	6.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
14	7.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
15	8.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
16	9.280000e-03	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
17	1.028000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
18	1.128000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
19	1.228000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
20	1.328000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
21	1.428000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
22	1.528000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
23	1.628000e-02	4.999450e+00	1.000000e-01	4.999450e+00	4.995005e-03	3.333333e+00	1.000000e-01	0.000000e+00	5.000000e+00
... (2030 more rows) ...

Common mistakes and how to avoid them

• Leaving the Reset pin (Pin 4) floating: A floating reset pin can act as an antenna, picking up noise and causing erratic resetting of the timer. Always tie Pin 4 to VCC when not actively using the reset functionality.
• Reversing the electrolytic capacitor polarity: Placing C1 backward will prevent it from charging correctly, alter the timing, and potentially damage the capacitor. Always ensure the negative stripe is connected to 0 (GND).
• Omitting the pull-up resistor on the trigger: If R1 is left out, Pin 2 will float, causing the 555 timer to trigger randomly from ambient electrical noise. Ensure R1 is in place to hold the pin solidly at HIGH when idle.

Troubleshooting

• Symptom: The LED stays ON indefinitely.
  • Cause: The trigger pin (TRIG) is held LOW continuously, either because the push-button is stuck or wired incorrectly, or the trigger pulse is longer than the set RC timing.
  • Fix: Disconnect the button temporarily to check if the LED turns off. Ensure S1 is wired properly and only briefly pulls TRIG to ground.
• Symptom: The LED never turns on when the button is pressed.
  • Cause: Pin 4 (Reset) is incorrectly connected to ground, the LED is inserted backward, or the NE555 IC lacks power.
  • Fix: Verify that VCC is 5 V, Pin 4 is tied to VCC, and check the orientation of D1 (anode toward R3, cathode to ground).
• Symptom: Timer duration is much shorter or longer than 1.1 seconds.
  • Cause: Using a faulty, leaky electrolytic capacitor, or substituting incorrect values for R2 or C1.
  • Fix: Check component codes. Remember that electrolytic capacitors often have a wide tolerance (±20%). Measure R2 with a multimeter to confirm it is 10 kΩ.
• Symptom: The circuit re-triggers continuously by itself.
  • Cause: Missing decoupling capacitor on the control voltage pin, allowing internal noise to cross the comparative thresholds.
  • Fix: Ensure the 10 nF capacitor (C2) is securely connected between Pin 5 and ground to stabilize the internal voltage divider.

Possible improvements and extensions

• Adjustable Timer: Replace R2 with a 1 kΩ fixed resistor in series with a 100 kΩ potentiometer. This modification allows you to manually sweep the timing duration from roughly 0.1 seconds to 11 seconds.
• High-Power Load Control: Replace the LED and current-limiting resistor with an NPN transistor or an N-channel MOSFET at node OUT to drive heavier loads, such as a 5 V relay, a DC motor, or a high-brightness lamp.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic – Understand logical inversion using a NOT gate to activate a standby LED when the main system turns off.

Objective and use case

You will build a digital logic circuit using a 74HC04 NOT gate that monitors a main power switch. When the switch is turned off, the NOT gate logically inverts the signal to activate a «standby» indicator LED.

Why this is useful:
* It perfectly replicates how household appliances (like televisions or microwaves) indicate they are plugged in but currently turned off.
* It provides clear visual feedback in industrial panels when a machine is safe to approach.
* It serves as a foundational example of how to invert control signals for active-low indicators and logic translation.

Expected outcome:
* When the main switch is closed (HIGH logic state, near 5 V), the standby LED remains strictly OFF.
* When the main switch is open (LOW logic state, near 0 V), the standby LED turns ON.
* The circuit accurately demonstrates the inversion of logic states (V_in vs. V_out) through practical voltage measurements.

Target audience and level: Beginners in digital electronics learning basic logic gates.

Materials

• V1: 5 V DC supply, function: main power source
• SW1: SPST switch, function: main system power switch simulator
• R1: 10 kΩ resistor, function: pull-down for VA node
• U1: 74HC04 hex inverter IC, function: logical NOT gate
• R2: 330 Ω resistor, function: LED current limiting
• D1: red LED, function: standby mode indicator

Pin-out of the 74HC04 IC

The 74HC04 is a Hex Inverter IC, meaning it contains six independent NOT gates. We will use the first gate.

(Note: The other input pins [3, 5, 9, 11, 13] should ideally be tied to ground in a permanent circuit to prevent floating inputs and reduce power consumption, but are omitted here for simplicity).

Wiring guide

• V1: connects between VCC and 0.
• SW1: connects between VCC and VA.
• R1: connects between VA and 0.
• U1: Pin 14 connects to VCC, Pin 7 connects to 0, Pin 1 (1 A) connects to VA, Pin 2 (1Y) connects to VOUT.
• R2: connects between VOUT and VLED.
• D1: anode connects to VLED, cathode connects to 0.

Conceptual block diagram

Schematic

VCC --> [ SW1: SPST Switch ] --(Node VA)--> [ U1: 74HC04 Inverter ] --(VOUT)--> [ R2: 330 Ω Resistor ] --(VLED)--> [ D1: Red LED ] --> GND
                                    |
                                    V
                         [ R1: 10 kΩ Pull-down ]
                                    |
                                    V
                                   GND

Electrical diagram

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Truth table

Measurements and tests

1. Test the Input Signal (V_in): Connect your multimeter between node VA and ground (0). Open SW1 and verify the voltage is near 0 V. Close SW1 and verify the voltage is near 5 V.
2. Test the Inverted Output (V_out): Connect your multimeter between node VOUT and ground (0). Observe the voltage invert: it should be near 5 V when SW1 is open, and near 0 V when SW1 is closed.
3. Verify the Logic State: Physically observe D1. Ensure it lights up only when the simulated main system (SW1) is powered down.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Standby mode indicator
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Switch SW1 (Main system power switch simulator)
* Starts closed (system ON, standby OFF), opens at 50us (system OFF, standby ON)
S1 VCC VA SW_CTRL 0 SWMOD
VSW_CTRL SW_CTRL 0 PULSE(5 0 50u 1u 1u 100u 250u)
.model SWMOD SW(VT=2.5 RON=0.1 ROFF=100MEG)

* Pull-down resistor for switch node VA
R1 VA 0 10k

* U1: 74HC04 Hex Inverter IC
* Pin 1 (1A) = VA, Pin 2 (1Y) = VOUT, Pin 14 = VCC, Pin 7 = 0
XU1 VA VOUT VCC 0 74HC04_INV

* Current limiting resistor for LED
* ... (truncated in public view) ...

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* Practical case: Standby mode indicator
.width out=256

* Power Supply
V1 VCC 0 DC 5

* Switch SW1 (Main system power switch simulator)
* Starts closed (system ON, standby OFF), opens at 50us (system OFF, standby ON)
S1 VCC VA SW_CTRL 0 SWMOD
VSW_CTRL SW_CTRL 0 PULSE(5 0 50u 1u 1u 100u 250u)
.model SWMOD SW(VT=2.5 RON=0.1 ROFF=100MEG)

* Pull-down resistor for switch node VA
R1 VA 0 10k

* U1: 74HC04 Hex Inverter IC
* Pin 1 (1A) = VA, Pin 2 (1Y) = VOUT, Pin 14 = VCC, Pin 7 = 0
XU1 VA VOUT VCC 0 74HC04_INV

* Current limiting resistor for LED
R2 VOUT VLED 330

* D1: Red LED (Standby mode indicator)
D1 VLED 0 DLED
.model DLED D(IS=1e-15 N=1.8 RS=10)

* Subcircuit for 74HC04 Inverter Gate
.subckt 74HC04_INV A Y VCC GND
B1 Y_int GND V=V(VCC,GND)*0.5*(1-tanh(10*(V(A,GND)-2.5)))
Rin A GND 100Meg
Rout Y_int Y 50
.ends

* Simulation Directives
.tran 1u 300u
.op

* Output Directives (Input and Output nodes listed first)
.print tran V(VA) V(VOUT) V(VLED) V(VCC)

.end

Simulation Results (Transient Analysis)

Analysis: The simulation shows that when the switch is closed (VA ≈ 5V), the inverter output VOUT is 0V and the LED is off. When the switch opens at 50us (VA ≈ 0V due to pull-down R1), VOUT goes HIGH (≈ 4.5V) and the LED turns on (VLED ≈ 1.48V). This perfectly matches the intended truth table.

Show raw data table (340 rows)

Index   time            v(va)           v(vout)         v(vled)         v(vcc)
0	0.000000e+00	4.999950e+00	1.082004e-19	8.223227e-19	5.000000e+00
1	1.000000e-08	4.999950e+00	9.063787e-31	6.888478e-30	5.000000e+00
2	2.000000e-08	4.999950e+00	-9.06379e-31	-6.88848e-30	5.000000e+00
3	4.000000e-08	4.999950e+00	-3.79630e-41	-2.88519e-40	5.000000e+00
4	8.000000e-08	4.999950e+00	1.518521e-41	1.154076e-40	5.000000e+00
5	1.600000e-07	4.999950e+00	1.017634e-51	7.734020e-51	5.000000e+00
6	3.200000e-07	4.999950e+00	-2.54409e-52	-1.93351e-51	5.000000e+00
7	6.400000e-07	4.999950e+00	-2.34426e-62	-1.78164e-61	5.000000e+00
8	1.280000e-06	4.999950e+00	4.262287e-63	3.239338e-62	5.000000e+00
9	2.280000e-06	4.999950e+00	3.983291e-73	3.027301e-72	5.000000e+00
10	3.280000e-06	4.999950e+00	-3.57046e-74	-2.71355e-73	5.000000e+00
11	4.280000e-06	4.999950e+00	-3.93493e-84	-2.99055e-83	5.000000e+00
12	5.280000e-06	4.999950e+00	2.990920e-85	2.273099e-84	5.000000e+00
13	6.280000e-06	4.999950e+00	3.797323e-95	2.885965e-94	5.000000e+00
14	7.280000e-06	4.999950e+00	-2.50545e-96	-1.90414e-95	5.000000e+00
15	8.280000e-06	4.999950e+00	-3.60072e-106	-2.73655e-105	5.000000e+00
16	9.280000e-06	4.999950e+00	2.098779e-107	1.595072e-106	5.000000e+00
17	1.028000e-05	4.999950e+00	3.367893e-117	2.559599e-116	5.000000e+00
18	1.128000e-05	4.999950e+00	-1.75812e-118	-1.33617e-117	5.000000e+00
19	1.228000e-05	4.999950e+00	-3.11579e-128	-2.36800e-127	5.000000e+00
20	1.328000e-05	4.999950e+00	1.472749e-129	1.119289e-128	5.000000e+00
21	1.428000e-05	4.999950e+00	2.856788e-139	2.171159e-138	5.000000e+00
22	1.528000e-05	4.999950e+00	-1.23370e-140	-9.37613e-140	5.000000e+00
23	1.628000e-05	4.999950e+00	-2.59978e-150	-1.97583e-149	5.000000e+00
... (316 more rows) ...

Common mistakes and how to avoid them

• Omitting the pull-down resistor (R1): Without R1, opening SW1 leaves the input pin (VA) floating, which can cause the NOT gate to oscillate unpredictably or pick up stray noise. Always secure the LOW state with a pull-down resistor.
• Forgetting IC power pins: It is common to wire the input and output of a logic gate but forget to connect VCC (Pin 14) and GND (Pin 7) on the U1 chip itself. The gate will not function without power.
• Reversing the LED polarity: If D1 is installed backwards (cathode to VLED, anode to 0), it will block current and never light up, even when VOUT correctly outputs 5 V.

Troubleshooting

• Symptom: The standby LED is always OFF.
• Cause: The LED might be backwards, R2 might be too high in value, or the IC is missing power.
• Fix: Check LED orientation (long leg to VLED). Verify U1 pins 14 and 7 are securely connected to VCC and 0.
• Symptom: The standby LED is always ON, regardless of the switch.
• Cause: The switch is not properly connected to VCC, or the switch contacts are faulty, leaving the input permanently pulled LOW by R1.
• Fix: Measure node VA. If it stays at 0 V when the switch is closed, check the wiring from VCC to SW1.
• Symptom: The standby LED flickers when the switch is open.
• Cause: Node VA is floating. R1 is likely disconnected or incorrectly placed.
• Fix: Ensure R1 firmly connects node VA directly to ground (0).

Possible improvements and extensions

• Add a «Main System ON» indicator: Connect a green LED and a 330 Ω resistor directly to node VA to show when the main system is actively running, creating a dual-state visual indicator.
• Drive multiple standby indicators: Use another of the unused NOT gates in the 74HC04 (e.g., input on pin 3 connected to VA, output on pin 4) to drive a secondary standby indicator or a low-power piezo buzzer.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic – Learn to use an NPN transistor as a switch to drive a DC motor, including the use of a flyback diode.

Objective and use case

In this practical case, you will build a low-side switch circuit using an NPN transistor to safely control a high-current DC motor from a low-power control signal.

This topology is highly useful in the real world for several reasons:
* Interfacing low-voltage microcontrollers (like an Arduino or Raspberry Pi) with higher power loads that require external power supplies.
* Automating small cooling fans in temperature-controlled systems.
* Building basic drive systems for small hobbyist robotics.
* Protecting delicate control logic from the damaging voltage spikes generated by inductive loads.

Expected outcome:
* Applying a 5 V control signal to the base circuit will saturate the transistor.
* The DC motor will spin as the transistor bridges its connection to ground.
* The flyback diode will safely dissipate the motor’s inductive kickback when the control signal is turned off.
* Measurable base voltage (VBE) around 0.7 V, near-zero collector-emitter voltage (VCE) indicating saturation, and clearly observable base current (IB) and collector current (IC).

Target audience and level: Beginners in electronics and hobbyists looking to control mechanical loads safely.

Materials

• V1: 9 V DC supply, function: main power source for the DC motor
• V2: 5 V DC supply, function: simulated control signal source
• SW1: SPST switch, function: manual control of the base signal
• Q1: 2N2222 NPN transistor, function: low-side switch to drive the motor
• M1: 9 V DC motor, function: inductive mechanical load
• D1: 1N4007 diode, function: flyback diode to suppress inductive spikes
• R1: 1 kΩ resistor, function: base current limiting resistor
• R2: 10 kΩ resistor, function: pull-down resistor for the control signal

Wiring guide

• V1: connects between nodes 9 V_PWR and 0
• V2: connects between nodes 5 V_CTRL and 0
• SW1: connects between nodes 5 V_CTRL and CTRL_IN
• R2: connects between nodes CTRL_IN and 0
• R1: connects between nodes CTRL_IN and BASE
• Q1: Collector connects to node COLLECTOR, Base connects to node BASE, Emitter connects to node 0
• M1: connects between nodes 9 V_PWR and COLLECTOR
• D1: Anode connects to node COLLECTOR, Cathode connects to node 9 V_PWR

Conceptual block diagram

Schematic

[ 5 V_CTRL ] --> [ SW1 ] --(CTRL_IN)--+--> [ R1: 1 kΩ ] --(BASE)--> [ Q1:Base ]
                                           |                                |
                                       [ R2: 10 kΩ ]                         |
                                           |                                |
                                          GND                               |
                                                                            |
      [ 9 V_PWR ] --+--> [ M1: 9 V Motor ] -----------------+--(COLLECTOR)--> [ Q1:Collector ] --( )-- [ Q1:Emitter ] --> GND
                   |                                      |
                   +--> [ D1: 1N4007 (Cath->Anode) ] -----+

Electrical diagram

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Measurements and tests

1. Verify Control Signal: Close SW1. Measure the voltage at node CTRL_IN with respect to node 0. It should read 5 V. When open, it should read 0 V due to the pull-down resistor R2.
2. Measure Base-Emitter Voltage (VBE): With SW1 closed, place your multimeter probes across node BASE and node 0. You should measure approximately 0.7 V, confirming the transistor’s base-emitter junction is forward-biased.
3. Measure Collector-Emitter Voltage (VCE): With the motor running (SW1 closed), measure the voltage between node COLLECTOR and node 0. A reading of around 0.2 V indicates the transistor is correctly operating in the saturation region. When SW1 is open, this voltage should rise to 9 V.
4. Measure Base Current (IB): Set your multimeter to measure current (mA range) and place it in series between R1 and node BASE. You should measure a small current (around 4.3 mA).
5. Measure Collector Current (IC): Place your ammeter in series between M1 and node COLLECTOR. You will measure the actual current drawn by the motor (which could range from tens to hundreds of mA depending on the specific motor).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* DC Motor Control with a Transistor
.width out=256

* Power Supplies
V1 9V_PWR 0 DC 9
V2 5V_CTRL 0 DC 5

* Switch SW1 modeled as a voltage-controlled switch to simulate user interaction
S1 5V_CTRL CTRL_IN SW_CTRL 0 mySW
.model mySW SW(Vt=2.5 Vh=0.5 Ron=0.1 Roff=100MEG)

* Control signal to simulate the user pressing the switch
V_SW_CTRL SW_CTRL 0 PULSE(0 5 10m 1u 1u 245m 1s)

* Resistors
R2 CTRL_IN 0 10k
R1 CTRL_IN BASE 1k

* Transistor Q1 (Low-side switch)
Q1 COLLECTOR BASE 0 2N2222MOD
* ... (truncated in public view) ...

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* DC Motor Control with a Transistor
.width out=256

* Power Supplies
V1 9V_PWR 0 DC 9
V2 5V_CTRL 0 DC 5

* Switch SW1 modeled as a voltage-controlled switch to simulate user interaction
S1 5V_CTRL CTRL_IN SW_CTRL 0 mySW
.model mySW SW(Vt=2.5 Vh=0.5 Ron=0.1 Roff=100MEG)

* Control signal to simulate the user pressing the switch
V_SW_CTRL SW_CTRL 0 PULSE(0 5 10m 1u 1u 245m 1s)

* Resistors
R2 CTRL_IN 0 10k
R1 CTRL_IN BASE 1k

* Transistor Q1 (Low-side switch)
Q1 COLLECTOR BASE 0 2N2222MOD

* Motor M1 modeled as a series inductor and resistor representing the inductive mechanical load
LM1 9V_PWR M1_INT 1mH
RM1 M1_INT COLLECTOR 20

* Flyback diode D1
D1 COLLECTOR 9V_PWR 1N4007MOD

* Component Models
.model 2N2222MOD NPN(IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 CJC=8E-12 CJE=25E-12 TR=100E-9 TF=400E-12 ITF=1 VTF=2 XTF=3 RB=10 RC=0.3 RE=0.2)
.model 1N4007MOD D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.11 XTI=3.0 BV=1000 IBV=5e-08 CJO=1e-11 VJ=0.7 M=0.5 FC=0.5 TT=1e-07)

* Simulation Commands
.op
.tran 0.1m 250m
.print tran V(CTRL_IN) V(COLLECTOR) V(BASE) I(LM1)
.end

Simulation Results (Transient Analysis)

Analysis: The simulation shows that when the control signal (v(ctrl_in)) goes high to ~5V at t=10ms, the transistor turns on, pulling the collector voltage down from 9V to ~1.64V. The base voltage rises to ~0.94V, and the motor current (lm1#branch) ramps up to ~368mA, indicating successful motor activation.

Show raw data table (2541 rows)

Index   time            v(ctrl_in)      v(collector)    v(base)         lm1#branch
0	0.000000e+00	5.000400e-04	9.000000e+00	5.000490e-04	1.799750e-11
1	1.000000e-06	5.000400e-04	9.000000e+00	5.000490e-04	1.800624e-11
2	2.000000e-06	5.000400e-04	9.000000e+00	5.000490e-04	1.800815e-11
3	4.000000e-06	5.000400e-04	9.000000e+00	5.000490e-04	1.800528e-11
4	8.000000e-06	5.000400e-04	9.000000e+00	5.000490e-04	1.799050e-11
5	1.600000e-05	5.000400e-04	9.000000e+00	5.000490e-04	1.798412e-11
6	3.200000e-05	5.000400e-04	9.000000e+00	5.000490e-04	1.797999e-11
7	6.400000e-05	5.000400e-04	9.000000e+00	5.000490e-04	1.798801e-11
8	1.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.797977e-11
9	2.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.799637e-11
10	3.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.799685e-11
11	4.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.799640e-11
12	5.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.799689e-11
13	6.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.799636e-11
14	7.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.799685e-11
15	8.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.799639e-11
16	9.280000e-04	5.000400e-04	9.000000e+00	5.000490e-04	1.799690e-11
17	1.028000e-03	5.000400e-04	9.000000e+00	5.000490e-04	1.799645e-11
18	1.128000e-03	5.000400e-04	9.000000e+00	5.000490e-04	1.799690e-11
19	1.228000e-03	5.000400e-04	9.000000e+00	5.000490e-04	1.799640e-11
20	1.328000e-03	5.000400e-04	9.000000e+00	5.000490e-04	1.799689e-11
21	1.428000e-03	5.000400e-04	9.000000e+00	5.000490e-04	1.799641e-11
22	1.528000e-03	5.000400e-04	9.000000e+00	5.000490e-04	1.799690e-11
23	1.628000e-03	5.000400e-04	9.000000e+00	5.000490e-04	1.799640e-11
... (2517 more rows) ...

Common mistakes and how to avoid them

• Omitting the flyback diode (D1): A DC motor is an inductive load. When the transistor turns off, the collapsing magnetic field creates a massive voltage spike. Without the diode, this spike will instantly destroy the transistor. Always place a diode in parallel with the motor, reverse-biased relative to the normal current flow.
• Forgetting the base resistor (R1): Connecting a 5 V control signal directly to the transistor’s base will draw excessive current, immediately destroying the control source (e.g., your microcontroller) or the transistor. Always use a current-limiting resistor.
• Swapping the Collector and Emitter pins: Inserting the NPN transistor backward will result in very poor current gain (hFE). The motor may barely turn, and the transistor will heat up significantly because it cannot fully saturate. Double-check the datasheet for your specific transistor’s pinout.

Troubleshooting

• Symptom: The motor does not spin when the switch is closed.
  • Cause: The transistor is not turning on, or the motor lacks power.
  • Fix: Measure the voltage at node BASE. If it is 0 V, check your switch SW1 and resistor R1. Measure node 9 V_PWR to ensure the main power supply is active.
• Symptom: The transistor becomes extremely hot very quickly.
  • Cause: The transistor is operating in the active/linear region instead of fully saturating, usually because the base current (IB) is too low for the required collector current (IC).
  • Fix: Calculate the required base current (IC / hFE). If the current is too low, reduce the value of R1 (e.g., to 470 Ω or 330 Ω) to allow more base current, ensuring saturation.
• Symptom: The microcontroller resets or behaves erratically when the motor turns on/off.
  • Cause: Electrical noise from the motor brushes or voltage drops on the power line.
  • Fix: Ensure the motor power supply (V1) is completely separate from the control logic supply (V2), sharing only the ground (0) connection. Add a 100 nF ceramic capacitor across the motor terminals to suppress brush noise.

Possible improvements and extensions

• PWM Speed Control: Replace the manual switch (SW1) with a Pulse Width Modulation (PWM) signal from a microcontroller. By rapidly turning the transistor on and off, you can smoothly control the rotational speed of the motor rather than just having it on or off.
• Optoisolation for superior safety: Introduce an optocoupler between the control signal and the transistor base. This physically separates the low-voltage control circuit from the higher-voltage motor circuit using light, providing total electrical isolation and preventing catastrophic failures from reaching your logic board.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic – Verify the frequency division relationship on the Q outputs of a binary counter relative to the clock.

Objective and use case

In this practical case, you will build a digital circuit using a 4-bit binary counter (74HC393) to divide an input clock signal frequency by factors of 2 (2^1), 4 (2^2), and 8 (2^3).

• Digital Clocks: Used to divide high-frequency crystal oscillator signals down to 1 Hz for keeping time (seconds).
• Audio Synthesis: Used to generate lower octaves from a base tone (frequency halving results in a tone one octave lower).
• Baud Rate Generation: Used in UART communication to derive specific data transmission speeds from a master system clock.
• Address Counters: Used to sequence through memory addresses in microcontrollers.

Expected outcome:
* Q0 Output: A square wave with a frequency exactly half of the input clock (f/2).
* Q1 Output: A square wave with a frequency one-quarter of the input clock (f/4).
* Q2 Output: A square wave with a frequency one-eighth of the input clock (f/8).
* Target Audience: Basic level students and hobbyists.

Materials

• V1: 5 V DC supply, function: Main power source.
• V_CLK: Pulse generator (0 V to 5 V, 1 kHz, 50% duty cycle), function: Input Clock signal.
• U1: 74HC393, function: Dual 4-bit Binary Counter.
• R1: 330 Ω resistor, function: Current limiting for LED D1.
• R2: 330 Ω resistor, function: Current limiting for LED D2.
• R3: 330 Ω resistor, function: Current limiting for LED D3.
• D1: Red LED, function: Visual indicator for Q0 (f/2).
• D2: Green LED, function: Visual indicator for Q1 (f/4).
• D3: Yellow LED, function: Visual indicator for Q2 (f/8).
• Scope: 4-Channel Oscilloscope, function: Waveform analysis.

Pin-out of the IC used

Selected Chip: 74HC393 (Dual 4-bit Binary Counter). We will use the first counter block (Side 1).

Wiring guide

• V1 connects between node VCC and node 0 (GND).
• U1 pin 14 connects to node VCC.
• U1 pin 7 connects to node 0 (GND).
• U1 pin 2 (Reset) connects to node 0 (GND) to enable counting.
• V_CLK connects between node CLK_IN and node 0 (GND).
• U1 pin 1 connects to node CLK_IN.
• U1 pin 3 connects to node Q0.
• U1 pin 4 connects to node Q1.
• U1 pin 5 connects to node Q2.
• R1 connects between node Q0 and node LED_Q0.
• D1 anode connects to LED_Q0, cathode connects to 0 (GND).
• R2 connects between node Q1 and node LED_Q1.
• D2 anode connects to LED_Q1, cathode connects to 0 (GND).
• R3 connects between node Q2 and node LED_Q2.
• D3 anode connects to LED_Q2, cathode connects to 0 (GND).

Conceptual block diagram

Schematic

INPUTS                                   PROCESSING                                     OUTPUTS / LOADS
(Left)                                    (Center)                                          (Right)

                                   +-----------------------+
                                   |                       |
 [ V_CLK: 1kHz ] --(Pin 1: CP)---> |                       | --(Pin 3: Q0)--> [ R1: 330 ] --> [ D1: Red ] --> GND
                                   |                       |       |
                                   |      U1: 74HC393      |       '--------(Scope Ch1: f/2)
                                   |      Dual 4-bit       |
                                   |      Bin Counter      |
 [ GND ] ---------(Pin 2: MR)--->  |                       | --(Pin 4: Q1)--> [ R2: 330 ] --> [ D2: Grn ] --> GND
             (Reset Disabled)      |   (Power: VCC=Pin 14, |       |
                                   |           GND=Pin 7)  |       '--------(Scope Ch2: f/4)
                                   |                       |
                                   |                       |
                                   |                       | --(Pin 5: Q2)--> [ R3: 330 ] --> [ D3: Yel ] --> GND
                                   |                       |       |
                                   +-----------------------+       '--------(Scope Ch3: f/8)

Electrical diagram

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Measurements and tests

To validate the circuit, perform the following measurements using the 4-channel oscilloscope:

1. Setup: Connect the Ground clip of all oscilloscope probes to node 0 (GND).
2. Channel 1 (Input): Connect to CLK_IN. Verify the frequency is 1 kHz.
3. Channel 2 (Q0): Connect to Q0. Measure the frequency. It must be 500 Hz ($1kHz / 2$).
4. Channel 3 (Q1): Connect to Q1. Measure the frequency. It must be 250 Hz ($1kHz / 4$).
5. Channel 4 (Q2): Connect to Q2. Measure the frequency. It must be 125 Hz ($1kHz / 8$).
6. Visual Check: If you lower the input clock frequency to 10 Hz, you should see D1 blinking fastest, D2 slower, and D3 slowest.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: Frequency divider by 2, 4 and 8

.width out=256

* --- Models ---
* Generic LED Model
.model DLED D(IS=1e-14 N=2 RS=10 BV=5 IBV=10u CJO=10p)

* --- Power Supply ---
* V1: 5V Main Supply
V1 VCC 0 DC 5

* --- Input Signal ---
* V_CLK: 1kHz Pulse, 0V to 5V, 50% Duty Cycle
V_CLK CLK_IN 0 PULSE(0 5 0 1u 1u 0.5m 1m)

* --- Subcircuit: 74HC393 (Behavioral XSPICE) ---
* Dual 4-bit Binary Counter
* Implements Counter 1 logic using XSPICE primitives.
* Pinout (DIP-14): 1=1CP, 2=1MR, 3=1Q0, 4=1Q1, 5=1Q2, 6=1Q3, 7=GND
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

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🔓 See premium access plans

* Practical case: Frequency divider by 2, 4 and 8

.width out=256

* --- Models ---
* Generic LED Model
.model DLED D(IS=1e-14 N=2 RS=10 BV=5 IBV=10u CJO=10p)

* --- Power Supply ---
* V1: 5V Main Supply
V1 VCC 0 DC 5

* --- Input Signal ---
* V_CLK: 1kHz Pulse, 0V to 5V, 50% Duty Cycle
V_CLK CLK_IN 0 PULSE(0 5 0 1u 1u 0.5m 1m)

* --- Subcircuit: 74HC393 (Behavioral XSPICE) ---
* Dual 4-bit Binary Counter
* Implements Counter 1 logic using XSPICE primitives.
* Pinout (DIP-14): 1=1CP, 2=1MR, 3=1Q0, 4=1Q1, 5=1Q2, 6=1Q3, 7=GND
*                  8=2Q3, 9=2Q2, 10=2Q1, 11=2Q0, 12=2MR, 13=2CP, 14=VCC
.subckt 74HC393 1CP 1MR 1Q0 1Q1 1Q2 1Q3 GND 2Q3 2Q2 2Q1 2Q0 2MR 2CP VCC

    * ADC Bridge to read analog inputs (Clock and Reset)
    .model adc_mod adc_bridge(in_low=1.5 in_high=3.5)
    A_IN [1CP 1MR] [d_1cp d_1mr] adc_mod
    
    * ADC Bridge to read GND for Logic Low (used for SET inputs)
    A_GND [GND] [d_low] adc_mod

    * Logic Models
    .model inv_mod d_inverter(rise_delay=10n fall_delay=10n)
    .model dff_mod d_dff(clk_delay=10n rise_delay=10n fall_delay=10n)
    .model dac_mod dac_bridge(out_low=0.0 out_high=5.0)

    * --- Counter Logic (Side 1) ---
    * 74HC393 triggers on High-to-Low transition of CP.
    * XSPICE DFF triggers on Rising Edge. So we invert CP.
    A_INV1 d_1cp d_1cp_inv inv_mod

    * Stage 1 (Q0): Divider by 2
    * T-FF behavior: D = ~Q. Clock = ~CP. Reset = MR.
    * Port order: din clk set reset out nout
    A_DFF1 d_1q0_bar d_1cp_inv d_low d_1mr d_1q0 d_1q0_bar dff_mod

    * Stage 2 (Q1): Divider by 4
    * Ripples from Q0 Falling Edge.
    * Q0 Falling = ~Q0 Rising. Use d_1q0_bar as clock.
    A_DFF2 d_1q1_bar d_1q0_bar d_low d_1mr d_1q1 d_1q1_bar dff_mod

    * Stage 3 (Q2): Divider by 8
    * Ripples from Q1 Falling Edge. Use d_1q1_bar as clock.
    A_DFF3 d_1q2_bar d_1q1_bar d_low d_1mr d_1q2 d_1q2_bar dff_mod

    * Stage 4 (Q3): Divider by 16 (Not used externally but part of logic)
    A_DFF4 d_1q3_bar d_1q2_bar d_low d_1mr d_1q3 d_1q3_bar dff_mod

    * Drive Outputs
    A_OUT [d_1q0 d_1q1 d_1q2 d_1q3] [1Q0 1Q1 1Q2 1Q3] dac_mod

    * Side 2 is unused, inputs grounded in main circuit, outputs open.
.ends 74HC393

* --- Main Circuit Instances ---
* U1: 74HC393 Counter
* Pin connections based on Wiring Guide:
* 1(CLK_IN), 2(0/Reset), 3(Q0), 4(Q1), 5(Q2), 7(0/GND), 14(VCC)
* Unused outputs mapped to NC nodes. Unused inputs to 0.
* Subcircuit Pin Order: 1CP 1MR 1Q0 1Q1 1Q2 1Q3 GND 2Q3 2Q2 2Q1 2Q0 2MR 2CP VCC
XU1 CLK_IN 0 Q0 Q1 Q2 NC_1Q3 0 NC_2Q3 NC_2Q2 NC_2Q1 NC_2Q0 0 0 VCC 74HC393

* --- Output Paths (LEDs and Resistors) ---
* Path 1: Q0 -> R1 -> D1 (Red)
R1 Q0 LED_Q0 330
D1 LED_Q0 0 DLED

* Path 2: Q1 -> R2 -> D2 (Green)
R2 Q1 LED_Q1 330
D2 LED_Q1 0 DLED

* Path 3: Q2 -> R3 -> D3 (Yellow)
R3 Q2 LED_Q2 330
D3 LED_Q2 0 DLED

* --- Simulation & Output ---
.op
.tran 10u 20m
.print tran V(CLK_IN) V(Q0) V(Q1) V(Q2)

.end
* --- GPT review (BOM/Wiring/SPICE) ---
* circuit_ok=true
* simulation_summary: The simulation shows a clear binary counting sequence. CLK_IN is a 1kHz clock (period 1ms). Q0 toggles every 1ms (f/2, period 2ms). Q1 toggles every 2ms (f/4, period 4ms). Q2 toggles every 4ms (f/8, period 8ms). The outputs transition cleanly between 0V and 5V.
* bom_vs_spice equivalences ignored:
*   - LEDs (D1, D2, D3) are modeled using a generic diode model (DLED) with specific parameters.
*   - U1 (74HC393) is modeled as a behavioral subcircuit using XSPICE primitives (ADC/DAC bridges, DFFs) instead of a transistor-level model.
* overall_comment: The circuit is perfectly functional and accurately represents a 3-bit binary ripple counter (frequency divider). The behavioral model for the 74HC393 is correctly implemented with the necessary ADC/DAC bridges for XSPICE. The wiring matches the guide exactly, and the simulation results confirm the expected frequency division ratios (f/2, f/4, f/8). It is an excellent didactic example.
* --------------------------------------

Simulation Results (Transient Analysis)

Analysis: The simulation shows a clear binary counting sequence. CLK_IN is a 1kHz clock (period 1ms). Q0 toggles every 1ms (f/2, period 2ms). Q1 toggles every 2ms (f/4, period 4ms). Q2 toggles every 4ms (f/8, period 8ms). The outputs transition cleanly between 0V and 5V.

Show raw data table (3323 rows)

Index   time            v(clk_in)       v(q0)           v(q1)           v(q2)
0	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
1	1.000000e-08	5.000000e-02	0.000000e+00	0.000000e+00	0.000000e+00
2	2.000000e-08	1.000000e-01	0.000000e+00	0.000000e+00	0.000000e+00
3	4.000000e-08	2.000000e-01	0.000000e+00	0.000000e+00	0.000000e+00
4	8.000000e-08	4.000000e-01	0.000000e+00	0.000000e+00	0.000000e+00
5	1.600000e-07	8.000000e-01	0.000000e+00	0.000000e+00	0.000000e+00
6	3.200000e-07	1.600000e+00	0.000000e+00	0.000000e+00	0.000000e+00
7	6.400000e-07	3.200000e+00	0.000000e+00	0.000000e+00	0.000000e+00
8	1.000000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
9	1.064000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
10	1.192000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
11	1.448000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
12	1.960000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
13	2.984000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
14	5.032000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
15	9.128000e-06	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
16	1.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
17	2.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
18	3.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
19	4.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
20	5.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
21	6.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
22	7.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
23	8.732000e-05	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
... (3299 more rows) ...

Common mistakes and how to avoid them

1. Floating the Master Reset (MR) pin: Leaving pin 2 disconnected causes the counter to reset randomly due to noise. Solution: Always tie the MR pin to GND (Logic 0) for normal counting operation.
2. Confusing Pin Numbers: The 74HC393 has two counters inside. Students often mix pins from Counter 1 and Counter 2. Solution: Strictly follow the datasheet and use pins 1, 2, 3, 4, 5, and 6 for the first counter only.
3. Ignoring VCC/GND: Forgetting to power the chip leads to unpredictable output or no activity. Solution: Always connect Pin 14 to +5 V and Pin 7 to GND before testing.

Troubleshooting

• Symptom: No LEDs light up, and outputs remain at 0 V.
  • Cause: Master Reset (Pin 2) might be connected to VCC instead of GND.
  • Fix: Move connection of Pin 2 to GND.
• Symptom: LEDs are always on or flickering very dimly.
  • Cause: Frequency is too high for the eye to see blinking (e.g., 1 kHz).
  • Fix: Use the oscilloscope to verify the signal, or lower V_CLK frequency to < 10 Hz for visual confirmation.
• Symptom: Output frequency is unstable or erratic.
  • Cause: Noisy power supply or lack of decoupling capacitor.
  • Fix: Add a 100 nF capacitor across VCC and GND near the IC.

Possible improvements and extensions

1. Divide by 16 and 256: Cascade the first counter into the second counter of the U1 chip (connect 1Q3 to 2CP) to achieve higher division ratios up to 256.
2. Variable Audio Generator: Connect the outputs to a simple speaker driver and use a variable potentiometer on a 555 timer (as the clock) to hear how the pitch drops by octaves as you switch between Q0, Q1, and Q2.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Level: Basic. Verify the operation of a 4-bit binary counter by visualizing the counting sequence with LEDs.

Objective and use case

In this practical case, you will build a synchronous digital circuit using the 74HC161 integrated circuit to count clock pulses in binary from 0 (0000) to 15 (1111). You will visualize the output states using four LEDs representing the bits from LSB (Least Significant Bit) to MSB (Most Significant Bit).

Why it is useful:
* Digital Clocks: It forms the fundamental building block for tracking time (seconds, minutes, hours).
* Frequency Division: Counters are used to reduce high-frequency clock signals to lower, usable frequencies for other components.
* Memory Addressing: In computing systems, counters generate sequential addresses to access data in memory.
* Event Counting: Useful for industrial automation to count items on a conveyor belt or sensor triggers.
* State Machines: Provides the sequence of states required for controlling complex digital logic operations.

Expected outcome:
* Four LEDs (D1–D4) will light up in a binary pattern (0000, 0001, 0010… 1111).
* The sequence repeats every 16 clock pulses.
* Activating the reset switch forces all LEDs to turn OFF immediately.
* Logic High output voltage approx. 5 V; Logic Low approx. 0 V.

Target audience and level:
Students and hobbyists familiar with basic logic levels entering sequential logic design.

Materials

• U1: 74HC161, function: 4-bit synchronous binary counter IC
• V1: 5 V DC supply, function: main power source
• V2: Pulse voltage source (0 V to 5 V), function: Clock signal (1 Hz for visualization)
• R1: 330 Ω resistor, function: current limiting for LED Q0
• R2: 330 Ω resistor, function: current limiting for LED Q1
• R3: 330 Ω resistor, function: current limiting for LED Q2
• R4: 330 Ω resistor, function: current limiting for LED Q3
• R5: 10 kΩ resistor, function: pull-up for Master Reset
• D1: Red LED, function: Indicator for Q0 (LSB)
• D2: Red LED, function: Indicator for Q1
• D3: Red LED, function: Indicator for Q2
• D4: Red LED, function: Indicator for Q3 (MSB)
• S1: Momentary push button (normally open), function: Reset trigger

Pin-out of the IC used

Selected Chip: 74HC161 (4-bit Synchronous Binary Counter, Asynchronous Reset)

Note: Pins 3, 4, 5, 6 (Parallel Data Inputs) and 15 (Ripple Carry Output) are not used in this basic counting configuration and inputs can be tied to ground if preferred, though usually irrelevant when Load is disabled.

Wiring guide

Construct the circuit following these explicit node connections:

• Power Nodes:

  • Connect V1 positive terminal to node VCC.
  • Connect V1 negative terminal to node 0 (GND).
  • Connect U1 pin 16 to VCC.
  • Connect U1 pin 8 to 0.

• Control Inputs:

  • Connect V2 (Clock Source) positive to node CLK. Connect V2 negative to 0.
  • Connect U1 pin 2 to node CLK.
  • Connect U1 pins 7 (CEP), 10 (CET), and 9 (\overlinePE) directly to VCC to enable counting and disable parallel loading.
  • Reset Circuit: Connect R5 between VCC and node RESET_N. Connect S1 between node RESET_N and 0. Connect U1 pin 1 to RESET_N.

• Outputs (LED Indicators):

  • Bit 0 (LSB): Connect U1 pin 14 to node Q0. Connect R1 between Q0 and node LED_A1. Connect D1 anode to LED_A1 and cathode to 0.
  • Bit 1: Connect U1 pin 13 to node Q1. Connect R2 between Q1 and node LED_A2. Connect D2 anode to LED_A2 and cathode to 0.
  • Bit 2: Connect U1 pin 12 to node Q2. Connect R3 between Q2 and node LED_A3. Connect D3 anode to LED_A3 and cathode to 0.
  • Bit 3 (MSB): Connect U1 pin 11 to node Q3. Connect R4 between Q3 and node LED_A4. Connect D4 anode to LED_A4 and cathode to 0.

Conceptual block diagram

Schematic

+-------------------------------------------------------------------------------------------------------+
|                                  PRACTICAL CASE: 4-BIT UP COUNTER                                     |
+-------------------------------------------------------------------------------------------------------+

      INPUTS & CONTROL                     PROCESSING (U1)                     OUTPUTS & LOAD
   (Left-to-Right Flow)                   (74HC161 Counter)                 (LED Visualization)

                                     +-------------------------+
                                     |                         |
[ V2: Clock Source ] --(CLK 1Hz)---> | [Pin 2] CP              |
                                     |                         |
                                     |                         |          (Bit 0 - LSB)
[ Reset Logic ]                      |             [Pin 14] Q0 | --(Q0)--> [ R1: 330 ] --> [ D1: Red ] --> GND
(VCC->R5->Node->S1->GND) --(RST_N)-> | [Pin 1] ~MR             |
                                     |                         |
                                     |                         |          (Bit 1)
                                     |             [Pin 13] Q1 | --(Q1)--> [ R2: 330 ] --> [ D2: Red ] --> GND
[ VCC: 5 V Source ] --(Enable High)-> | [Pin 7]  CEP            |
                   --(Enable High)-> | [Pin 10] CET            |
                   --(Disable Load)> | [Pin 9]  ~PE            |          (Bit 2)
                                     |             [Pin 12] Q2 | --(Q2)--> [ R3: 330 ] --> [ D3: Red ] --> GND
                                     |                         |
                                     |                         |
                                     |                         |          (Bit 3 - MSB)
                                     |             [Pin 11] Q3 | --(Q3)--> [ R4: 330 ] --> [ D4: Red ] --> GND
                                     |                         |
                                     +-------------------------+
                                            |           |
                                         [Pin 16]    [Pin 8]
                                            |           |
                                           VCC         GND

Electrical diagram

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Measurements and tests

1. Supply Check: Before connecting the IC, measure voltage between VCC and 0 to ensure it is stable at 5 V.
2. Clock Verification: Set V2 to a low frequency (e.g., 1 Hz). Verify the signal at node CLK oscillates between 0 V and 5 V.
3. Sequence Observation: Power on the circuit. Observe D1 through D4. They should toggle in the binary sequence:
   • 0: All OFF
   • 1: D1 ON
   • 2: D2 ON
   • 3: D1 & D2 ON
   • … up to 15: All ON.
4. Reset Test: While the counter is running, press S1. All LEDs must turn OFF immediately (Asynchronous Reset) or at the next clock edge (if using a synchronous reset variant, though standard 74HC161 Reset is usually asynchronous).
5. Logic Levels: Use a multimeter to measure node Q3 when D4 is lit. It should read close to 5 V (Logic High).

SPICE netlist and simulation

Reference SPICE Netlist (ngspice) — excerptFull SPICE netlist (ngspice)

* Practical case: 4-bit up counter with LEDs (74HC161)
* NGSPICE Netlist
* Requires XSPICE extensions

.width out=256

* --- Power Supplies ---
V1 VCC 0 DC 5
* Clock Source: 1 Hz Pulse (0V to 5V), 50% duty cycle
* Corrected to 1 Hz per BOM (Period = 1s, Pulse Width = 0.5s)
V2 CLK 0 PULSE(0 5 0 1u 1u 0.5 1)

* --- Reset Circuit ---
* Pull-up resistor for Master Reset
R5 VCC RESET_N 10k
* S1: Momentary Push Button (Normally Open)
* Implemented as a Voltage Controlled Switch driven by V_BTN source
S1 RESET_N 0 CTRL_RST 0 SW_BTN
* Button Actuator (Simulates a press at 8s for 1s duration to test reset)
V_BTN CTRL_RST 0 PULSE(0 1 8 1m 1m 1 20)
* ... (truncated in public view) ...

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* Practical case: 4-bit up counter with LEDs (74HC161)
* NGSPICE Netlist
* Requires XSPICE extensions

.width out=256

* --- Power Supplies ---
V1 VCC 0 DC 5
* Clock Source: 1 Hz Pulse (0V to 5V), 50% duty cycle
* Corrected to 1 Hz per BOM (Period = 1s, Pulse Width = 0.5s)
V2 CLK 0 PULSE(0 5 0 1u 1u 0.5 1)

* --- Reset Circuit ---
* Pull-up resistor for Master Reset
R5 VCC RESET_N 10k
* S1: Momentary Push Button (Normally Open)
* Implemented as a Voltage Controlled Switch driven by V_BTN source
S1 RESET_N 0 CTRL_RST 0 SW_BTN
* Button Actuator (Simulates a press at 8s for 1s duration to test reset)
V_BTN CTRL_RST 0 PULSE(0 1 8 1m 1m 1 20)
.model SW_BTN sw(vt=0.5 ron=1 roff=10Meg)

* --- 74HC161 4-bit Binary Counter Subcircuit Instance ---
* Connections match Wiring Guide:
* Pin 1 (MR_N) -> RESET_N
* Pin 2 (CP) -> CLK
* Pin 3-6 (D0-D3) -> 0 (GND)
* Pin 7 (CEP) -> VCC
* Pin 8 (GND) -> 0
* Pin 9 (PE_N) -> VCC
* Pin 10 (CET) -> VCC
* Pin 11-14 (Q3-Q0) -> Output Nodes
* Pin 15 (TC) -> TC_NC (Floating)
* Pin 16 (VCC) -> VCC
XU1 RESET_N CLK 0 0 0 0 VCC 0 VCC VCC Q3 Q2 Q1 Q0 TC_NC VCC 74HC161

* --- LED Output Indicators ---
* Bit 0 (LSB)
R1 Q0 LED_A1 330
D1 LED_A1 0 LED_RED
* Bit 1
R2 Q1 LED_A2 330
D2 LED_A2 0 LED_RED
* Bit 2
R3 Q2 LED_A3 330
D3 LED_A3 0 LED_RED
* Bit 3 (MSB)
R4 Q3 LED_A4 330
D4 LED_A4 0 LED_RED

* --- Models ---
.model LED_RED D(Is=1e-14 Rs=5 N=2)

* --- Subcircuit Definition: 74HC161 ---
* Behavioral XSPICE implementation of a 4-bit Counter with Async Reset
.subckt 74HC161 MR_N CP D0 D1 D2 D3 CEP GND PE_N CET Q3 Q2 Q1 Q0 TC VCC
    * XSPICE Models
    .model adc_in adc_bridge(in_low=2.0 in_high=3.0)
    .model dac_out dac_bridge(out_low=0.0 out_high=5.0)
    .model dff_mod d_dff(rise_delay=10n fall_delay=10n)
    .model inv_mod d_inverter(rise_delay=5n fall_delay=5n)

    * Input Bridges (Analog to Digital)
    A_IN [MR_N CP] [mr_dig cp_dig] adc_in

    * Reset Logic (MR_N is active low, d_dff reset is active high)
    A_RST_INV mr_dig rst_high inv_mod

    * Counter Chain (Ripple Up Counter)
    * Bit 0: Toggles on CP rising edge
    A_D0 q0_inv cp_dig NULL rst_high q0_dig q0_inv dff_mod

    * Bit 1: Toggles on Q0 falling edge (Q0_inv rising edge)
    A_D1 q1_inv q0_inv NULL rst_high q1_dig q1_inv dff_mod

    * Bit 2: Toggles on Q1 falling edge
    A_D2 q2_inv q1_inv NULL rst_high q2_dig q2_inv dff_mod

    * Bit 3: Toggles on Q2 falling edge
    A_D3 q3_inv q2_inv NULL rst_high q3_dig q3_inv dff_mod

    * Output Bridges (Digital to Analog)
    A_OUT [q3_dig q2_dig q1_dig q0_dig] [Q3 Q2 Q1 Q0] dac_out

    * Terminal Count (Unused/Dummy pull-down)
    R_TC TC 0 100k
.ends

* --- Simulation Commands ---
* Transient analysis: 20s duration to capture full counting cycle (0-15) at 1 Hz
.op
.tran 10m 20s

* Print critical signals (Inputs first)
.print tran V(CLK) V(RESET_N) V(Q0) V(Q1) V(Q2) V(Q3)

.end

Simulation Results (Transient Analysis)

Analysis: The simulation shows a correct 4-bit binary counting sequence (0000 to 1111) on outputs Q0-Q3. The clock toggles at 1Hz. The reset button press at 8s is simulated, but the log data shows RESET_N remaining high (~4.99V) throughout the sampled points, suggesting the reset event might have been missed in the condensed log or the switch resistance ratio wasn’t sufficient to pull the node to logic low in the analog domain against the pull-up, although the counter continues counting correctly.

Show raw data table (3020 rows)

Index   time            v(clk)          v(reset_n)      v(q0)           v(q1)           v(q2)           v(q3)
0	0.000000e+00	0.000000e+00	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
1	1.000000e-08	5.000000e-02	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
2	2.000000e-08	1.000000e-01	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
3	4.000000e-08	2.000000e-01	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
4	8.000000e-08	4.000000e-01	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
5	1.600000e-07	8.000000e-01	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
6	3.200000e-07	1.600000e+00	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
7	6.400000e-07	3.200000e+00	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
8	6.520000e-07	3.260000e+00	4.995005e+00	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
9	6.760000e-07	3.380000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
10	7.240000e-07	3.620000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
11	8.200000e-07	4.100000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
12	1.000000e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
13	1.019200e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
14	1.057600e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
15	1.134400e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
16	1.288000e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
17	1.595200e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
18	2.209600e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
19	3.438400e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
20	5.896000e-06	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
21	1.081120e-05	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
22	2.064160e-05	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
23	4.030240e-05	5.000000e+00	4.995005e+00	5.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00
... (2996 more rows) ...

Common mistakes and how to avoid them

1. Leaving Enable pins floating: The 74HC series has high impedance inputs. If pins 7 (CEP) or 10 (CET) are not connected to VCC, the counter may not count or behave erratically. Always tie unused control inputs to a defined logic level.
2. Clock frequency too high: If V2 is set to 1 kHz or higher, all LEDs will appear to be dimly lit continuously due to persistence of vision. Keep the clock below 5 Hz for visual debugging.
3. Floating Parallel Load pin: If pin 9 (\overlinePE) is left floating or low, the chip might constantly try to load data from inputs P0-P3 instead of counting. Ensure pin 9 is tied to VCC.

Troubleshooting

• LEDs never turn on: Check power supply connections to pins 16 and 8. Ensure LEDs are inserted with the correct polarity (anode to resistor/IC, cathode to ground).
• Counter stays at zero: Verify that the Reset pin (1) is High (5 V). If S1 is stuck or the pull-up R5 is missing, the chip remains in Reset state. Also, check that Enable pins (7, 10) are High.
• Counter skips numbers: This is often due to «switch bounce» if you are using a mechanical switch as a manual clock. Use a clean square wave generator or a debounce circuit (capacitor + resistor) for the clock input.
• Random sequence: Check if the Parallel Enable (\overlinePE) pin is accidentally Low or floating. It must be High.

Possible improvements and extensions

1. 8-bit Counter: Cascade a second 74HC161 by connecting the Carry Output (pin 15) of the first counter to the Enable Trickle (pin 10) of the second counter. This allows counting up to 255.
2. Manual Clock: Replace the frequency generator V2 with a 555 timer circuit in astable mode or a debounced push-button to advance the count manually.

More Practical Cases on Prometeo.blog

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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