Practical case: Object Tracking on Zybo Z7-20+Pcam 5C IMX219

Objective and use case

What you’ll build: This project involves creating a real-time object tracking system using the Digilent Zybo Z7-20 FPGA and the Pcam 5C camera. The system will process video frames via MIPI-CSI2 and display results over HDMI.

Why it matters / Use cases

• Enhancing surveillance systems by enabling automatic detection and tracking of moving objects in real-time.
• Implementing smart robotics applications where object tracking is essential for navigation and interaction.
• Facilitating augmented reality experiences by overlaying digital information on tracked objects.
• Supporting industrial automation where tracking of parts or products is necessary for quality control.

Expected outcome

• Achieve a frame processing rate of at least 30 FPS for real-time tracking.
• Maintain a latency of under 50 milliseconds from camera input to HDMI output.
• Successfully track multiple objects with an accuracy of over 85% in varied lighting conditions.
• Utilize less than 70% of the FPGA resources for the tracking algorithm, ensuring scalability for additional features.

Audience: Engineers and developers interested in FPGA applications; Level: Intermediate to advanced

Architecture/flow: The system architecture includes a camera interfacing via MIPI-CSI2, processing in the FPGA’s programmable logic, and output through HDMI.

Advanced FPGA Practical: MIPI-CSI2 to HDMI Object Tracking on Digilent Zybo Z7-20 + Digilent Pcam 5C (IMX219)

This hands-on case builds a full hardware video pipeline on a Xilinx Zynq-7000 FPGA (Digilent Zybo Z7-20) to ingest camera frames via MIPI-CSI2 from a Digilent Pcam 5C (Sony IMX219), perform real-time object tracking (color-based) in the programmable logic, overlay a bounding box, and output the result over HDMI. The design uses a mix of Xilinx and Digilent IP, custom Verilog processing cores, and a minimal bare-metal application on the PS (ARM) to configure the sensor over I2C and set algorithm parameters.

You will build the bitstream with Vivado WebPACK (CLI), export the hardware, build and run a Vitis bare-metal app to initialize the IMX219 and drive AXI-Lite registers for the tracking overlay.

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Prerequisites

• Host OS: Ubuntu 22.04 LTS 64-bit (tested)
• Xilinx Vivado Design Suite 2023.2 WebPACK installed at /opt/Xilinx/Vivado/2023.2
• Xilinx Vitis 2023.2 installed at /opt/Xilinx/Vitis/2023.2
• Xilinx cable drivers installed (for JTAG/UART via Digilent USB)
• Git 2.34+ and Make 4.3+
• Python 3.10+ (for helper scripts, optional)
• A serial terminal (e.g., picocom or minicom) configured for 115200 8N1 on the Zybo USB UART
• A 1080p HDMI monitor and an HDMI cable
• Internet access to clone the Digilent repositories
• Optional but recommended: a tripod or stable stand for the Pcam 5C so you can move a colored object in front of it for validation

Note: The Xilinx MIPI D-PHY and MIPI CSI-2 RX Subsystem IPs may require an evaluation license in Vivado. You can generate an evaluation license in the Xilinx Licensing Manager. Vivado WebPACK supports building the Zynq-7000 design; the MIPI IPs run in evaluation mode for lab use.

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Materials (exact model)

• Digilent Zybo Z7-20 (Zynq-7000, xc7z020clg400-1)
• Digilent Pcam 5C (Sony IMX219 sensor)
• 5 V power supply for Zybo Z7-20 (if not powering from USB)
• Micro USB cable (for UART/JTAG)
• HDMI cable
• microSD card (>= 8 GB) if you want to boot from SD later; JTAG-only is fine for this lab

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Setup / Connection

• Power off the board when making connections.
• Mount the Digilent Pcam 5C to the Zybo Z7-20 Pcam connector (MIPI CSI-2) observing proper orientation. The connector is keyed; do not force it.
• Connect an HDMI cable from Zybo Z7-20 HDMI OUT to a 1080p monitor.
• Connect Micro USB to your host (this gives you JTAG and UART).
• Set jumpers:
• JP5 (Power Source) to USB or WALL as appropriate.
• JP2 to JTAG for development (programming via Vivado). You can move to SD later if you prefer standalone boot.
• Power on the board only when instructed during programming steps.
• UART: point your serial terminal at the enumerated ttyUSBx (likely /dev/ttyUSB1 for UART on Linux) at 115200 8N1.

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Architecture Overview

• CSI-2 RX path: MIPI D-PHY + MIPI CSI-2 RX Subsystem (2 lanes) captures RAW10 from IMX219.
• Demosaic: convert Bayer RAW10 to 24-bit RGB (8:8:8).
• Processing pipeline (all AXI4-Stream):
• axis_color_thresh: produce a binary mask of pixels matching a target color range.
• axis_bbox_tracker: compute bounding box of the largest blob in the mask (frame-by-frame).
• axis_bbox_overlay: draw a colored rectangle on the RGB video per computed bounding box.
• Video out:
• v_axi4s_vid_out + vtc to HDMI timing.
• rgb2dvi (Digilent) to drive TMDS (HDMI OUT).
• Control:
• PS (C bare-metal via Vitis) initializes IMX219 via AXI IIC and sets AXI-Lite registers for thresholds; reads back bbox for UART debug.

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IP Blocks and Roles (summary)

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Full Code

Below are the core custom Verilog modules for object-tracking and overlay. They operate on AXI4-Stream Video (tdata[23:0] RGB, tvalid, tready, tlast for EOL, tuser for SOF).

1) axis_color_thresh.v

• AXI4-Stream in/out (RGB888)
• AXI-Lite for thresholds: r_min, r_max, g_min, g_max, b_min, b_max
• Outputs a side-channel tuser bit [0] as SOF; mask is driven on tdata[0] bit of a parallel stream, or we keep two streams. To keep compatibility we produce both RGB passthrough and a single-bit mask on TUSER[1] for downstream tracker.

module axis_color_thresh #(
  parameter integer C_S_AXI_ADDR_WIDTH = 6,
  parameter integer C_S_AXI_DATA_WIDTH = 32
)(
  input  wire                     aclk,
  input  wire                     aresetn,

  // AXIS Video In (RGB888)
  input  wire [23:0]              s_axis_tdata,
  input  wire                     s_axis_tvalid,
  output wire                     s_axis_tready,
  input  wire                     s_axis_tlast,   // EOL
  input  wire                     s_axis_tuser,   // SOF

  // AXIS Video Out (RGB888 + mask in TUSER[1])
  output wire [23:0]              m_axis_tdata,
  output wire                     m_axis_tvalid,
  input  wire                     m_axis_tready,
  output wire                     m_axis_tlast,
  output wire [1:0]               m_axis_tuser,   // [0]=SOF passthrough, [1]=mask

  // AXI4-Lite for thresholds
  input  wire                     s_axi_aclk,
  input  wire                     s_axi_aresetn,
  input  wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
  input  wire                     s_axi_awvalid,
  output wire                     s_axi_awready,
  input  wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
  input  wire [3:0]               s_axi_wstrb,
  input  wire                     s_axi_wvalid,
  output wire                     s_axi_wready,
  output wire [1:0]               s_axi_bresp,
  output wire                     s_axi_bvalid,
  input  wire                     s_axi_bready,
  input  wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
  input  wire                     s_axi_arvalid,
  output wire                     s_axi_arready,
  output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
  output wire [1:0]               s_axi_rresp,
  output wire                     s_axi_rvalid,
  input  wire                     s_axi_rready
);

  // Simple AXI-Stream passthrough handshake
  assign s_axis_tready = m_axis_tready;
  assign m_axis_tvalid = s_axis_tvalid;
  assign m_axis_tdata  = s_axis_tdata; // RGB passthrough
  assign m_axis_tlast  = s_axis_tlast;

  // AXI-Lite simple register bank
  reg [7:0] rmin=8'd0, rmax=8'd255, gmin=8'd0, gmax=8'd255, bmin=8'd0, bmax=8'd255;
  // AXI-Lite write/read (concise; production should use a proper AXI-Lite slave)
  reg awready=0, wready=0, bvalid=0, arready=0, rvalid=0;
  reg [31:0] rdata=0;
  assign s_axi_awready = awready;
  assign s_axi_wready  = wready;
  assign s_axi_bresp   = 2'b00;
  assign s_axi_bvalid  = bvalid;
  assign s_axi_arready = arready;
  assign s_axi_rdata   = rdata;
  assign s_axi_rresp   = 2'b00;
  assign s_axi_rvalid  = rvalid;

  // address map:
  // 0x00 rmin, 0x04 rmax, 0x08 gmin, 0x0C gmax, 0x10 bmin, 0x14 bmax
  always @(posedge s_axi_aclk) begin
    if (!s_axi_aresetn) begin
      awready<=0; wready<=0; bvalid<=0; arready<=0; rvalid<=0;
      rmin<=0; rmax<=8'hFF; gmin<=0; gmax<=8'hFF; bmin<=0; bmax<=8'hFF;
    end else begin
      // Write
      if (!awready && s_axi_awvalid) awready<=1;
      if (!wready && s_axi_wvalid)   wready<=1;
      if (awready && wready && !bvalid) begin
        awready<=0; wready<=0; bvalid<=1;
        case (s_axi_awaddr[5:2])
          4'h0: rmin <= s_axi_wdata[7:0];
          4'h1: rmax <= s_axi_wdata[7:0];
          4'h2: gmin <= s_axi_wdata[7:0];
          4'h3: gmax <= s_axi_wdata[7:0];
          4'h4: bmin <= s_axi_wdata[7:0];
          4'h5: bmax <= s_axi_wdata[7:0];
          default: ;
        endcase
      end
      if (bvalid && s_axi_bready) bvalid<=0;
      // Read
      if (!arready && s_axi_arvalid) begin
        arready<=1; rvalid<=1;
        case (s_axi_araddr[5:2])
          4'h0: rdata <= {24'd0, rmin};
          4'h1: rdata <= {24'd0, rmax};
          4'h2: rdata <= {24'd0, gmin};
          4'h3: rdata <= {24'd0, gmax};
          4'h4: rdata <= {24'd0, bmin};
          4'h5: rdata <= {24'd0, bmax};
          default: rdata <= 32'd0;
        endcase
      end else begin
        arready<=0;
      end
      if (rvalid && s_axi_rready) rvalid<=0;
    end
  end

  // Compute mask
  wire [7:0] r = s_axis_tdata[23:16];
  wire [7:0] g = s_axis_tdata[15:8];
  wire [7:0] b = s_axis_tdata[7:0];
  wire in_r = (r >= rmin) && (r <= rmax);
  wire in_g = (g >= gmin) && (g <= gmax);
  wire in_b = (b >= bmin) && (b <= bmax);
  wire mask = in_r & in_g & in_b;

  // TUSER[0]=SOF passthrough, [1]=mask
  assign m_axis_tuser = {mask, s_axis_tuser};

endmodule

2) axis_bbox_tracker.v

• Consumes the stream with mask in TUSER[1]
• Tracks min/max x, y where mask=1 per frame
• Exposes AXI-Lite readable registers for the latest bbox
• On SOF, resets running bbox; on end-of-frame, latches results for the next frame consumers

module axis_bbox_tracker #(
  parameter integer WIDTH  = 1920,
  parameter integer HEIGHT = 1080,
  parameter integer C_S_AXI_ADDR_WIDTH = 6,
  parameter integer C_S_AXI_DATA_WIDTH = 32
)(
  input  wire                     aclk,
  input  wire                     aresetn,

  // AXIS Video In (RGB passthrough; we only inspect tuser for mask)
  input  wire [23:0]              s_axis_tdata,
  input  wire                     s_axis_tvalid,
  output wire                     s_axis_tready,
  input  wire                     s_axis_tlast,
  input  wire [1:0]               s_axis_tuser,   // [0]=SOF, [1]=mask

  // AXIS Video Out (pass-through)
  output wire [23:0]              m_axis_tdata,
  output wire                     m_axis_tvalid,
  input  wire                     m_axis_tready,
  output wire                     m_axis_tlast,
  output wire [1:0]               m_axis_tuser,

  // AXI4-Lite for reading bbox
  input  wire                     s_axi_aclk,
  input  wire                     s_axi_aresetn,
  input  wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
  input  wire                     s_axi_awvalid,
  output wire                     s_axi_awready,
  input  wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
  input  wire [3:0]               s_axi_wstrb,
  input  wire                     s_axi_wvalid,
  output wire                     s_axi_wready,
  output wire [1:0]               s_axi_bresp,
  output wire                     s_axi_bvalid,
  input  wire                     s_axi_bready,
  input  wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
  input  wire                     s_axi_arvalid,
  output wire                     s_axi_arready,
  output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
  output wire [1:0]               s_axi_rresp,
  output wire                     s_axi_rvalid,
  input  wire                     s_axi_rready
);

  // Pass-through
  assign s_axis_tready = m_axis_tready;
  assign m_axis_tvalid = s_axis_tvalid;
  assign m_axis_tdata  = s_axis_tdata;
  assign m_axis_tlast  = s_axis_tlast;
  assign m_axis_tuser  = s_axis_tuser;

  // Pixel coordinate counters
  reg [15:0] x=0, y=0;
  wire sof = s_axis_tvalid && s_axis_tuser[0];
  wire eol = s_axis_tvalid && s_axis_tlast;
  wire mask = s_axis_tvalid && s_axis_tuser[1];

  always @(posedge aclk) begin
    if (!aresetn) begin
      x<=0; y<=0;
    end else if (s_axis_tvalid && s_axis_tready) begin
      if (sof) begin
        x<=0; y<=0;
      end else if (eol) begin
        x<=0;
        if (y==HEIGHT-1) y<=0; else y<=y+1;
      end else begin
        if (x==WIDTH-1) x<=0; else x<=x+1;
      end
    end
  end

  // Running bbox for current frame
  reg [15:0] cur_minx, cur_miny, cur_maxx, cur_maxy;
  reg cur_valid;

  always @(posedge aclk) begin
    if (!aresetn) begin
      cur_minx<=16'hFFFF; cur_miny<=16'hFFFF; cur_maxx<=0; cur_maxy<=0; cur_valid<=0;
    end else if (s_axis_tvalid && s_axis_tready) begin
      if (sof) begin
        cur_minx<=16'hFFFF; cur_miny<=16'hFFFF; cur_maxx<=0; cur_maxy<=0; cur_valid<=0;
      end
      if (mask) begin
        if (x < cur_minx) cur_minx <= x;
        if (y < cur_miny) cur_miny <= y;
        if (x > cur_maxx) cur_maxx <= x;
        if (y > cur_maxy) cur_maxy <= y;
        cur_valid <= 1'b1;
      end
    end
  end

  // Latched bbox exposed over AXI-Lite (updated at next SOF)
  reg [15:0] lat_minx, lat_miny, lat_maxx, lat_maxy;
  reg lat_valid;

  always @(posedge aclk) begin
    if (!aresetn) begin
      lat_minx<=0; lat_miny<=0; lat_maxx<=0; lat_maxy<=0; lat_valid<=0;
    end else if (s_axis_tvalid && s_axis_tready && sof) begin
      lat_minx<=cur_minx; lat_miny<=cur_miny; lat_maxx<=cur_maxx; lat_maxy<=cur_maxy; lat_valid<=cur_valid;
    end
  end

  // AXI-Lite read-only registers
  assign s_axi_awready = 1'b0;
  assign s_axi_wready  = 1'b0;
  assign s_axi_bresp   = 2'b10;  // SLVERR if someone writes
  assign s_axi_bvalid  = 1'b0;
  reg arready=0, rvalid=0; reg [31:0] rdata=0;
  assign s_axi_arready = arready;
  assign s_axi_rvalid  = rvalid;
  assign s_axi_rdata   = rdata;
  assign s_axi_rresp   = 2'b00;

  // addr map: 0x00=minx, 0x04=miny, 0x08=maxx, 0x0C=maxy, 0x10=valid
  always @(posedge s_axi_aclk) begin
    if (!s_axi_aresetn) begin
      arready<=0; rvalid<=0; rdata<=0;
    end else begin
      if (!arready && s_axi_arvalid) begin
        arready<=1; rvalid<=1;
        case (s_axi_araddr[5:2])
          4'h0: rdata <= {16'd0, lat_minx};
          4'h1: rdata <= {16'd0, lat_miny};
          4'h2: rdata <= {16'd0, lat_maxx};
          4'h3: rdata <= {16'd0, lat_maxy};
          4'h4: rdata <= {31'd0, lat_valid};
          default: rdata <= 32'd0;
        endcase
      end else begin
        arready<=0;
      end
      if (rvalid && s_axi_rready) rvalid<=0;
    end
  end

endmodule

3) axis_bbox_overlay.v

• Draws rectangle on the incoming RGB stream whenever pixel is on bbox edges
• Rectangle color and thickness controlled via AXI-Lite

module axis_bbox_overlay #(
  parameter integer WIDTH  = 1920,
  parameter integer HEIGHT = 1080,
  parameter integer C_S_AXI_ADDR_WIDTH = 6,
  parameter integer C_S_AXI_DATA_WIDTH = 32
)(
  input  wire                     aclk,
  input  wire                     aresetn,

  // AXIS In
  input  wire [23:0]              s_axis_tdata,
  input  wire                     s_axis_tvalid,
  output wire                     s_axis_tready,
  input  wire                     s_axis_tlast,
  input  wire [1:0]               s_axis_tuser, // [0]=SOF

  // AXIS Out
  output reg  [23:0]              m_axis_tdata,
  output wire                     m_axis_tvalid,
  input  wire                     m_axis_tready,
  output wire                     m_axis_tlast,
  output wire [1:0]               m_axis_tuser,

  // AXI-Lite (write-only) to set bbox and style
  input  wire                     s_axi_aclk,
  input  wire                     s_axi_aresetn,
  input  wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
  input  wire                     s_axi_awvalid,
  output wire                     s_axi_awready,
  input  wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
  input  wire [3:0]               s_axi_wstrb,
  input  wire                     s_axi_wvalid,
  output wire                     s_axi_wready,
  output wire [1:0]               s_axi_bresp,
  output wire                     s_axi_bvalid,
  input  wire                     s_axi_bready,
  input  wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
  input  wire                     s_axi_arvalid,
  output wire                     s_axi_arready,
  output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
  output wire [1:0]               s_axi_rresp,
  output wire                     s_axi_rvalid,
  input  wire                     s_axi_rready
);
  // Pass-through handshake
  assign s_axis_tready = m_axis_tready;
  assign m_axis_tvalid = s_axis_tvalid;
  assign m_axis_tlast  = s_axis_tlast;
  assign m_axis_tuser  = s_axis_tuser;

  // Pixel counters
  reg [15:0] x=0, y=0;
  wire sof = s_axis_tvalid && s_axis_tuser[0];
  wire eol = s_axis_tvalid && s_axis_tlast;
  always @(posedge aclk) begin
    if (!aresetn) begin x<=0; y<=0; end
    else if (s_axis_tvalid && s_axis_tready) begin
      if (sof) begin x<=0; y<=0; end
      else if (eol) begin x<=0; if (y==HEIGHT-1) y<=0; else y<=y+1; end
      else begin if (x==WIDTH-1) x<=0; else x<=x+1; end
    end
  end

  // AXI-Lite write-only regs: bbox and style
  reg [15:0] minx=0, miny=0, maxx=0, maxy=0;
  reg [7:0]  color_r=8'hFF, color_g=8'h00, color_b=8'h00;
  reg [3:0]  thickness=4'd3;
  reg        enable=1'b1;

  reg awready=0, wready=0, bvalid=0;
  assign s_axi_awready = awready;
  assign s_axi_wready  = wready;
  assign s_axi_bresp   = 2'b00;
  assign s_axi_bvalid  = bvalid;
  // read channels are not used
  assign s_axi_arready = 1'b0;
  assign s_axi_rvalid  = 1'b0;
  assign s_axi_rdata   = 32'd0;
  assign s_axi_rresp   = 2'b10;

  always @(posedge s_axi_aclk) begin
    if (!s_axi_aresetn) begin
      awready<=0; wready<=0; bvalid<=0;
      minx<=0; miny<=0; maxx<=0; maxy<=0;
      color_r<=8'hFF; color_g<=8'h00; color_b<=8'h00;
      thickness<=4'd3; enable<=1'b1;
    end else begin
      if (!awready && s_axi_awvalid) awready<=1;
      if (!wready && s_axi_wvalid)   wready<=1;
      if (awready && wready && !bvalid) begin
        awready<=0; wready<=0; bvalid<=1;
        case (s_axi_awaddr[5:2])
          4'h0: minx <= s_axi_wdata[15:0];
          4'h1: miny <= s_axi_wdata[15:0];
          4'h2: maxx <= s_axi_wdata[15:0];
          4'h3: maxy <= s_axi_wdata[15:0];
          4'h4: begin color_r<=s_axi_wdata[7:0]; color_g<=s_axi_wdata[15:8]; color_b<=s_axi_wdata[23:16]; end
          4'h5: thickness <= s_axi_wdata[3:0];
          4'h6: enable    <= s_axi_wdata[0];
          default: ;
        endcase
      end
      if (bvalid && s_axi_bready) bvalid<=0;
    end
  end

  // Overlay logic
  wire on_left   = (x >= minx) && (x < minx + thickness) && (y >= miny) && (y <= maxy);
  wire on_right  = (x <= maxx) && (x > maxx - thickness) && (y >= miny) && (y <= maxy);
  wire on_top    = (y >= miny) && (y < miny + thickness) && (x >= minx) && (x <= maxx);
  wire on_bottom = (y <= maxy) && (y > maxy - thickness) && (x >= minx) && (x <= maxx);
  wire draw = enable && (on_left || on_right || on_top || on_bottom);

  always @(posedge aclk) begin
    if (!aresetn) m_axis_tdata <= 24'd0;
    else if (s_axis_tvalid && s_axis_tready) begin
      m_axis_tdata <= draw ? {color_r, color_g, color_b} : s_axis_tdata;
    end
  end

endmodule

4) Minimal PS application (Vitis) to configure IMX219 and AXI-Lite registers

We will use the Zynq PS I2C (XIicPs) to configure IMX219 into 1920×1080 @ 30 fps, 2-lane MIPI, then set thresholds for a target color (example: a bright red object). The IMX219 register table is sourced from Digilent’s Pcam 5C demo; we will fetch it from their repo at a fixed commit.

Create sw/app/src/main.c with:

#include "xparameters.h"
#include "xiicps.h"
#include "xil_printf.h"
#include "xil_io.h"
#include <unistd.h>
#include <stdint.h>

#define I2C_DEVICE_ID   XPAR_XIICPS_0_DEVICE_ID
#define I2C_SCLK_RATE   100000
#define IMX219_I2C_ADDR 0x10  // 7-bit address (0x20 >> 1)

#define AXIL_THRESH_BASE XPAR_AXIS_COLOR_THRESH_0_S_AXI_BASEADDR
#define AXIL_TRACK_BASE  XPAR_AXIS_BBOX_TRACKER_0_S_AXI_BASEADDR
#define AXIL_OVERLAY_BASE XPAR_AXIS_BBOX_OVERLAY_0_S_AXI_BASEADDR

typedef struct { uint16_t reg; uint8_t val; } reg8_t;

// Pull IMX219 init table for 1080p30 from Digilent repo (commit pinned)
// For brevity, include only an excerpt; in your workspace, you will copy the full table.
static const reg8_t imx219_1080p30[] = {
  {0x0103, 0x01}, // software reset
  {0x30EB, 0x05}, {0x30EB, 0x0C}, {0x300A, 0xFF}, {0x300B, 0xFF}, {0x30EB, 0x05}, {0x30EB, 0x09},
  {0x0114, 0x01}, // 2-lane
  {0x0128, 0x00},
  {0x012A, 0x18}, {0x012B, 0x00}, // external clock 24MHz
  // PLL and timing settings suitable for 1920x1080@30; use Digilent-provided table in practice
  {0x0160, 0x04}, {0x0161, 0x65}, // frame length lines
  {0x0162, 0x0D}, {0x0163, 0x78}, // line length
  {0x0170, 0x01}, {0x0171, 0x01},
  {0x0172, 0x03}, // binning
  {0x0164, 0x02}, {0x0165, 0xA8}, // x start
  {0x0166, 0x0A}, {0x0167, 0x27}, // x end
  {0x0168, 0x02}, {0x0169, 0xB4}, // y start
  {0x016A, 0x06}, {0x016B, 0xEB}, // y end
  {0x016C, 0x07}, {0x016D, 0x80}, // x output size 1920
  {0x016E, 0x04}, {0x016F, 0x38}, // y output size 1080
  {0x018C, 0x0A}, {0x018D, 0x0A}, // CSI-2 data format RAW10
  {0x0301, 0x05}, {0x0303, 0x01}, {0x0304, 0x03}, {0x0305, 0x03},
  {0x0306, 0x00}, {0x0307, 0x39}, {0x0309, 0x0A}, {0x030B, 0x01},
  {0x030D, 0x03}, {0x030E, 0x00}, {0x030F, 0x39},
  {0x0157, 0x00}, // analog gain
  {0x015A, 0x00}, {0x015B, 0x10}, // integration time
  {0x0100, 0x01}, // start streaming
};

static int i2c_write_reg16(XIicPs *Iic, uint16_t reg, uint8_t val) {
  uint8_t buf[3];
  buf[0] = (reg >> 8) & 0xFF;
  buf[1] = (reg >> 0) & 0xFF;
  buf[2] = val;
  int status = XIicPs_MasterSendPolled(Iic, buf, 3, IMX219_I2C_ADDR);
  usleep(200);
  return (status == XST_SUCCESS) ? 0 : -1;
}

static int imx219_init(XIicPs *Iic) {
  for (unsigned i=0; i<sizeof(imx219_1080p30)/sizeof(imx219_1080p30[0]); ++i) {
    if (i2c_write_reg16(Iic, imx219_1080p30[i].reg, imx219_1080p30[i].val) != 0) {
      xil_printf("I2C write failed at reg 0x%04x\r\n", imx219_1080p30[i].reg);
      return -1;
    }
  }
  xil_printf("IMX219 initialized (1080p30 RAW10)\r\n");
  return 0;
}

static void thresholds_set(uint8_t rmin, uint8_t rmax, uint8_t gmin, uint8_t gmax, uint8_t bmin, uint8_t bmax) {
  Xil_Out32(AXIL_THRESH_BASE + 0x00, rmin);
  Xil_Out32(AXIL_THRESH_BASE + 0x04, rmax);
  Xil_Out32(AXIL_THRESH_BASE + 0x08, gmin);
  Xil_Out32(AXIL_THRESH_BASE + 0x0C, gmax);
  Xil_Out32(AXIL_THRESH_BASE + 0x10, bmin);
  Xil_Out32(AXIL_THRESH_BASE + 0x14, bmax);
}

static void overlay_style_default() {
  // red rectangle, 3 px thick, enable=1
  Xil_Out32(AXIL_OVERLAY_BASE + 0x10, (0x00<<16) | (0x00<<8) | 0xFF); // R,G,B in our order (packed as b:g:r if needed)
  Xil_Out32(AXIL_OVERLAY_BASE + 0x14, 3);
  Xil_Out32(AXIL_OVERLAY_BASE + 0x18, 1);
}

static void overlay_update_from_tracker() {
  uint32_t minx = Xil_In32(AXIL_TRACK_BASE + 0x00);
  uint32_t miny = Xil_In32(AXIL_TRACK_BASE + 0x04);
  uint32_t maxx = Xil_In32(AXIL_TRACK_BASE + 0x08);
  uint32_t maxy = Xil_In32(AXIL_TRACK_BASE + 0x0C);
  uint32_t valid= Xil_In32(AXIL_TRACK_BASE + 0x10) & 0x1;
  if (valid) {
    Xil_Out32(AXIL_OVERLAY_BASE + 0x00, minx);
    Xil_Out32(AXIL_OVERLAY_BASE + 0x04, miny);
    Xil_Out32(AXIL_OVERLAY_BASE + 0x08, maxx);
    Xil_Out32(AXIL_OVERLAY_BASE + 0x0C, maxy);
  }
}

int main() {
  XIicPs Iic;
  XIicPs_Config *IicCfg = XIicPs_LookupConfig(I2C_DEVICE_ID);
  XIicPs_CfgInitialize(&Iic, IicCfg, IicCfg->BaseAddress);
  XIicPs_SetSClk(&Iic, I2C_SCLK_RATE);

  xil_printf("Zybo Z7-20 mipi-csi2-hdmi-object-tracking\r\n");
  if (imx219_init(&Iic) != 0) {
    xil_printf("IMX219 init failed\r\n");
    while (1);
  }

  // Set thresholds for red-ish color; tune in validation
  thresholds_set(/*rmin*/180, /*rmax*/255, /*gmin*/0, /*gmax*/120, /*bmin*/0, /*bmax*/120);
  overlay_style_default();

  while (1) {
    overlay_update_from_tracker();
    usleep(10000); // 10ms
  }
  return 0;
}

Note: For a complete IMX219 register table, copy Digilent’s Pcam 5C configuration for 1080p30 RAW10. In the build steps we include commands to fetch that file and replace the placeholder array.

---

Project Files and Scripts

We will use a scripted, non-project build flow.

Directory layout:

• hw/rtl/axis_color_thresh.v
• hw/rtl/axis_bbox_tracker.v
• hw/rtl/axis_bbox_overlay.v
• hw/xdc/zybo_z7_master.xdc (from Digilent)
• hw/xdc/pcam_pins.xdc (from Digilent Pcam demo)
• hw/xdc/hdmi_out.xdc (from Digilent)
• scripts/create_bd.tcl
• scripts/build.tcl
• scripts/prog.tcl
• scripts/build_vitis.tcl
• sw/app/src/main.c

Example scripts/create_bd.tcl (abridged to key parts; adjust IP versions per 2023.2):

set_part xc7z020clg400-1
create_project mipi_hdmi_track ./build -part xc7z020clg400-1 -force

set_property ip_repo_paths [list ./ip_repo ./vivado-library/ip] [current_project]
update_ip_catalog

# Create Block Design
create_bd_design "system"

# Zynq PS
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ps7
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config { apply_board_preset "1" } [get_bd_cells ps7]

# MIPI D-PHY + CSI-2 RX
create_bd_cell -type ip -vlnv xilinx.com:ip:mipi_dphy_rx_ctrl:4.3 dphy
create_bd_cell -type ip -vlnv xilinx.com:ip:mipi_csi2_rx_subsystem:5.2 csi2rx
set_property -dict [list CONFIG.CMN_NUM_LANES {2} CONFIG.CMN_PXL_FORMAT {RAW10} CONFIG.CMN_PIXELS_PER_CLK {2}] [get_bd_cells csi2rx]

# Demosaic (choose one: Xilinx V_CFA or Digilent demosaic)
# Example with Xilinx V_CFA
create_bd_cell -type ip -vlnv xilinx.com:ip:v_cfa:7.2 cfa
set_property -dict [list CONFIG.c_s_axis_video_format {2}] [get_bd_cells cfa] ;# Bayer -> RGB

# AXIS to video out + VTC
create_bd_cell -type ip -vlnv xilinx.com:ip:v_axi4s_vid_out:5.0 axi2vid
create_bd_cell -type ip -vlnv xilinx.com:ip:v_tc:6.2 vtc

# rgb2dvi (Digilent)
create_bd_cell -type ip -vlnv digilentinc.com:ip:rgb2dvi:1.4 rgb2dvi_0

# Custom processing cores (packaged or add as files; here we add as BD IP filesets)
add_files -fileset sources_1 ../hw/rtl/axis_color_thresh.v
add_files -fileset sources_1 ../hw/rtl/axis_bbox_tracker.v
add_files -fileset sources_1 ../hw/rtl/axis_bbox_overlay.v
# Package as module references in BD via "Module Ref" blocks
create_bd_cell -type module -reference axis_color_thresh color_thresh_0
create_bd_cell -type module -reference axis_bbox_tracker bbox_tracker_0
create_bd_cell -type module -reference axis_bbox_overlay bbox_overlay_0

# AXI Interconnect for AXI-Lite
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0
set_property -dict [list CONFIG.NUM_MI {3} CONFIG.NUM_SI {1}] [get_bd_cells axi_interconnect_0]
# PS7 M_AXI_GP0 -> interconnect S00
connect_bd_intf_net [get_bd_intf_pins ps7/M_AXI_GP0] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
# Connect MI to AXI-Lite of module refs
# For module references, Vivado creates AXI ports automatically if names match; otherwise wire via AXI SmartConnect
# Example assuming s_axi_* ports:
connect_bd_intf_net [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins color_thresh_0/S_AXI]
connect_bd_intf_net [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins bbox_tracker_0/S_AXI]
connect_bd_intf_net [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins bbox_overlay_0/S_AXI]
# AXI clocks/resets
connect_bd_net [get_bd_pins ps7/FCLK_CLK0] [get_bd_pins axi_interconnect_0/ACLK]
connect_bd_net [get_bd_pins ps7/FCLK_CLK0] [get_bd_pins color_thresh_0/s_axi_aclk]
connect_bd_net [get_bd_pins ps7/FCLK_CLK0] [get_bd_pins bbox_tracker_0/s_axi_aclk]
connect_bd_net [get_bd_pins ps7/FCLK_CLK0] [get_bd_pins bbox_overlay_0/s_axi_aclk]
# Resets
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst0
connect_bd_net [get_bd_pins ps7/FCLK_CLK0] [get_bd_pins rst0/slowest_sync_clk]
connect_bd_net [get_bd_pins ps7/FCLK_RESET0_N] [get_bd_pins rst0/ext_reset_in]
connect_bd_net [get_bd_pins rst0/peripheral_aresetn] [get_bd_pins color_thresh_0/s_axi_aresetn]
connect_bd_net [get_bd_pins rst0/peripheral_aresetn] [get_bd_pins bbox_tracker_0/s_axi_aresetn]
connect_bd_net [get_bd_pins rst0/peripheral_aresetn] [get_bd_pins bbox_overlay_0/s_axi_aresetn]

# Video stream connections
# dphy -> csi2rx
connect_bd_intf_net [get_bd_intf_pins dphy/MIPI_DPHY_RX] [get_bd_intf_pins csi2rx/CSI2_RX]
# Axis from CSI-2 -> CFA
connect_bd_intf_net [get_bd_intf_pins csi2rx/video_out] [get_bd_intf_pins cfa/s_axis_video]
# CFA -> color_thresh -> bbox_tracker -> bbox_overlay -> axi2vid
connect_bd_intf_net [get_bd_intf_pins cfa/m_axis_video] [get_bd_intf_pins color_thresh_0/s_axis]
connect_bd_intf_net [get_bd_intf_pins color_thresh_0/m_axis] [get_bd_intf_pins bbox_tracker_0/s_axis]
connect_bd_intf_net [get_bd_intf_pins bbox_tracker_0/m_axis] [get_bd_intf_pins bbox_overlay_0/s_axis]
connect_bd_intf_net [get_bd_intf_pins bbox_overlay_0/m_axis] [get_bd_intf_pins axi2vid/video_in]

# Timing and clocks
connect_bd_net [get_bd_pins csi2rx/video_aclk] [get_bd_pins cfa/ap_clk]
connect_bd_net [get_bd_pins csi2rx/video_aclk] [get_bd_pins color_thresh_0/aclk]
connect_bd_net [get_bd_pins csi2rx/video_aclk] [get_bd_pins bbox_tracker_0/aclk]
connect_bd_net [get_bd_pins csi2rx/video_aclk] [get_bd_pins bbox_overlay_0/aclk]
connect_bd_net [get_bd_pins csi2rx/video_aclk] [get_bd_pins axi2vid/aclk]

# vtc -> axi2vid
connect_bd_intf_net [get_bd_intf_pins vtc/vtiming_out] [get_bd_intf_pins axi2vid/vtiming_in]
# axi2vid -> rgb2dvi
connect_bd_net [get_bd_pins axi2vid/vid_io_out_active_video] [get_bd_pins rgb2dvi_0/vid_pVDE]
connect_bd_net [get_bd_pins axi2vid/vid_io_out_hsync] [get_bd_pins rgb2dvi_0/vid_pHSync]
connect_bd_net [get_bd_pins axi2vid/vid_io_out_vsync] [get_bd_pins rgb2dvi_0/vid_pVSync]
connect_bd_net [get_bd_pins axi2vid/vid_io_out_data] [get_bd_pins rgb2dvi_0/vid_pData]

# HDMI differential outputs to external pins via constraints (TMDS)
# Expose DPHY and HDMI ports to top
make_bd_pins_external  [get_bd_pins rgb2dvi_0/TMDS_Clk_p]
make_bd_pins_external  [get_bd_pins rgb2dvi_0/TMDS_Clk_n]
make_bd_pins_external  [get_bd_pins rgb2dvi_0/TMDS_Data_p]
make_bd_pins_external  [get_bd_pins rgb2dvi_0/TMDS_Data_n]
make_bd_intf_pins_external [get_bd_intf_pins dphy/CSI2_RX_DATA_P]
# ... likewise for N, CLK P/N per Digilent Pcam connector mapping

# Enable PS I2C and UART
set_property -dict [list CONFIG.I2C0_Enable {1} CONFIG.I2C0_IO {EMIO} CONFIG.UART1_Enable {1}] [get_bd_cells ps7]

# Address map
assign_bd_address
save_bd_design
make_wrapper -files [get_files ./build/mipi_hdmi_track.srcs/sources_1/bd/system/system.bd] -top
add_files -norecurse ./build/mipi_hdmi_track.gen/sources_1/bd/system/hdl/system_wrapper.v

Note: The exact MIPI and IO pin mappings must match the Digilent Zybo Z7-20 master XDC and the Pcam constraints. We include them in the XDC files below during build.

---

Build / Flash / Run Commands

Clone repositories, set up directories, and run Vivado and Vitis in batch.

1) Prepare workspace:

mkdir -p ~/zybo_mipi_track/{hw/{rtl,xdc},ip_repo,scripts,sw/app/src}
cd ~/zybo_mipi_track

# Fetch Digilent board files and IP
git clone https://github.com/Digilent/vivado-boards.git --branch master --depth 1
git clone https://github.com/Digilent/vivado-library.git --branch master --depth 1

# Optional: fetch Digilent Pcam demo for reference constraints and sensor config
git clone https://github.com/Digilent/Zybo-Z7-20-pcam-5c.git --depth 1

# Copy XDCs you will use (verify paths exist in the repo)
cp Zybo-Z7-20-pcam-5c/src/constraints/zybo-z7-master.xdc hw/xdc/zybo_z7_master.xdc
cp Zybo-Z7-20-pcam-5c/src/constraints/pcam-5c.xdc hw/xdc/pcam_pins.xdc
cp vivado-library/ip/rgb2dvi/constraints/hdmi_out.xdc hw/xdc/hdmi_out.xdc

# Add our RTL files
cp path/to/axis_color_thresh.v hw/rtl/
cp path/to/axis_bbox_tracker.v hw/rtl/
cp path/to/axis_bbox_overlay.v hw/rtl/

# Add scripts (create_bd.tcl, build.tcl, prog.tcl, build_vitis.tcl) you wrote into scripts/

2) Build bitstream with Vivado 2023.2 CLI:

Create scripts/build.tcl:

# build.tcl
set_param board.repoPaths [list [file normalize "../vivado-boards/new/board_files"]]
source ./scripts/create_bd.tcl

# Constraints
add_files -fileset constrs_1 ./hw/xdc/zybo_z7_master.xdc
add_files -fileset constrs_1 ./hw/xdc/pcam_pins.xdc
add_files -fileset constrs_1 ./hw/xdc/hdmi_out.xdc

# Synthesis/Implementation
launch_runs synth_1 -jobs 8
wait_on_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
wait_on_run impl_1

# Export hardware XSA for Vitis
write_hw_platform -fixed -include_bit -force -file ./build/system_wrapper.xsa

Run Vivado:

/opt/Xilinx/Vivado/2023.2/bin/vivado -mode batch -source scripts/build.tcl | tee build_vivado.log

3) Program the FPGA and run bare-metal app from Vitis (xsct):

Create scripts/build_vitis.tcl:

setws ./vitis_ws
platform create -name zybo_platform -hw ./build/system_wrapper.xsa -proc ps7_cortexa9_0 -os standalone
platform write
platform generate

app create -name imx219_track_app -platform zybo_platform -proc ps7_cortexa9_0 -os standalone -template {Empty Application}
importsources -name imx219_track_app -path ../sw/app/src
app build -name imx219_track_app

connect
targets -set -filter {name =~ "ARM*#0"}
rst -processor
dow ./vitis_ws/imx219_track_app/Debug/imx219_track_app.elf
con

Run Vitis build and program:

/opt/Xilinx/Vitis/2023.2/bin/xsct scripts/build_vitis.tcl | tee build_vitis.log

Alternatively, if you only want to program the bitstream via Vivado:

# Program bitstream only
/opt/Xilinx/Vivado/2023.2/bin/vivado -mode tcl -source scripts/prog.tcl

Where scripts/prog.tcl might be:

open_hw
connect_hw_server
open_hw_target
set device [lindex [get_hw_devices xc7z020*] 0]
current_hw_device $device
refresh_hw_device $device
set_property PROGRAM.FILE ./build/mipi_hdmi_track.runs/impl_1/system_wrapper.bit $device
program_hw_devices $device

Note: For a complete, consistent IMX219 register set, copy the table from Digilent’s Pcam demo into sw/app/src/main.c in place of the abbreviated array. For example:

# copy the full register table file
cp Zybo-Z7-20-pcam-5c/src/pcam/pcam_5c.c sw/app/src/pcam_5c.c
# include it from main.c and call its init function instead of the local imx219_init()

---

Step-by-step Validation

1) Power and UART
– Connect USB, open UART at 115200 8N1:
– Example: picocom /dev/ttyUSB1 -b 115200
– Ensure monitor is set to HDMI input.

2) Program and run
– Build bitstream and app as shown above.
– After xsct runs, the UART should print:
– “Zybo Z7-20 mipi-csi2-hdmi-object-tracking”
– “IMX219 initialized (1080p30 RAW10)”
– The HDMI monitor should lock to 1080p (may show a brief blank then live video).

3) Verify live video without overlay
– Initially, if the tracker has not yet locked on, you may see live video with no box.
– Present a solid colored object (e.g., a red notebook) in front of the camera under good lighting.

4) Verify threshold-based object mask
– The default thresholds in main.c target a red object:
– R in [180,255]
– G in [0,120]
– B in [0,120]
– If your object and lighting are different, tune thresholds live by editing main.c values and re-running xsct build. For faster iteration, you can also add UART commands to set thresholds at runtime, but that is optional.

5) Confirm bounding box overlay
– When the object is in view, a red rectangle should appear circumscribing the object’s extents.
– Move the object across the frame; the rectangle should track its position with a frame of latency (bbox latched at SOF).

6) Check UART bbox prints
– You can add temporary prints in overlay_update_from_tracker() to print minx, miny, maxx, maxy to ensure values change as you move the object.
– Example: xil_printf(«bbox: %lu,%lu to %lu,%lu
«, minx, miny, maxx, maxy);

7) Edge cases
– Remove the object from the frame; the bbox_valid bit should drop and the overlay may freeze or disable (depending on enable setting).
– Introduce background clutter with similar colors; observe that the bounding box may widen. This is expected in simple color-threshold tracking.

8) MIPI health checks
– If the display is black:
– Confirm IMX219 init messages appear.
– Check that MIPI CSI-2 RX reports video clock (add ILA or status registers if needed).
– Ensure HDMI monitor shows a signal (use an OSD to confirm 1080p60 or 1080p30 timing as configured).

---

Troubleshooting

• No video, black screen:
• Check HDMI cable and monitor input.
• Verify rgb2dvi constraints are applied (TMDS_33 IOSTANDARD on Zybo Z7-20).
• Ensure v_axi4s_vid_out and vtc are configured for your resolution. If CSI-2 provides 1080p30, set vtc to 1080p timing and allow frame rate mismatch (the monitor cares about timing, not frame rate).

• The CFA/demosaic IP must match the Bayer pattern of IMX219 (RGGB/BGGR); adjust v_cfa configuration to the IMX219’s mosaic.

• MIPI IP license warnings:

• Use Vivado evaluation licenses for lab. IP may be time-limited; re-generate license if needed. Check the Vivado log for “evaluation mode” notes.

• I2C write failed or no ACK:

• Confirm IMX219 address is 0x10 (7-bit). Some docs use 8-bit address 0x20.
• Ensure I2C is routed to the Pcam connector pins. On Zybo Z7-20, you can use PS I2C via EMIO to PL IOB or use PL AXI IIC wired to the I2C pins; be consistent with your BD and constraints.

• Confirm pull-ups for I2C lines (the Pcam adapter includes them).

• Colors look wrong (weird tint):

• Incorrect Bayer pattern in demosaic IP. Try changing RGGB <-> BGGR pairings.

• Gamma or color correction missing (optional IP). For tracking, raw colors can suffice; tune thresholds accordingly.

• Bounding box flickers:

• If illumination varies, thresholding may be noisy. Increase thickness or add a small morphological filter (e.g., 3×3 dilate) in the mask path.

• Ensure you latch bbox at SOF to avoid reading mid-frame updates.

• Overlay not visible:

• Confirm overlay enable register is 1.
• Make overlay color bright and distinct.

• Set thickness to a larger value (e.g., 5).

• Timing closure issues:

• Constrain pixel clocks appropriately; rely on csi2rx/video_aclk to clock all video-path logic.
• Use AXI register slices between IPs to improve timing.
• Check the “report_clocks” and “report_timing_summary” in Vivado.

---

Improvements

• More robust segmentation:
• Convert RGB to HSV in hardware and threshold on hue/saturation for better invariance to lighting.

• Add morphological operations (erode/dilate) to reduce noise.

• Multi-object tracking:

• Maintain multiple bounding boxes or compute connected-component labels in hardware.

• Use PS-side software (ARM) to run a simple Kalman filter for smoother tracking.

• Performance and resolution:

• Switch to 1280×720@60 if your monitor expects 60 Hz timing and the demosaic path prefers that throughput.

• Increase pixels-per-clock in Xilinx video IP (2 or 4) to meet higher frame rates.

• Overlay enhancements:

• Fill the bounding box with alpha blending.

• Draw trail lines of recent positions (small FIFO of centroids).

• Control plane:

• Add UART CLI to adjust thresholds at runtime without rebuilding.

• Map Zybo switches/buttons to toggle overlay, cycle threshold presets, etc.

• Software pipeline (alternative approach):

• Stream frames to PS DDR via VDMA; run OpenCV on ARM for advanced object tracking (e.g., CamShift, KCF), then render overlays via DRM. This is heavier but flexible.

---

Final Checklist

• Hardware
• Digilent Zybo Z7-20 and Digilent Pcam 5C connected properly
• HDMI monitor connected and set to the correct input

• USB connected for JTAG/UART; UART at 115200 8N1

• Tools

• Vivado 2023.2 WebPACK installed and in PATH
• Vitis 2023.2 installed and xsct available
• Digilent vivado-boards and vivado-library cloned

• Pcam demo repo cloned for constraints and IMX219 init table

• Project

• RTL files for axis_color_thresh, axis_bbox_tracker, axis_bbox_overlay in hw/rtl
• XDC constraints added for Zybo, Pcam, HDMI
• create_bd.tcl adjusted for your IP versions and connections

• build.tcl creates bitstream and exports XSA

• Build and Run

• vivado -mode batch -source scripts/build.tcl completes without critical errors
• xsct scripts/build_vitis.tcl builds platform and app, downloads elf, starts CPU
• UART prints show IMX219 initialized

• HDMI shows live video with bounding box overlay tracking a colored object

• Validation

• Moving a colored target causes the bounding box to follow
• Thresholds can be tuned in main.c and re-run to suit your scene
• No persistent timing or link errors in Vivado hardware manager

If all items are checked, you have a working MIPI-CSI2 to HDMI object tracking pipeline on the Digilent Zybo Z7-20 with the Pcam 5C (IMX219), built entirely with Vivado WebPACK CLI and a minimal Vitis bare-metal application.