Practical case: Light switching from two points

Light switching from two points prototype (Maker Style)

Level: Medium. Implement an XOR logic function using universal NAND gates to control a light source from two independent locations.

Objective and use case

In this case, you will build a digital logic circuit that replicates a residential 2-way switching system (hallway light) using a single 74HC00 Quad NAND Gate IC. By combining four NAND gates, you will synthesize the Exclusive-OR (XOR) function, proving that NAND gates are «universal» building blocks.

Why it is useful:
* Residential wiring simulation: Demonstrates how two switches can independently toggle a single load (hallway/staircase logic).
* Digital Logic Synthesis: Teaches how to build complex logic (XOR) from basic universal gates (NAND).
* Arithmetic Circuits: This specific XOR topology is the fundamental component of a digital «Half-Adder» used in CPU ALUs.
* Error Detection: XOR logic is used to calculate parity bits for data transmission.

Expected outcome:
* State 00: When both switches are OFF, the LED is OFF.
* State 01/10: When only one switch is ON, the LED is ON (High logic level > 3.5 V).
* State 11: When both switches are ON, the LED is OFF.
* Universality: Successful demonstration that 4 NAND gates = 1 XOR gate.

Target audience: Electronics students and hobbyists familiar with basic logic gates.

Materials

  • V1: 5 V DC power supply, function: Main circuit power.
  • U1: 74HC00, function: Quad 2-input NAND gate IC.
  • S1: SPST Switch, function: Input A (Switch 1).
  • S2: SPST Switch, function: Input B (Switch 2).
  • R1: 10 kΩ resistor, function: Pull-down for Input A.
  • R2: 10 kΩ resistor, function: Pull-down for Input B.
  • R3: 330 Ω resistor, function: LED current limiting.
  • D1: Red LED, function: Output indicator (Light).

Pin-out of the IC used

Selected Chip: 74HC00 (Quad 2-Input NAND Gate)

Pin Name Logic Function Connection in this case
1 1 A Input Gate 1 Connect to Node INPUT_A
2 1B Input Gate 1 Connect to Node INPUT_B
3 1Y Output Gate 1 Internal Node NAND_1_OUT
4 2 A Input Gate 2 Connect to Node INPUT_A
5 2B Input Gate 2 Connect to Node NAND_1_OUT
6 2Y Output Gate 2 Internal Node NAND_2_OUT
7 GND Ground Connect to Node 0 (GND)
8 3Y Output Gate 3 Internal Node NAND_3_OUT
9 3 A Input Gate 3 Connect to Node NAND_1_OUT
10 3B Input Gate 3 Connect to Node INPUT_B
11 4Y Output Gate 4 Connect to Node FINAL_OUT
12 4 A Input Gate 4 Connect to Node NAND_2_OUT
13 4B Input Gate 4 Connect to Node NAND_3_OUT
14 VCC Power Supply Connect to Node VCC (+5 V)

Wiring guide

  • V1: Connect positive terminal to node VCC and negative terminal to node 0.
  • U1 (Power): Connect Pin 14 to VCC and Pin 7 to 0.
  • S1: Connect one side to VCC and the other to node INPUT_A.
  • R1: Connect between node INPUT_A and node 0.
  • S2: Connect one side to VCC and the other to node INPUT_B.
  • R2: Connect between node INPUT_B and node 0.
  • U1 (Gate 1): Connect Pin 1 to INPUT_A, Pin 2 to INPUT_B. Pin 3 is node NAND_1_OUT.
  • U1 (Gate 2): Connect Pin 4 to INPUT_A, Pin 5 to NAND_1_OUT. Pin 6 is node NAND_2_OUT.
  • U1 (Gate 3): Connect Pin 10 to INPUT_B, Pin 9 to NAND_1_OUT. Pin 8 is node NAND_3_OUT.
  • U1 (Gate 4): Connect Pin 12 to NAND_2_OUT, Pin 13 to NAND_3_OUT. Pin 11 is node FINAL_OUT.
  • R3: Connect between node FINAL_OUT and the Anode of D1.
  • D1: Connect the Cathode to node 0.

Conceptual block diagram

Conceptual block diagram — 74HC00 NAND gate
Quick read: inputs → main block → output (actuator or measurement). This summarizes the ASCII schematic below.

Schematic

Title: Practical case: Light switching from two points (XOR Logic)

INPUT STAGE                  LOGIC PROCESSING (74HC00)                  OUTPUT STAGE
(User Controls)              (NAND-based XOR Circuit)                   (Indicator)

                                     (Pin 4)
VCC --> [ S1 ] --(Node A)----------> [ U1:Gate 2 ] --(NAND_2)--\
          |                          (Pin 5,6)                  \
       [ R1 ]                            ^                       \
          v                              |                        \
         GND                        (NAND_1_OUT)                   \
                                         |                          \
                                         |                           \
(Node A) & (Node B) -----------> [ U1:Gate 1 ]                        --> [ U1:Gate 4 ] --(FINAL)--> [ R3 ] --> [ D1: LED ] --> GND
                                 (Pin 1,2->3)                        /    (Pin 12,13->11)
                                         |                          /
                                         |                         /
                                    (NAND_1_OUT)                  /
          ^                              |                       /
       [ R2 ]                            v                      /
          |                          (Pin 9)                   /
VCC --> [ S2 ] --(Node B)----------> [ U1:Gate 3 ] --(NAND_3)-/
                                     (Pin 10,8)
Electrical Schematic

Truth table (Synthesized XOR)

Switch A (S1) Switch B (S2) LED State (D1) Logic Function
0 (OFF) 0 (OFF) OFF (0) No active input
0 (OFF) 1 (ON) ON (1) Inputs differ
1 (ON) 0 (OFF) ON (1) Inputs differ
1 (ON) 1 (ON) OFF (0) Inputs match

Measurements and tests

  1. Initial State Check: Ensure both S1 and S2 are open. Measure voltage at Pin 11 (FINAL_OUT). It should be < 0.5 V (Logic 0). D1 should be dark.
  2. First Switch Toggle: Close S1 only. Measure voltage at Pin 11. It should be close to 5 V (Logic 1). D1 should light up.
  3. Second Switch Toggle: Open S1 and close S2. Observe D1. It should light up again (Logic 1).
  4. Collision Check: Close both S1 and S2 simultaneously. Measure voltage at Pin 3 (NAND_1_OUT). Since both inputs are High, Pin 3 must be Low. Consequently, Pin 11 (FINAL_OUT) should go Low, turning D1 OFF.

SPICE netlist and simulation

Reference SPICE Netlist (ngspice)

* Practical case: Light switching from two points
* Title: Light switching from two points

* ==============================================================================
* COMPONENT MODELS
* ==============================================================================

* Simple LED Model
.model DLED D(IS=1e-22 RS=10 N=1.5 CJO=10p BV=5 IBV=10u)

* Voltage Controlled Switch Model for Buttons
* Vt=2.5V threshold, Ron=1 ohm, Roff=10Meg ohm
.model SW_PUSH SW(Vt=2.5 Ron=1 Roff=10Meg)

* ==============================================================================
* MAIN CIRCUIT
* ==============================================================================

* --- Power Supply ---
* V1: 5 V DC power supply
* ... (truncated in public view) ...

Copy this content into a .cir file and run with ngspice.

🔒 Part of this section is premium. With the 7-day pass or the monthly membership you can access the full content (materials, wiring, detailed build, validation, troubleshooting, variants and checklist) and download the complete print-ready PDF pack.

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Simulation Results (Transient Analysis)

Simulation Results (Transient Analysis)

Analysis: The simulation confirms the XOR logic behavior required for 2-way switching. When inputs differ (e.g., t=51us: A=0, B=1 -> Out=5V; t=101us: A=1, B=1 -> Out=0V; t=180us: A=1, B=0 -> Out=5V), the LED is ON (approx 1.88V drop). When inputs match (0,0 or 1,1), the output is near 0V.
Show raw data table (773 rows) 
Index   time            v(input_a)      v(input_b)      v(final_out)    v(led_node)
0	0.000000e+00	4.995005e-03	4.995005e-03	-3.70921e-68	-1.32951e-36
1	1.000000e-08	4.995005e-03	4.995005e-03	-3.70921e-68	-3.37339e-37
2	2.000000e-08	4.995005e-03	4.995005e-03	-3.70921e-68	1.661518e-37
3	4.000000e-08	4.995005e-03	4.995005e-03	-3.70921e-68	2.976605e-37
4	8.000000e-08	4.995005e-03	4.995005e-03	-3.70921e-68	8.146600e-38
5	1.600000e-07	4.995005e-03	4.995005e-03	-3.70921e-68	-2.74917e-38
6	3.200000e-07	4.995005e-03	4.995005e-03	-3.70921e-68	-1.00046e-38
7	3.562500e-07	4.995005e-03	4.995005e-03	-3.70921e-68	-9.54478e-40
8	4.196875e-07	4.995005e-03	4.995005e-03	-3.70921e-68	1.440911e-39
9	4.372461e-07	4.995005e-03	4.995005e-03	-3.70921e-68	5.873353e-40
10	4.679736e-07	4.995005e-03	4.995005e-03	-3.70921e-68	-1.64244e-40
11	5.019934e-07	4.999500e+00	4.999500e+00	-3.70921e-68	5.471353e-16
12	5.700330e-07	4.999500e+00	4.999500e+00	-3.70921e-68	1.883035e-16
13	7.061121e-07	4.999500e+00	4.999500e+00	-3.70921e-68	-1.89304e-16
14	9.782703e-07	4.999500e+00	4.999500e+00	-3.70921e-68	1.713539e-16
15	1.000000e-06	4.999500e+00	4.999500e+00	-3.70921e-68	-8.76370e-17
16	1.043459e-06	4.999500e+00	4.999500e+00	-3.70921e-68	2.969253e-18
17	1.130378e-06	4.999500e+00	4.999500e+00	-3.70921e-68	1.336375e-17
18	1.304216e-06	4.999500e+00	4.999500e+00	-3.70921e-68	1.285658e-18
19	1.651892e-06	4.999500e+00	4.999500e+00	-3.70921e-68	-4.38731e-19
20	2.347244e-06	4.999500e+00	4.999500e+00	-3.70921e-68	-3.76487e-20
21	3.347244e-06	4.999500e+00	4.999500e+00	-3.70921e-68	3.641502e-21
22	4.347244e-06	4.999500e+00	4.999500e+00	-3.70921e-68	3.034717e-22
23	5.347244e-06	4.999500e+00	4.999500e+00	-3.70921e-68	-2.04956e-23
... (749 more rows) ...

Common mistakes and how to avoid them

  1. Floating Inputs: Forgetting R1 or R2 causes the inputs to «float,» often reading as High due to electromagnetic noise. Solution: Always ensure inputs are pulled to Ground when the switch is open.
  2. Incorrect Gate Feedback: Wiring Pin 3 output to the wrong inputs on Gates 2 or 3 destroys the logic. Solution: Double-check that the output of the first NAND (Pin 3) connects to BOTH the second (Pin 5) and third (Pin 9) gates.
  3. Forgetting Power: Logic chips do not work passively. Solution: Verify 5 V on Pin 14 and continuity to Ground on Pin 7 before inserting signals.

Troubleshooting

  • Symptom: LED is always ON, regardless of switch position.
    • Cause: Wiring error at the final NAND gate (Gate 4) or output shorted to VCC.
    • Fix: Check connections at Pins 11, 12, and 13. Ensure Pin 11 is not touching the positive rail.
  • Symptom: LED behaves like an OR gate (stays ON when both switches are ON).
    • Cause: The first NAND gate (Gate 1) is not effectively inhibiting the signal.
    • Fix: Check continuity on Pins 1, 2, and 3. If Gate 1 output stays High when inputs are High, the XOR logic fails.
  • Symptom: Circuit works erratically when touching the wires.
    • Cause: Missing pull-down resistors (floating inputs).
    • Fix: Verify R1 and R2 are securely connected between the input pins and Ground.

Possible improvements and extensions

  1. 3-Way Switching: Add a third switch and another XOR stage (using a second 74HC00 or a 74HC86) to control the light from three locations.
  2. Comparison with Dedicated IC: Build the same circuit using a 74HC86 (Quad XOR) alongside this one to compare propagation delay and wiring complexity.

More Practical Cases on Prometeo.blog

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Quick Quiz

Question 1: What specific real-world application does this digital logic circuit simulate?




Question 2: Which logic function is synthesized using the NAND gates in this experiment?




Question 3: Which specific Integrated Circuit (IC) is used to build this circuit?




Question 4: Why are NAND gates referred to as "universal" building blocks?




Question 5: According to the expected outcome, what is the state of the LED when only one switch is ON?




Question 6: What happens to the LED when both switches are turned ON (State 11)?




Question 7: How many NAND gates are combined to synthesize the XOR function in this topology?




Question 8: In the context of CPU ALUs, what arithmetic component is this XOR topology the fundamental part of?




Question 9: How is XOR logic utilized in data transmission applications?




Question 10: What voltage level is indicated as the threshold for a High logic level (LED ON) in this context?




Carlos Núñez Zorrilla
Carlos Núñez Zorrilla
Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

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