Practical case: 0 to 9 BCD Decimal Counter

Objective and use case

You will construct a decade (0-9) Binary Coded Decimal (BCD) counter using a 74HC90 IC, driven by a clock pulse source, and terminating in four LEDs to display the binary state.

This circuit is highly useful in real-world applications for:
* Building fundamental digital clock circuits (seconds and minutes counters).
* Event counting systems on manufacturing lines.
* Understanding logic state machines and frequency dividers (divide-by-10).
* Creating foundational timing circuits without the need for microcontrollers.

Expected outcome:
* The circuit will automatically count from 0000 (decimal 0) to 1001 (decimal 9) in binary.
* A transient validation will show the CLK signal alongside the state of QA, QB, QC, and QD.
* Pressing the manual reset button will immediately pull the RST node HIGH and force the outputs to 0000.
* The LEDs will visually blink according to their respective binary significance (QA toggling fastest, QD toggling slowest).

Target audience and level: Intermediate electronics students learning sequential logic and counters.

Materials

• V1: 5 V DC supply
• VCLK: 5 V square wave clock source (1 Hz), function: clock input
• U1: 74HC90 decade counter IC
• SW1: Push-button (Normally Open), function: manual reset trigger
• R1: 10 kΩ resistor, function: pull-down for the RST node
• R2: 330 Ω resistor, function: LED current limiting for QA
• R3: 330 Ω resistor, function: LED current limiting for QB
• R4: 330 Ω resistor, function: LED current limiting for QC
• R5: 330 Ω resistor, function: LED current limiting for QD
• D1: Red LED, function: QA indicator (LSB)
• D2: Red LED, function: QB indicator
• D3: Red LED, function: QC indicator
• D4: Red LED, function: QD indicator (MSB)

Conceptual block diagram

Measurements and tests

• Clock validation: Monitor the CLK node on an oscilloscope or transient plot to verify a consistent square wave.
• Counting sequence: Plot QA, QB, QC, and QD simultaneously. Observe that QA toggles on every falling edge of CLK, and that the binary state progresses correctly from 0000 to 1001.
• BCD Wrap-around: Watch the transition after 1001 (decimal 9). The very next clock pulse should automatically return all outputs (QA–QD) back to 0000 (decimal 0) instead of proceeding to 1010 (decimal 10).
• Manual Reset: While the counter is at any non-zero state (e.g., 0101), actuate SW1. Observe that the RST node spikes to 5 V, forcing QA, QB, QC, and QD to 0000 immediately, ignoring the CLK signal until the button is released.

Common mistakes and how to avoid them

• Forgetting to connect QA to CKB: The 74HC90 is internally split into a divide-by-2 and a divide-by-5 section. If you do not bridge pin 12 (QA) to pin 1 (CKB), the IC will only count from 0 to 1 and stop, or will not generate the proper BCD sequence.
• Leaving reset pins floating: CMOS logic inputs (like the 74HC series) must never be left disconnected. Leaving MS1, MS2, or the MR pins floating will cause the counter to randomly reset due to ambient electrical noise. Ensure they are tied firmly to 0 or managed via a pull-down resistor.
• Swapping the output bits: Reading the LEDs in the wrong order is very common. Always remember that QA is the Least Significant Bit (LSB, toggles fastest) and QD is the Most Significant Bit (MSB, toggles slowest).

Troubleshooting

• Symptom: All LEDs remain entirely off, and the counter never advances.
  • Cause: The Master Reset (MR1 and MR2) or Master Set (MS1 and MS2) pins might be receiving a logic HIGH.
  • Fix: Check that SW1 is not stuck closed, ensure R1 (pull-down) is properly connected to ground, and verify MS1/MS2 are wired directly to 0.
• Symptom: The counter counts wildly or skips numbers unexpectedly.
  • Cause: The clock signal (CLK) lacks debouncing, or there is missing power supply decoupling.
  • Fix: If using a mechanical switch for a clock instead of a clean generator, add a hardware debounce circuit (RC + Schmitt trigger). Additionally, place a 100 nF capacitor directly between VCC and GND near the IC.
• Symptom: The count goes up to 5 and resets (0, 1, 2, 3, 4, 0…).
  • Cause: The clock inputs are wired backwards. The clock is entering CKB and cascading into CKA.
  • Fix: Ensure the external clock goes exclusively to CKA (pin 14) and QA bridges to CKB (pin 1).