Implementation Code

The implementation is divided into two complete, synthesizable Verilog modules: the I2S receiver and the envelope detector/alarm logic.

1. I2S Receiver Module (i2s_rx.v)

This module generates the necessary I2S clocks from a 50 MHz system clock and shifts in the 24-bit audio samples from the INMP441.

module i2s_rx (
    input wire clk_50m,
    input wire rst_n,
    output wire i2s_sck,
    output wire i2s_ws,
    input wire i2s_sd,
    output reg [23:0] left_data,
    output reg data_valid
);
    reg [3:0] bclk_div;
    reg bclk;
    reg [5:0] bit_cnt;
    reg [23:0] shift_reg;

    // Generate I2S Bit Clock (SCK)
    always @(posedge clk_50m or negedge rst_n) begin
        if (!rst_n) begin
            bclk_div <= 4'd0;
            bclk <= 1'b0;
        end else begin
            bclk_div <= bclk_div + 1'b1;
            if (bclk_div == 4'd7) begin
                bclk <= ~bclk;
            end
        end
    end

    assign i2s_sck = bclk;
    // Word Select toggles every 32 bits (64 bits per frame)
    assign i2s_ws = bit_cnt[5]; 

    // Shift in I2S Data
    always @(negedge bclk or negedge rst_n) begin
        if (!rst_n) begin
            bit_cnt <= 6'd0;
            shift_reg <= 24'd0;
            left_data <= 24'd0;
            data_valid <= 1'b0;
        end else begin
            bit_cnt <= bit_cnt + 1'b1;
            data_valid <= 1'b0;

            // INMP441 outputs data MSB first, delayed by 1 BCLK after WS transition
            if (bit_cnt >= 6'd1 && bit_cnt <= 6'd24) begin
                shift_reg <= {shift_reg[22:0], i2s_sd};
            end

            // Latch data at the end of the left channel slot
            if (bit_cnt == 6'd31) begin
                left_data <= shift_reg;
                data_valid <= 1'b1;
            end
        end
    end
endmodule

2. Envelope Detector and Alarm Module (noise_monitor.v)

This module takes the signed 24-bit audio data, calculates the absolute value (rectification), manages a peak-hold algorithm with decay for display purposes, and triggers the alarm LED if the threshold is breached.

module noise_monitor (
    input wire clk_50m,
    input wire rst_n,
    input wire signed [23:0] audio_data,
    input wire data_valid,
    output reg alarm_led,
    output reg [15:0] peak_level
);
    parameter THRESHOLD = 24'd1000000;
    parameter DECAY_RATE = 16'd10;

    reg [23:0] abs_data;
    reg [31:0] decay_timer;

    always @(posedge clk_50m or negedge rst_n) begin
        if (!rst_n) begin
            alarm_led <= 1'b0;
            peak_level <= 16'd0;
            abs_data <= 24'd0;
            decay_timer <= 32'd0;
        end else begin
            if (data_valid) begin
                // Rectify signal (Absolute value)
                if (audio_data[23]) begin
                    abs_data <= -audio_data;
                end else begin
                    abs_data <= audio_data;
                end

                // Trigger threshold alarm
                if (abs_data > THRESHOLD) begin
                    alarm_led <= 1'b1;
                end else begin
                    alarm_led <= 1'b0;
                end

                // Peak hold logic using the upper 16 bits
                if (abs_data[23:8] > peak_level) begin
                    peak_level <= abs_data[23:8];
                    decay_timer <= 32'd0;
                end
            end

            // Decay peak level over time for visual display updates
            decay_timer <= decay_timer + 1'b1;
            if (decay_timer == 32'd500000) begin // Trigger decay every 10ms at 50MHz
                decay_timer <= 32'd0;
                if (peak_level > DECAY_RATE) begin
                    peak_level <= peak_level - DECAY_RATE;
                end else begin
                    peak_level <= 16'd0;
                end
            end
        end
    end
endmodule

Compilation

To synthesize the design using open-source tools like Yosys, you can run the following command in your terminal:

yosys -p "synth_ice40 -top noise_monitor -json noise_monitor.json" i2s_rx.v noise_monitor.v