Building a Quadrature Encoder RPM Meter with Lattice ECP5

Objective and use case

What you’ll build: A digital Revolutions Per Minute (RPM) meter that reads a mechanical quadrature encoder using a Lattice ECP5 FPGA, calculating rotational speed and displaying it in real-time with sub-millisecond latency on an external LED bar.

Why it matters / Use cases

Low-Speed Conveyor Monitoring: Provides independent verification of assembly line belt speeds with <1ms latency, acting as a reliable low-speed shaft monitor.
Manual Crank/Winch Testing: Acts as a measurement aid to ensure operators do not exceed safe manual winding speeds (e.g., 0-120 RPM) on mechanical hoists or laboratory tensioners.
Stepper Motor Tuning: Offers physical, independent verification of actual rotational speed during low-frequency tuning, bypassing microcontroller software estimates.
Hardware Signal Processing: Demonstrates crucial FPGA concepts including shift-register synchronization, mechanical switch debouncing (~5ms filter), and fixed-time window frequency measurement.

Expected outcome

A robust Verilog module that continuously samples the KY-040 encoder’s A and B channels at 50MHz without metastability.
A digital state machine that filters mechanical bounce and accurately decodes quadrature step direction.
A real-time RPM calculation and LED bar display pipeline utilizing <1% of the ECP5 FPGA logic resources (LUTs).

Audience: Embedded hardware engineers and FPGA developers; Level: Intermediate

Architecture/flow: KY-040 Encoder → 2-Stage Flip-Flop Synchronizer → Debounce Filter → Quadrature Decoder → Fixed-Window RPM Counter → LED Bar Display Driver

Educational validation note

Before publication, this case passed the Prometeo automated validation gate with status PASS. For this FPGA/ULX3S profile, the synthesizable Verilog blocks were checked with Yosys (read_verilog) and the Verilog design/test set was linted with Verilator. The validator also checked code-block structure, copy/paste-safe ASCII command options, unsupported stacks, and availability of the ULX3S/ECP5 toolchain (yosys, nextpnr-ecp5, ecppack, openFPGALoader).

Published validation evidence

Automatic result: PASS.
Parsed structure: 3 sections, 1 tables and 2 code blocks detected before publication.
Checked code: 2 Verilog/Yosys-Verilator.
Supported catalog: the article text was checked against Prometeo’s validation-capable device profiles, and unsupported stacks block publication.
Report findings: no blocking findings.

This validation confirms syntax and tool compatibility for the published code, but it does not replace physical testing on your exact ULX3S board revision, pin-constraint file and real wiring.

Educational safety note

This project is an educational prototype, not a certified product. Before powering the setup, verify the pinout of your exact ULX3S board revision, keep FPGA I/O signals at 3.3 V, never connect 5 V directly to I/O pins, disconnect power before changing wiring, and use suitable external supplies for loads, motors or servos while sharing ground only when the wiring requires it.

Conceptual block diagram

High-level view: what enters the system, what each block processes, and what comes out.

Functional architecture

KY-040 Encoder

2-Stage Flip-Flop Synchronizer

Debounce Filter

Quadrature Decoder

Fixed-Window RPM Counter

LED Bar Display Driver

Conceptual signal and responsibility flow between device blocks.

Validation path

Source code

Verilator

Yosys

Hardware implementation

Conceptual summary of the tools used to check the published material.

Hardware Setup

This tutorial targets the Radiona ULX3S with a Lattice ECP5-85F FPGA.

Signal Name	ULX3S Pin	I/O Standard	Hardware Connection
`clk_25mhz`	G2	LVCMOS33	Onboard 25MHz Oscillator
`enc_a`	B11	LVCMOS33 (Pull-up)	KY-040 CLK Pin (GPIO `gp[0]`)
`enc_b`	C11	LVCMOS33 (Pull-up)	KY-040 DT Pin (GPIO `gp[1]`)
`led[0]`	H3	LVCMOS33	Onboard LED 0
`led[1]`	E1	LVCMOS33	Onboard LED 1
`led[2]`	E2	LVCMOS33	Onboard LED 2
`led[3]`	D1	LVCMOS33	Onboard LED 3
`led[4]`	D2	LVCMOS33	Onboard LED 4
`led[5]`	C1	LVCMOS33	Onboard LED 5
`led[6]`	C2	LVCMOS33	Onboard LED 6
`led[7]`	B2	LVCMOS33	Onboard LED 7

Verilog Implementation

The design uses a 1-second time window generated from the 25MHz system clock. It synchronizes the asynchronous encoder inputs, debounces them, and counts the pulses. A standard KY-040 encoder generates 20 pulses per revolution.

Synthesizable Source Code

Save the following code as top.v.

Public preview of the validated file. The complete source is shown to members and in PDF/Print.

/* top.v */
module top #(
    parameter CLK_FREQ = 25000000,
    parameter DEBOUNCE_CYCLES = 50000
) (
    input  wire clk_25mhz,
    input  wire enc_a,
    input  wire enc_b,
    output wire [7:0] led
);

    // Synchronization registers to prevent metastability
    reg [2:0] sync_a;
    always @(posedge clk_25mhz) begin
        sync_a <= {sync_a[1:0], enc_a};
    end

    // Debounce logic for Channel A
    reg clean_a;
    reg [15:0] debounce_cnt_a;

    initial begin
        clean_a = 1'b1;
        debounce_cnt_a = 16'd0;
    end

    always @(posedge clk_25mhz) begin
        if (sync_a[2] == clean_a) begin
            debounce_cnt_a <= 16'd0;
        end else begin
            debounce_cnt_a <= debounce_cnt_a + 16'd1;
            if (debounce_cnt_a == DEBOUNCE_CYCLES) begin
                clean_a <= sync_a[2];
                debounce_cnt_a <= 16'd0;
            end
        end
    end

    // Edge detection on debounced Channel A
    reg clean_a_prev;
    initial clean_a_prev = 1'b1;

    always @(posedge clk_25mhz) begin
        clean_a_prev <= clean_a;
    end
// ...

    wire step_pulse = (clean_a == 1'b1 && clean_a_prev == 1'b0);

    // 1-Second Timer and Pulse Counter
    reg [24:0] timer;
    reg [15:0] pulse_count;
    reg [15:0] saved_pulses;

    initial begin
        timer = 25'd0;
        pulse_count = 16'd0;
        saved_pulses = 16'd0;
    end

    always @(posedge clk_25mhz) begin
        if (timer == CLK_FREQ - 1) begin
            timer <= 25'd0;
            saved_pulses <= pulse_count;
            pulse_count <= 16'd0;
        end else begin
            timer <= timer + 25'd1;
            if (step_pulse) begin
                pulse_count <= pulse_count + 16'd1;
            end
        end
    end

    // Calculate RPM: (Pulses per second * 60) / 20 pulses per revolution = Pulses * 3
    wire [15:0] rpm = saved_pulses * 16'd3;

🔒 This content is premium. With the monthly subscription (7-day free trial) you can unlock the full didactic material and the print-ready PDF pack.🔓 Unlock it — 7-day free trial

/* top.v */
module top #(
    parameter CLK_FREQ = 25000000,
    parameter DEBOUNCE_CYCLES = 50000
) (
    input  wire clk_25mhz,
    input  wire enc_a,
    input  wire enc_b,
    output wire [7:0] led
);

    // Synchronization registers to prevent metastability
    reg [2:0] sync_a;
    always @(posedge clk_25mhz) begin
        sync_a <= {sync_a[1:0], enc_a};
    end

    // Debounce logic for Channel A
    reg clean_a;
    reg [15:0] debounce_cnt_a;

    initial begin
        clean_a = 1'b1;
        debounce_cnt_a = 16'd0;
    end

    always @(posedge clk_25mhz) begin
        if (sync_a[2] == clean_a) begin
            debounce_cnt_a <= 16'd0;
        end else begin
            debounce_cnt_a <= debounce_cnt_a + 16'd1;
            if (debounce_cnt_a == DEBOUNCE_CYCLES) begin
                clean_a <= sync_a[2];
                debounce_cnt_a <= 16'd0;
            end
        end
    end

    // Edge detection on debounced Channel A
    reg clean_a_prev;
    initial clean_a_prev = 1'b1;

    always @(posedge clk_25mhz) begin
        clean_a_prev <= clean_a;
    end

    wire step_pulse = (clean_a == 1'b1 && clean_a_prev == 1'b0);

    // 1-Second Timer and Pulse Counter
    reg [24:0] timer;
    reg [15:0] pulse_count;
    reg [15:0] saved_pulses;

    initial begin
        timer = 25'd0;
        pulse_count = 16'd0;
        saved_pulses = 16'd0;
    end

    always @(posedge clk_25mhz) begin
        if (timer == CLK_FREQ - 1) begin
            timer <= 25'd0;
            saved_pulses <= pulse_count;
            pulse_count <= 16'd0;
        end else begin
            timer <= timer + 25'd1;
            if (step_pulse) begin
                pulse_count <= pulse_count + 16'd1;
            end
        end
    end

    // Calculate RPM: (Pulses per second * 60) / 20 pulses per revolution = Pulses * 3
    wire [15:0] rpm = saved_pulses * 16'd3;

    // LED Bar Graph Display (Thermometer Code)
    reg [7:0] led_reg;
    always @(*) begin
        led_reg = 8'b00000000;
        if (rpm >= 16'd15)  led_reg[0] = 1'b1;
        if (rpm >= 16'd30)  led_reg[1] = 1'b1;
        if (rpm >= 16'd45)  led_reg[2] = 1'b1;
        if (rpm >= 16'd60)  led_reg[3] = 1'b1;
        if (rpm >= 16'd75)  led_reg[4] = 1'b1;
        if (rpm >= 16'd90)  led_reg[5] = 1'b1;
        if (rpm >= 16'd105) led_reg[6] = 1'b1;
        if (rpm >= 16'd120) led_reg[7] = 1'b1;
    end

    assign led = led_reg;

endmodule

Testbench

Save the following code as tb_top.v. The testbench overrides the module parameters to drastically shorten the 1-second counting window for practical simulation times.

/* tb_top.v */
`timescale 1ns/1ps

module tb_top;
    reg clk;
    reg enc_a;
    reg enc_b;
    wire [7:0] led;

    // Instantiate with simulation-friendly parameters
    // CLK_FREQ = 2500 (100us window instead of 1s)
    // DEBOUNCE_CYCLES = 5 (instead of 50000)
    top #(
        .CLK_FREQ(2500),
        .DEBOUNCE_CYCLES(5)
    ) dut (
        .clk_25mhz(clk),
        .enc_a(enc_a),
        .enc_b(enc_b),
        .led(led)
    );

    initial begin
        clk = 0;
        forever #20 clk = ~clk; // 25MHz clock (40ns period)
    end

    initial begin
        $dumpfile("tb_top.vcd");
        $dumpvars(0, tb_top);

        enc_a = 1;
        enc_b = 1;

        #1000;

        // Simulate multiple encoder steps to register an RPM
        repeat (10) begin
            enc_a = 0; #400; // Exceeds debounce (5 * 40ns = 200ns)
            enc_b = 0; #400;
            enc_a = 1; #400;
            enc_b = 1; #400;
        end

        // Wait for the timer window to expire (100us = 100,000ns)
        #150000;

        $finish;
    end
endmodule

Pin Constraints

Save the following code as ulx3s.lpf.

# ulx3s.lpf
LOCATE COMP "clk_25mhz" SITE "G2";
IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS

Find this product and/or books on this topic on Amazon

Go to Amazon

As an Amazon Associate, I earn from qualifying purchases. If you buy through this link, you help keep this project running.

Carlos Núñez Zorrilla

Electronics & Computer Engineer

Telecommunications Electronics Engineer and Computer Engineer (official degrees in Spain).

Follow me:

Who we are

Practical case: Quadrature Encoder RPM Meter with ULX3S

Building a Quadrature Encoder RPM Meter with Lattice ECP5

Objective and use case

Why it matters / Use cases

Expected outcome

Educational validation note

Published validation evidence

Educational safety note

Conceptual block diagram

Functional architecture

Validation path

Hardware Setup

Verilog Implementation

Synthesizable Source Code

Testbench

Pin Constraints

Quick Quiz

Practical case: Quadrature Encoder RPM Meter with ULX3S

Building a Quadrature Encoder RPM Meter with Lattice ECP5

Objective and use case

Why it matters / Use cases

Expected outcome

Educational validation note

Published validation evidence

Educational safety note

Conceptual block diagram

Functional architecture

Validation path

Hardware Setup

Verilog Implementation

Synthesizable Source Code

Testbench

Pin Constraints

Quick Quiz

Related Posts