Practical case: SPI Tester for 74HC595 with ULX3S

/* spi_master.v */
module spi_master (
    input wire clk,          // System clock
    input wire rst,          // Active high reset
    input wire start,        // Pulse high to start transmission
    input wire [7:0] data_in,// Data to transmit
    output reg mosi,         // Master Out Slave In
    output reg sck,          // Serial Clock
    output reg latch,        // Register Latch (RCLK)
    output reg busy          // High while transmitting
);

    reg [3:0] bit_cnt;
    reg [7:0] shift_reg;
    reg [2:0] state;

    localparam IDLE  = 3'd0;
    localparam LOAD  = 3'd1;
    localparam LOW   = 3'd2;
    localparam HIGH  = 3'd3;
    localparam LATCH = 3'd4;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            mosi <= 1'b0;
            sck <= 1'b0;
            latch <= 1'b0;
            busy <= 1'b0;
            bit_cnt <= 4'd0;
            shift_reg <= 8'd0;
            state <= IDLE;
        end else begin
            case (state)
                IDLE: begin
                    latch <= 1'b0;
                    sck <= 1'b0;
                    if (start) begin
                        shift_reg <= data_in;
                        busy <= 1'b1;
                        bit_cnt <= 4'd8;
                        state <= LOAD;
                    end else begin
                        busy <= 1'b0;
                    end
                end

                LOAD: begin
                    mosi <= shift_reg[7];
                    shift_reg <= {shift_reg[6:0], 1'b0};
                    sck <= 1'b0;
                    state <= HIGH;
                end

                HIGH: begin
                    sck <= 1'b1;
                    bit_cnt <= bit_cnt - 4'd1;
                    state <= LOW;
                end

                LOW: begin
                    sck <= 1'b0;
                    if (bit_cnt == 4'd0) begin
                        state <= LATCH;
                    end else begin
                        state <= LOAD;
                    end
                end

                LATCH: begin
                    latch <= 1'b1;
                    state <= IDLE;
                end

                default: state <= IDLE;
            endcase
        end
    end
endmodule

/* tester_top.v */
module tester_top #(
    parameter TIMER_BITS = 24 // Can be reduced for simulation speed
)(
    input wire clk_25mhz,
    input wire [2:1] btn,
    output wire spi_mosi,
    output wire spi_sck,
    output wire spi_latch
);

    wire rst = btn[1];
    wire mode_btn = btn[2];

    // Clock dividers
    reg [TIMER_BITS-1:0] timer;
    reg [3:0] spi_clk_div;
    wire spi_clk = spi_clk_div[3];

    always @(posedge clk_25mhz) begin
        timer <= timer + 1;
        spi_clk_div <= spi_clk_div + 4'd1;
    end

    wire update_tick = (timer == 0);

    // Button Debouncer
    reg [15:0] debounce_shift;
    reg mode_btn_clean;
    reg mode_btn_last;
    wire mode_pulse;

    always @(posedge clk_25mhz) begin
        debounce_shift <= {debounce_shift[14:0], mode_btn};
        if (debounce_shift == 16'hFFFF) mode_btn_clean <= 1'b1;
        else if (debounce_shift == 16'h0000) mode_btn_clean <= 1'b0;

        mode_btn_last <= mode_btn_clean;
    end

    assign mode_pulse = mode_btn_clean & ~mode_btn_last;

    // Pattern Generator State Machine
    reg [1:0] mode;
    reg [7:0] current_pattern;
    reg [2:0] walk_idx;

    always @(posedge clk_25mhz or posedge rst) begin
        if (rst) begin
            mode <= 2'd0;
            walk_idx <= 3'd0;
            current_pattern <= 8'h01;
        end else begin
            if (mode_pulse) begin
                mode <= mode + 2'd1;
                walk_idx <= 3'd0;
            end

            if (update_tick) begin
                case (mode)
                    2'd0: begin // Mode 0: Walking One
                        current_pattern <= (8'h01 << walk_idx);
                        walk_idx <= walk_idx + 3'd1;
                    end
                    2'd1: begin // Mode 1: Alternating
                        current_pattern <= (walk_idx[0]) ? 8'hAA : 8'h55;
                        walk_idx <= walk_idx + 3'd1;
                    end
                    2'd2: begin // Mode 2: All On
                        current_pattern <= 8'hFF;
                    end
                    2'd3: begin // Mode 3: All Off
                        current_pattern <= 8'h00;
                    end
                endcase
            end
        end
    end

    // SPI Master Instantiation
    wire spi_busy;
    reg spi_start;
    reg spi_start_d;

    // Generate a single-cycle start pulse in the spi_clk domain
    always @(posedge spi_clk) begin
        spi_start_d <= update_tick;
        spi_start <= update_tick & ~spi_start_d;
    end

    spi_master u_spi (
        .clk(spi_clk),
        .rst(rst),
        .start(spi_start),
        .data_in(current_pattern),
        .mosi(spi_mosi),
        .sck(spi_sck),
        .latch(spi_latch),
        .busy(spi_busy)
    );

endmodule